JPH0618365B2 - Timing method - Google Patents

Description

The present invention relates to a timing system, and more particularly to a timing system used for digital transmission systems such as backbone transmission systems, public networks, subscriber systems and the like.

[Conventional technology]

The progress of transmission technology using optical fiber as a transmission medium is remarkable, and the transmission information amount is several hundred Mbps
Transmission of several Gbps is becoming possible. Further, a parallel transmission method is considered as one method for realizing a wider band transmission system.

FIG. 3 is a block diagram showing an example of the configuration of a conventional timing system used in the digital parallel transmission system. In the figure, 301 _{1 to} 301 _n are data input lines, 302
Is a clock input line, 303 is a latch circuit, 304 is a selector circuit, 305 is a control signal input line, and 306 _{1 to} 306
₃ is a gate, 307 _{1 to} 307 _n are data output lines, 30
Reference numeral 8 is a clock output line. Here clock input line 30
Clock signal input from the 2 and a data input line 301 ₁
The data signals input from ˜301 _n have the same repetition period (T _o = 1 / f _o ), but are not always phase-synchronized. Therefore, the N data signals cannot be immediately retimed using this clock signal. Therefore, the input clock signal is applied to the gates 306 ₁ to 30 having a specific gate delay.
6 ₃ produces a four-phase clock signals through the selector circuit 3 which receives the clock signal of the generated four-phase
In 04, the one-phase clock signal is selected from the four-phase clock signals based on the control signal input from the control signal input line 305. Using this selected clock signal, the latch circuit 303 operates the N data input lines 301 ₁
˜301 _n input data signals are identified and retimed. As described above, in the circuit of FIG. 3, since it is possible to select and use one phase from the four-phase clock signals as the clock signal used for retiming,
Even if the clock signal input from the clock input line 302 and the data signals input from the N data input lines 301 _{1 to} 301 _n are not in phase synchronization, retiming of these data signals without error is performed. Is possible.

[Problems to be solved by the invention]

In the above-described conventional timing method, four-phase clock signals are generated by a non-logical operation using the gates 306 _{1 to} 306 _n having inherent gate delays, and one phase is selected from the four-phase clock signals. Since N data signals are retimed, the gate delay amount of the gates 306 _{1 to} 306 _n is an important factor in retiming the data signals, and the repetition frequency (f _o ) had to adjust the gate delay amount. Further, generally, the data signals input from the N data input lines 301 _{1 to} 301 _n include skew between data (phase distortion) and delay variation between signals. For this reason, the clock signals selected by the selector circuit 304 are all N data input lines 30.
It was not always possible to identify the information of 1 _{1 to} 301 _{n under} the optimum phase condition.

After selecting the optimum phase clock for the information on each data input line and identifying the information for each signal line,
A method of retiming the information between the N data input lines 301 _{1 to} 301 _n with a common clock signal and ensuring parallel bit synchronization is also conceivable. However, in this method, the phase control of the common clock for parallel bit synchronization is complicated.

An object of the present invention is to have a simple circuit configuration that solves these problems, does not generate a retiming clock signal for data by a non-logical operation, and does not depend on the repetition frequency of input data, An object of the present invention is to provide a timing method in which information of all N data input lines 301 _{1 to} 301 _n is identified at optimum timing and parallel bit synchronization is easily ensured.

[Means for solving problems]

The timing system of the present invention is a parallel transmission system in which a digital signal is transmitted using N signal lines, the internal state is initialized using each of the N signal lines, and the signal lines are repeated twice. N divide-by-two frequency divider circuits that divide a clock signal having a frequency component into two, and N delay circuits that delay the output signals of each of the N divide-by-2 circuits by half a clock of the clock signal, Output signals of the N discrimination circuits that retime the N signal lines by using the output signals of the N delay circuits, and output signals of the N discrimination circuits by using the clock of the divide-by-2 circuit. And a means for achieving parallel bit synchronization of.

〔Example〕

Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of the timing system of the present invention, and FIG. 2 is a time chart showing timing waveforms of signals at respective parts in FIG.

In FIG. 1, the letters a, b, c, d, e, f, g, h indicate the signal positions of the timing waveform in the timing chart of FIG. 2, 101 _{1 to} 101 _n are data input lines, and 102 Is a clock input line, 103 _{1 to} 103 _n is an identification circuit including a D flip-flop (DF / F), and 104 ₁ to 10
4 _{n + 1} is composed of T flip-flops (T-F / F) 2
A frequency divider circuit, 105 _{1 to} 105 _n are D-F / Fs, 106 is an inverter circuit, 107 is a latch circuit, and 108 ₁ to 10
8 _n is a data output line, and 109 is a clock output line.
Here the clock signal input from the clock input line 102 is twice the repetition frequency (2f _o of the data signal input from the data input line _{101 1 ~101 n, f o =} 1 /
T). The divide-by-two frequency divider circuits 104 _{1 to} 104 _n are clocks each having a frequency component twice as high as that of the data signal while resetting the internal state at the rising edge of the data signal input from each of the data input lines 101 _{1 to} 101 _n. Divide the signal by two. The divide-by-two circuit 104 _{n + 1} divides the frequency of the clock signal having a repetition frequency of 2f _o input from the clock input line 102 by two. On the other hand, the clock signal having the repeating frequency of 2f _o input from the clock input line is inverted in phase by the inverter circuit 106. Using this phase-inverted clock signal, each D-F / F 105 _{1 to} 105 _n is a repetition frequency which is an output signal of the divide-by-two frequency divider 104 _{1 to} 104 _n.
Punch out the clock signal at f _o . This allows DF / F1
The output signals of 05 _{1 to} 105 _n are the frequency _dividing circuits 104 ₁ to 104 _1.
The clock signal is delayed by T / 4 with respect to the output signal of 04 _n . The identification circuits 103 _{1 to} 103 _n have D-
The data signals input from the data input lines 101 _{1 to} 101 _n are identified using the clock signals output from the F / Fs 105 _{1 to} 105 _n . Further, the identification circuits 103 ₁ to 10
The output signal of 3 _n becomes the input of the latch circuit 107 and is retimed using the clock signal of the repetition frequency f _o which is the output of the divide-by-2 circuit 104 _{n + 1} , and the data output line 10
8 _{1 to} 108 _n are output.

In the timing chart of FIG. 2, point A is the start time of this timing chart. a ₁ ~a _n is a data signal input from the data input line ₁₀₁ 1 to 101 _n,
b is a clock signal input from the clock input line 102, c is an output signal of the inverter circuit 106, and a _{1 to} d _n
Is an output signal of the frequency _dividing circuit 104 _{1 to} 104 _n , e _{1 to} e
_n is the output signal of the D-F / F 105 _{1 to} 105 _n , f ₁ to
f _n is an output signal of the identification circuits 103 _{1 to} 103 _n , g ₁ to
g _n is the output signal of the latch circuit 107, and h is the frequency _dividing circuit 1
04 _{n + 1} output signal.

The data input lines 101 ₁ to 10 ₁ to 10 will be described with reference to FIGS. 1 and 2.
A process of correctly identifying a data signal input from 1 _n and ensuring parallel bit synchronization will be described. N
Each of the two divide-by-2 circuits 104 _{1 to} 104 _n resets the internal state at the rising edge of the input data signals a _{1 to} a _n , and supplies the supplied clock signal of the repetition frequency 2f _o to 2
Divide. Generally, two phases (2 phases (0 phase or π phase) in the frequency divider circuit
Although the output phase of is possible, the reset process here is 2
This corresponds to automatically selecting the clock signal of one of the phases. That is, the divide-by-2 circuit 104 _{1 to} 104 _n
As the output of 0, a 0-phase or π-phase clock signal (output signals d _{1 to} d _n ) appears. Output signals d _{1 to} d _n
Becomes an input signal of D-F / F 105 _{1 to} 105 _{n and} is retimed by the output signal c of the inverter circuit 106. Each of the clock signal _e 1 to e _n are D-F / F
Output signals of 105 _{1 to} 105 _n , and output signals d ₁ to
T / 4 phase by the delayed signal as compared to d _n. Rise of each of the clock signal _e 1 to e _n are always T / 4~3T / 4 delay from each of the change point of the input data signal _a 1 ~a _n inputted from the data input line ₁₀₁ 1 to 101 _n since will appear in the phase point, the input data signal a ₁ by using these clock signals e ₁ to e _n
Each of ~a _n it is possible to identify with no error and phase margin (output signal _f 1 _~f n). Here, the output signals f _{1 to} f _n have two phases (0 phase or π phase).
Although it will appear, by using the output clock signal h of the frequency _dividing circuit 104 _{n + 1} , the output signals f ₁ to
f _n is retimed and parallel bit synchronization is secured (output signals g _{1 to} g _n ).

As described above, the embodiment shown in FIG. 1 has been described, but the present invention is not limited to these combinations, and for example, the output signal of the divide-by-two frequency _dividing circuit 104 _n is set to the latch clock of the latch circuit 107. A configuration used as a signal is also possible. The clock signal generation method which is inputted from the clock input line 102, for example, after the timing signal of a repetition frequency f _o from a clock signal input from the data signal line 101 _n self extraction, repetition frequency 2f with a frequency doubler method of generating a _o of the clock signal, system having a clock signal of a repetition frequency 2f _o as the system clock, are conceivable clock signal external supply system such various schemes of repetition frequency 2f _o. Furthermore, even when a clock signal having a repetition frequency component N times the input data signal is used, the same effect as that of the present invention is expected.

〔The invention's effect〕

As described above, according to the timing method of the present invention, without depending on the repetition frequency of input data,
There is an effect that the parallel bit synchronization of the data signals input in parallel can be secured only by using a simple logical operation.

The present invention relates to a timing system in a digital transmission system, and is expected to be applied to an optical fiber transmission system, which has a higher speed and a larger capacity, in particular, an optical parallel transmission system by fiber multiplexing or wavelength multiplexing in the future. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a timing system of the present invention, FIG. 2 is a timing chart showing timing waveforms of signals of respective parts in FIG. 1, and FIG. 3 is a structural example of a conventional timing system. It is a block diagram. 101 _{1 to} 101 _n , 301 _{1 to} 301 _n ... Data input line, 102, 302 ... Clock input line, 103 ₁ to
103 _n ...... Identification circuit, 104 _{1 to} 104 _{n + 1} ...... 2 frequency divider circuit, 105 _{1 to} 105 _n ...... D-F / F, 106 ......
Inverter circuit, 107, 303 ... Latch circuit, 10
_{8 1 ~108 n, 307 1 ~307} n ...... data output lines, 109,308 ...... clock output line, 304 ...... selector circuit, 305 ...... control signal input line, ₃₀₆ 1-3
06 ₃ …… Gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display area H04L 29/00

Claims (1)

[Claims] 1. In a parallel transmission system for transmitting a digital signal using N signal lines, an internal state is initialized by using each of the N signal lines, and a repetition frequency twice that of the signal lines is used. A divide-by-two N-divider circuit that divides a clock signal having a component into two, and N delay circuits that delay the output signals of each of the N divide-by-2 circuits by half a clock of the clock signal; N identification circuits that retime each of the N signal lines using the output signals of the N delay circuits, and the N identification circuits that use the clocks of the divide-by-2 circuit.
And a means for establishing parallel bit synchronization of the output signals of the individual identification circuits.