KR100258086B1 - High speed digital data retiming device - Google Patents

Abstract

PURPOSE: An apparatus for re-timing high-speed digital data is provided to re-time data without loss of the data by providing the apparatus for re-timing high-speed digital data having large range for input allowable jitter. CONSTITUTION: A clock pulse generator(100) generates n multiple delay clock pulses having n phases. A transition detector(200) generates and outputs data transition detection signals which select one or more clock pulses where transition is generated. A data transition detection signal monitor(300) monitors the data transition detection signal and generates a clock pulse control signal. A D flipflop(500) re-times the serial data inputted form exterior to the clock pulse mixed by a clock pulse mixer(400). A re-timing buffer(600) re-times the re-timed data to the clock from exterior to synchronize and output it with external clock.

Description

High speed digital data retiming device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for retiming high speed binary data bits in which alignment jitter exists in a high speed digital data transmission system, and more particularly, to a high speed digital data retiming device having a large input allowable jitter. will be.

Binary data bits that are transmitted at high speed have static skews caused by delay differences between retiming clock pulses and data bits, and jitters generated by changes in time and temperature. In particular, high-speed digital data transmission systems often operate the entire system in synchronization with system clock pulses. In this case, if the phase between the data and the clock pulse is not sufficiently separated to satisfy the setup time and the hold time of the flip-flop, a condition of instability occurs and the data cannot be retimed stably.

In the conventional high speed digital data retiming apparatus, when the number of selection signals generated by the clock pulse selection signal generator reaches three or more, the clock pulse synthesizer generates the synthesis clock necessary for retiming using three or more clocks.

1 is a block diagram of a conventional high-speed digital data retiming apparatus, in which a high-speed binary data bit having jitter is retimed and output in synchronization with an external clock.

First, the multi-phase clock pulse generator 10 delays an external clock pulse by using a plurality of delay elements to generate and output clock pulses having a number of phases corresponding to the number of delay elements, and the clock pulse selection signal generator 20 A clock pulse that receives a multi-phase clock output from the multi-phase clock pulse generator 10 and data bits from the outside, and transitions near the center of the data bit interval (unit interval) input from the outside among the multi-phase clock pulses. Outputs a selection signal for selecting one or more, and the clock pulse synthesizer 30 outputs a clock pulse selection signal output from the clock pulse selection signal generator 20 and a multi-phase output from the multi-phase clock pulse generator 10. Even when the clock pulse is input, the transition of the clock pulse occurs in the center of the externally input data bit interval. Synthesized clock pulses. The D-flip-flop 40 retimes externally input data by the synthesized clock pulse output from the clock pulse synthesizer 30, and the buffer buffer 50 is used at the D-flip-flop 40. The retimed data is output in synchronization with an external clock pulse.

As described above, in the conventional high-speed digital data retiming apparatus, when a plurality of clocks are input to form a synthesized clock, the synthesized clock has a duty cycle of less than 50%, and the duty ratio depends on the number of clocks participating in the synthesis. Since the larger and smaller values do not have a minimum pulse width as a clock, data cannot be retimed stably, and the range of allowable input jitter becomes small, resulting in a loss of data.

In order to solve the above problems, the present invention monitors the number of data transition detection signals, and when the number is three or more, limits the number of clock pulses participating in the synthesis to be one or more and less than three, thereby synthesizing the clock pulses. A high-speed digital data retiming device with a large input allowable jitter range can be generated by satisfying the duty cycle of the circuit to ensure a minimum pulse width, thereby achieving stable retiming without loss of data. There is this.

1 is a block diagram of a conventional high speed digital data retiming apparatus;

2 is a block diagram of a high speed digital data retiming apparatus according to the present invention;

3 is a main timing diagram of the multiple delay clock pulse generator of FIG. 2;

4 is a main timing diagram of the data transition detector of FIG. 2;

5 is a configuration diagram of a data transition detection signal monitor of FIG. 2;

6 is a configuration diagram of the clock pulse synthesizer of FIG.

7 is a main timing diagram of FIG. 6;

<Explanation of symbols for main parts of drawing>

10: multi-phase clock pulse generator 20: clock pulse selection signal generator

30, 400: Clock pulse synthesizer 40, 500: D-Flip flop

50: buffer buffer 100: multiple delay clock pulse generator

200: data transition detector 300: data transition detection signal monitor

310: first full adder 311, 323: full adder

320: second full adder 321: third full adder

322: fourth full addition unit 330, 430: decision unit

331: first AND gate 332: first OR gate

410: positive phase clock pulse logic unit 411: second OR gate

412: second AND gate 420: anti-phase clock pulse logic unit

421: third OR gate 422: third AND gate

431 fourth OR gate 600 retiming buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for retiming high speed binary data bits with alignment jitter in a high speed digital data transmission system, and more particularly, to a high speed digital data retiming device having a large range of input allowable jitter.

A high-speed digital data retiming apparatus having a large input allowable jitter range includes multiple delay clock pulse generation means for delaying an external clock pulse using a delay element to generate a plurality of clock pulses having different phases, and the multiple delay clock pulses. Among the clock pulses output from the generating means, data transition detection means for selecting at least one data transition detection signal in which a transition is generated near the center of the data bit interval input from outside, and a data transition detection signal generated from the data transition detection means Data transition detection signal monitoring means for generating a clock pulse control signal so as to be one or more and less than three, and an optimum input for stably retiming external data by inputting multiple delayed clock pulses, data transition detection signals, and clock pulse control signals. Sum of clock pulses to synthesize clock pulses for A retiming means for retiming the serial data inputted from the outside into a synthesized clock pulse, and retiming the data retimed by the retiming means with an externally input clock to synchronize with an external clock for output It consists of a retiming buffer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a block diagram of a high-speed digital data retiming apparatus according to the present invention.

First, the multi-delay clock pulse generator 100 delays the clock pulse input from the outside by using a plurality of delay elements, and the first and last clock pulse phase difference is greater than or equal to the period T of the clock pulse input from the outside. Generate and output a plurality of multiple delayed clock pulses having a number of phases as many as the number of elements, and the data transition detector 200 inputs multiple delayed clock pulses output from the multiple delayed clock pulse generator 100 and data bits from the outside. And a data transition detection signal for selecting one or more clock pulses in which a transition occurs near the center of the data bit interval input from the plurality of multiple delayed clock pulses. The data transition detection signal monitor 300 receives the data transition detection signal generated by the data transition detector 200 and inverts the inverter, and monitors whether the number of '1' is three or more, In the case of 1 ', 1 or more and less than 3, a clock pulse control signal having a value of' 0 'is output. In this case, the data transition detection signal inverted by the data transition detection signal monitor 300 is an active state that selects a clock pulse that detects a transition of data when '1'. The clock pulse synthesizer 400 may include multiple delayed clock pulses of the multiple delayed clock pulse generator 100, a data transition detection signal of the data transition detector 200, and a clock pulse control signal of the data transition detection signal monitor 300. The clock pulses are synthesized so that the transition of the synthesized clock pulses occurs at the center of the externally input data bit interval. Here, when the clock pulse control signal is input only to the anti-phase clock logic unit, if the clock pulse control signal is '0', both the forward phase and the reverse phase of the clock pulse participate in clock pulse synthesis, but the clock pulse control signal is '1'. In this case, the reverse phase of the clock pulse is masked so that only the positive phase of the clock pulse participates in clock pulse synthesis, so that the number of selected clock pulses participating in the clock pulse synthesis is limited to two or less. In addition, when the clock pulse control signal is input only to the positive phase clock logic unit, if the clock pulse control signal is '0', both the normal phase and the reverse phase of the clock pulse participate in clock pulse synthesis, but the clock pulse control signal is '1'. In this case, the phase of the clock pulse is masked so that only the reverse phase of the clock pulse participates in clock pulse synthesis, so the number of selected clock pulses participating in the clock pulse synthesis is limited to two or less.

The reason why the number of clock pulses selected is limited to two or less is that the output value when the externally input data is retimed on the D-flip-flop 500 is (1, 0, 0) or (1, 1, 0). Since the data transition detection signal is activated when the value becomes (), the maximum number of the data transition detection signal is activated for the in-phase pulses is two. The D-flip-flop 500 retimes externally input data using the synthesized clock pulses generated by the clock pulse synthesizer 400, and the retiming buffer 600 receives data about the externally input clock pulses. When the phase of is slowly changed to one or more periods of a clock pulse input from the outside by a positive value or a negative value, it absorbs it so that no slip occurs and the synthesis of the clock pulse synthesizer 400 is performed. Finally, the retimed data is output in synchronization with the clock pulse inputted from the outside.

3 is a main timing diagram of the multiple delay clock pulse generator 100 of FIG. 2, (a) is an external clock pulse, (b) is a delayed clock pulse 1 (DCP1), (c) is a DCP2, and (d) DCP3, (e) represents DCP (n / 2), (f) represents DCPN1, (g) represents DCPN [(n-1) / 2], and (h) represents clock pulses of DCPN (n / 2), respectively. . And (a), (b), (c), (d), ... (e) represent positive phase multiple delayed clock pulses, and (f), ... (g), (h) are inverses Represents a phase multiple delay clock pulse, respectively. Here, n means the number of delay elements.

The external clock pulse of (a) is an externally input clock pulse, (b) is a signal obtained by delaying the external clock pulse by a phase difference of ΔP using a delay element and two inverters, and (c) and (d) , (e) is a signal obtained by delaying the positive phase clock pulse of the preceding stage by the phase difference of? P by using a delay element and two inverters. Since the phase difference from (b) to (e) is larger than the half period (T / 2) of the external input clock pulse (a), the multiple positive phase clock pulses of (b) to (e) are the external input clock pulse (a) Both of the transitions of data occurring between the rising transition and the falling transition of can be detected.

Similarly, (f), (g), and (h) are signals obtained by delaying the antiphase clock pulses of the preceding stage with a phase difference of ΔP using a delay element and two inverters. Since the phase difference from (f) to (h) is larger than the half period (T / 2) of the external input clock pulse (a), the multiple antiphase clock pulses of (f) to (h) are combined with the falling transition of the external input clock. All transitions of data occurring between rising transitions can be detected.

FIG. 4 is a main timing diagram of the data transition detector 200 of FIG. 2, wherein (a) is external input data, (b) is ENP1 (ENable Positive 1), (c) is ENP2, and (d) is ENP [( n / 2) -2], ... (e) is ENm, (f) is ENN1 (ENable Negative 1), (g) is ENN [(n / 2) -3], (h) is ENN [( n / 2) -2], respectively. Then, (b) to (e) represent selection signals generated by the positive phase clock pulses, and (f) to (h) represent the selection signals generated by the antiphase clock pulses.

(b) to (h) outputs an EN signal as '0' when data transition is detected in n multiple delayed clock pulses generated by the multiple delayed clock pulse generator 100 and '1' when no transition is detected. Show output. As described above, when the data transition occurs, the number of selection signals activated by '0' in the data transition detector is at least one, and the plurality of selection signals may be activated by '0'.

FIG. 5 is a configuration diagram of the data transition detection signal monitor 300 of FIG. 2, which monitors whether the number of selection signals generated by the data transition detector 200 is three or more using the full adder and the AND and OR gates. Transition detection signal monitor 300 circuit. The (n-4) data transition detection signals inputted from the data transition detector are input to the full adder so that the selection signal level at the time of inversion and activation becomes '1'. The first full adder 310 composed of (n-4) / 3 full adders 311 receives three data transition detection signals, respectively. The output of the full adder is SUM and CARRY. If the sum is '1', it means that there is at least one number of '1' at the input of the full adder, and if the carry is '1', the full adder Means that at least two of the number '1' is in the input of. Therefore, the sum and carry of the first full adder 310 indicate whether the number of '1' is one or more than two. The second full adder 320 is a third full adder 321 composed of a plurality of full adders 323 that add only a sum of values representing that the number of '1' is one or more of the outputs of the first full adder 310. ) And a fourth full adder 322 composed of a plurality of full adders 323 for only adding a carry value indicating that the number of '1' is two or more, and the third and fourth imputations as described above. The peaks 321 and 322 are serially configured, and only one full adder 323 is provided at the last stage. The outputs of the first full adder 310 are divided into a sum and a carry, and are added and output.

Accordingly, the output of the second full adder 320 is the sum of the output of the third full adder 321, which adds up to the sum indicating that the number of '1' is one or more, similarly to the first full adder 320. And carry each indicate whether the number of '1' is one or more than two, but the output from the fourth full adder 322 that totally adds the carry means that the number of '1' is two or more. This means that the number of '1' is two or more, and Carry means that the number of '1' is four or more. Accordingly, since the carry of the fourth full adder 322 means that there are four or more '1's, the number of' 1's is directly input to the first OR gate 332 of the determination unit 330. If there are four or more, the output value is '1'. When the above operation is repeated, only two full adders 323 are present at the final stage of the second full adder 320. Finally, in the determination unit 330, the first AND gate 331 is the third full adder, which means that one or more of '1' is output from the final stage full adder 323 of the second full adder 320. The sum of 321 and the sum of the fourth full addition unit 332, which means that the number of '1' is two or more, is output by logical multiplication. Here, the output of the first AND gate 331 indicates that the number of '1' is three or more. In addition, the first OR gate 332 outputs the OR of the outputs of the first AND gate 331 and the carry outputs of all stages of the fourth full adder 322 indicating that the number of '1' is four or more. do. Therefore, if the number of '1' at the input terminal is less than three, the output value is '0', and if the number of '1' at the input terminal is three or more, the output value is '1'.

As such, each stage means that the number of front end outputs and carry one '1' is one or more, and that the number of '1' is two or more, and that the number of '1' is four or more. Create a group with Groups that mean that the number of '1' is one or more and groups that mean the number of '1' are two or more are inputted by full adder.The grouped number is 3m-1, not multiple of 3. In this case, the half adder is used to input the output to the next stage or to a higher group. In the case of 3m -2, it is directly input to the next stage or higher group.

6 is a block diagram of the clock pulse synthesizer 400 of FIG. 2.

First, the positive phase clock pulse logic unit 410 outputs a plurality of second OR gates 411 from the positive phase multiple delay clock pulses output from the multiple delay clock pulse generator 100 and the data transition detector 200. The select signal generated by the positive phase clock pulse is ORed and output. The second AND gate 412 performs an AND operation on the output of the second OR gate 411. The anti-phase clock pulse logic unit 420 is configured by the third OR gate 421 to the anti-phase multiple delay clock pulse output from the multi delay clock pulse generator 100 and the antiphase clock pulse output from the data transition detector 200. The selection signal and the clock transition control signal CP_CON inputted from the data transition detection signal monitor 300 are ORed and output, and the third AND gate 412 is configured to logic the output of the third OR gate 421. Multiply and print. Here, when the clock pulse control signal CP_CON is '1', the outputs of the antiphase clock pulse logic unit 420 are all '1', so that the synthesized clock is made only by the positive phase clock pulse logic unit 410. . Therefore, the clock pulses used to synthesize the clock pulses are limited to one or more and less than three.

However, the clock pulse control signal CP_CON may be input only to the positive phase clock pulse logic unit 410 in addition to the method of inputting only to the antiphase clock pulse logic unit 420 as described above.

Finally, in the determination unit 430, the fourth OR gate 431 performs an OR on the outputs of the positive and reverse phase clock pulse logic units 410 and 420 to output the final synthesized clock.

7 is a main timing diagram of FIG. 6, wherein (a) is an external data bit, (b) is an external clock pulse, (c) is ENP1 (ENable Positive 1), (d) is DCP1 (Delayed Clock Pulse 1), (e) is ENP2, (f) is DCP2, ..., (g) is ENP [(n / 2) -2], (h) is DCP [(n / 2) -2], ... (i) ENN1 (ENable Negative 1), (j) DCPN1, ..., (k) ENN [(n / 2) -2], (l) DCPN (Delayed Clock Pulse Negative) [(n / 2) -2], (m) indicates CP_CON, and (n) indicates synthesized clock pulses, respectively.

The first transition of the external input data is {DCP1, DCP2, DCP3}, {DCP2, DCP3, DCP4}, {DCPN [(n / 2) -2], DCPN [(n / 2) -1], DCPN (n / 2)} Since it is detected in three combinations, ENP1, ENP2, and ENN [(n / 2) -2] are activated as '0' when data transition occurs from these three combinations. Since a total of three data transition detection signals are activated, the clock pulse control signal CP_CON is output as '1' from the data transition detection signal monitor. If the delay time until the clock pulse control signal reaches a stable value of '1' is less than T / 2-2P, no glitches occur in the synthesized clock. You can time it. In addition, since the number of clocks that participated in the synthesis is limited to one or more and less than three, the minimum pulse width as the clock is guaranteed to be T / 2-2P, so that no data slippage occurs.

As described above, the high-speed digital data retiming apparatus according to the present invention monitors whether three or more selection signals are used by the data transition detection signal monitor, thereby limiting the number of selection signals participating in clock synthesis to one or more than three, By minimizing jitter of the clock being synthesized, the number of multiple delayed clock pulses participating in the synthesis when the clock pulse synthesizer masks the select signal participating in the clock synthesis is reduced to one or more than three. The minimum pulse width of the synthesized clock can be guaranteed to be T / 2-2P, allowing stable retiming without losing data.

The present invention provides data for generating a data transition detection signal for selecting one or more clock pulses in which a transition occurs near a center of an externally input data bit interval among multiple delayed clock pulses output from the multiple delayed clock pulse generating means. A clock pulse control signal is generated so that the transition detection means and the data transition detection signal generated by the data transition detection means are one or more and less than three, satisfying the duty cycle of the clock synthesized by the clock pulse synthesizing means, and thus the minimum pulse width By providing a high-speed digital data retiming apparatus having a large range of input allowable jitter composed of data transition detection signal monitoring means for generating this guaranteed synthesized clock, it is possible to stably retime without losing data.

Claims (2)

An apparatus for retiming high speed binary data bits with alignment jitter in a high speed digital data transmission system, By delaying the externally input clock pulses to n-1 delay elements, n multiple delayed clock pulses with n phases whose first and last clock pulse phase differences are greater than or equal to the period (T) of the external clock pulses. Generating means for generating multiple delayed clock pulses; Generating and outputting a data transition detection signal for selecting one or more clock pulses in which a transition occurs near the center of an externally input data bit interval among n multiple delayed clock pulses output from the multiple delayed clock pulse generation means Transition detection means; A clock pulse control signal that monitors the data transition detection signal outputted from the data transition means and masks the clock pulse so that at least one or more clocks participating in clock pulse synthesis are masked when the data transition detection signal is three or more; Data transition detection signal monitoring means for generating and outputting a clock pulse control signal for generating and outputting the signal, and for suppressing the masking if there is more than one and less than three; Data bit intervals input externally from the multiple delay clock pulses output from the multiple delay clock pulse generation means, the data transition detection signal output from the data transition detection means and the clock pulse control signal output from the data transition detection signal monitoring means Clock pulse synthesizing means for synthesizing so that a transition of the synthesized clock pulses occurs at the center of the signal; A D-flip-flop for retiming the serial data input from the outside into a clock pulse synthesized by the clock pulse synthesizing means; When the phase of the data input from the outside changes slowly over one period of the clock pulse input from the outside, it is absorbed so that no slip occurs and the data re-timed by the retiming means is inputted from the outside. A high speed digital data retiming apparatus comprising: a retiming buffer means for retiming again to a clock and outputting in synchronization with an external clock. (Where n-1 is the number of delay elements) The method of claim 1, The data transition detection signal monitoring means is composed of a plurality of full adders and adds a data transition detection signal outputted from the data transition detection means by a plurality of full adders to a sum and carry signal of '0' or '1'. A first full adder for outputting a; The signal output from the first full adder is divided into a group indicating that there is at least one number in the first full adder input terminal and a group indicating that there is at least two numbers in the first full adder input terminal, and outputs the result. For each sum and carry, the group indicates that there is at least one number of 1s, the group indicating at least two numbers, and the signal indicating that there are four or more numbers of 1's. A second full adder configured to chain-repeatly repeat the group, and finally add the two adders to output signals indicating that four or more sums, carry and 1 are present; And a decision unit configured to logically multiply and sum the sum and the carry output from the second full adder to finally output a clock pulse control signal.

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