JPS62196352U - - Google Patents
Info
- Publication number
- JPS62196352U JPS62196352U JP8427886U JP8427886U JPS62196352U JP S62196352 U JPS62196352 U JP S62196352U JP 8427886 U JP8427886 U JP 8427886U JP 8427886 U JP8427886 U JP 8427886U JP S62196352 U JPS62196352 U JP S62196352U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- semiconductor chip
- encapsulating resin
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例による樹脂絶縁形半
導体装置の断面図、第２図はその平面図、第３図
、第４図はそれぞれ従来の樹脂絶縁形半導体装置
の断面図である。
１…低応力樹脂、５…耐湿性樹脂、２…リード
フレーム、３…リード線、４…半導体チツプ、６
…応力緩和用細溝。なお図中同一符号は同一又は
相当部分を示す。
FIG. 1 is a sectional view of a resin insulated semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view thereof, and FIGS. 3 and 4 are sectional views of conventional resin insulated semiconductor devices. DESCRIPTION OF SYMBOLS 1...Low stress resin, 5...Moisture-resistant resin, 2...Lead frame, 3...Lead wire, 4...Semiconductor chip, 6
...Thin grooves for stress relief. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
低応力性に優れた第１の封止樹脂で封止成形する
と同時に上記半導体チツプの上、下面側の該封止
樹脂表面部に細い巾の切込み部を形成し、全体を
耐湿性に優れた第２の封止樹脂で封止してなるこ
とを特徴とする樹脂絶縁形半導体装置。 A semiconductor chip mounted on a lead frame is encapsulated with a first encapsulating resin having excellent low stress properties, and at the same time, narrow cuts are made on the surface of the encapsulating resin on the upper and lower sides of the semiconductor chip. 1. A resin-insulated semiconductor device, characterized in that the semiconductor device is formed by molding the semiconductor device, and is entirely sealed with a second sealing resin having excellent moisture resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8427886U JPS62196352U (en) | 1986-06-02 | 1986-06-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8427886U JPS62196352U (en) | 1986-06-02 | 1986-06-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62196352U true JPS62196352U (en) | 1987-12-14 |
Family
ID=30938631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8427886U Pending JPS62196352U (en) | 1986-06-02 | 1986-06-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62196352U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019204819A (en) * | 2018-05-21 | 2019-11-28 | 株式会社デンソー | Electronic device |
-
1986
- 1986-06-02 JP JP8427886U patent/JPS62196352U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019204819A (en) * | 2018-05-21 | 2019-11-28 | 株式会社デンソー | Electronic device |
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