JPS62173539A - インサ−キット・エミュレ−タ - Google Patents
インサ−キット・エミュレ−タInfo
- Publication number
- JPS62173539A JPS62173539A JP61015086A JP1508686A JPS62173539A JP S62173539 A JPS62173539 A JP S62173539A JP 61015086 A JP61015086 A JP 61015086A JP 1508686 A JP1508686 A JP 1508686A JP S62173539 A JPS62173539 A JP S62173539A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- target
- circuit emulator
- debugging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61015086A JPS62173539A (ja) | 1986-01-27 | 1986-01-27 | インサ−キット・エミュレ−タ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61015086A JPS62173539A (ja) | 1986-01-27 | 1986-01-27 | インサ−キット・エミュレ−タ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62173539A true JPS62173539A (ja) | 1987-07-30 |
| JPH0373011B2 JPH0373011B2 (enExample) | 1991-11-20 |
Family
ID=11879030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61015086A Granted JPS62173539A (ja) | 1986-01-27 | 1986-01-27 | インサ−キット・エミュレ−タ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62173539A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408637A (en) * | 1990-12-27 | 1995-04-18 | Hitachi, Ltd. | Emulation techniques giving necessary information to a microcomputer to perform software debug and system debug even for incomplete target system |
-
1986
- 1986-01-27 JP JP61015086A patent/JPS62173539A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408637A (en) * | 1990-12-27 | 1995-04-18 | Hitachi, Ltd. | Emulation techniques giving necessary information to a microcomputer to perform software debug and system debug even for incomplete target system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0373011B2 (enExample) | 1991-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR970011212B1 (ko) | 데이타 프로세서 | |
| JPS62173539A (ja) | インサ−キット・エミュレ−タ | |
| JP2005353020A (ja) | コンピュータプログラムのシミュレーション方式 | |
| JPS6349851A (ja) | シミユレ−シヨンシステム | |
| JPH0550016B2 (enExample) | ||
| JP3424548B2 (ja) | 組み込み機器用ソフトウエア論理シミュレータ | |
| JPH0229455Y2 (enExample) | ||
| JPS6225334A (ja) | 命令処理方式 | |
| JPS584461A (ja) | プログラム・デバツク制御方式 | |
| JPH02181236A (ja) | デバッグ装置 | |
| JPS6325742A (ja) | トレ−ス機能付マイクロプロセツサ | |
| JPH0368037A (ja) | プログラム開発装置 | |
| JPH0465729A (ja) | シンボリック・デバッガ | |
| JPS63271542A (ja) | Romデバツガ | |
| Kosowska et al. | Implementing the Bus Protocol of a Microprocessor in a Software-Defined Computer | |
| JPS61131130A (ja) | レジスタ退避方法 | |
| JPH01159743A (ja) | ファームソフトシミュレータ | |
| JPH0233178B2 (enExample) | ||
| JPH04255038A (ja) | プロセッサのシミュレータによる入出力実行方法 | |
| JPH07113900B2 (ja) | エミュレーション・チップ | |
| JPH04369044A (ja) | コンピュータ用テスト装置 | |
| JPH06175874A (ja) | インサーキットエミュレータ装置 | |
| JPS59202546A (ja) | デバツグ装置 | |
| JPH02308342A (ja) | シミュレート・デバッガの構築方法 | |
| JPH01169546A (ja) | マルチタスクデバッカ |