JPS6213039A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS6213039A JPS6213039A JP60152734A JP15273485A JPS6213039A JP S6213039 A JPS6213039 A JP S6213039A JP 60152734 A JP60152734 A JP 60152734A JP 15273485 A JP15273485 A JP 15273485A JP S6213039 A JPS6213039 A JP S6213039A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- face
- electrode
- solder
- circuit metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は混成集積回路のフェイスダウン接続に関し、特
に支持基板上にフェイスダウン接続する混成集積回路の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to face-down connection of hybrid integrated circuits, and more particularly to improvements in hybrid integrated circuits that are face-down connected onto a support substrate.
（ロ）従来の技術
従来の半導体装置は第２図忙示す如く、チップキャリア
０１）の裏面に凹部を設け、その凹部の底部から側面お
よび壁体部ｔＬ′ｌＪ上面まで導電路０３）が形成され
、その壁体部ａり上面にはマザーボードａ４と接続する
接続電極（Ｌ！１９を設ける。(B) Prior Art As shown in Figure 2, a conventional semiconductor device has a recessed portion on the back surface of a chip carrier 01), and a conductive path 03) is formed from the bottom of the recessed portion to the side surface and the upper surface of the wall portion tL'lJ. A connection electrode (L!19) is provided on the upper surface of the wall portion a to be connected to the motherboard a4.
半導体チップαｅはチップキャリア（１１）の凹部の底
部に固着されダイスボンドまたはワイヤーボンドで前記
導電路ａ（至）に接続される。あらかじめチップキャリ
アαＤに配線形成されたマザーボード側との接続電極（
１５１と、スクリーン印刷等で半田等が塗布されたマザ
ーボードσ４とを重ね合せた後、マザーボードＩを加熱
しチップキャリア（１１１とマザーボード（１４とを接
着させるものである。The semiconductor chip αe is fixed to the bottom of the recess of the chip carrier (11) and connected to the conductive path a by die bonding or wire bonding. Connecting electrodes with the motherboard side that are wired on the chip carrier
151 and a motherboard σ4 coated with solder or the like by screen printing or the like are superimposed, and then the motherboard I is heated to bond the chip carrier (111) and the motherboard (14) together.
上述した同様の技術は特開昭６０−１７９３４号公報に
記載されている。A technique similar to that described above is described in Japanese Patent Application Laid-Open No. 17934/1983.
（ハ）発明ｂｚ解決しようとする問題点第２図に示す従
来技術では、マザーボード全体を加熱してフェイスダウ
ン・ボンデイングラ行すっていたので加熱装置が大きく
なる欠点ｂ−あった。(c) Problems to be Solved by the Invention In the prior art shown in FIG. 2, face-down bonding was performed by heating the entire motherboard, which resulted in the drawback that the heating device became large.
また、マザーボード全体を加熱しハンダが溶けるまでの
時間がかかるので作業性に問題があった。Additionally, it takes time to heat the entire motherboard and melt the solder, which poses problems in workability.
更にマザーボードを加熱し接続を行なっていた為、カラ
スエポキシ基板等の基板をマザーボードとして使用でき
ない欠点す−あった。Furthermore, since the motherboard was heated for connection, there was a drawback that a board such as a glass epoxy board could not be used as the motherboard.
に）問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであり、第１
図に示す如く支持基板（１）上に導電路（２）および接
続電極（３）を形成し、その接続電極（３）上にフェイ
スダウン回路金属基板（４）上に形成したバンプ電極（
７）とを一致させ配置した後、フェイスダウン回路金属
基板（４）をウロ熱支持基板（１）にフェイスダウン接
続するものである。B) Means for Solving the Problems The present invention has been made in view of the above points, and
As shown in the figure, a conductive path (2) and a connecting electrode (3) are formed on a supporting substrate (1), and a bump electrode (
7) and then connect the face-down circuit metal board (4) face-down to the heat support board (1).
（ホ）作用
本発明に依れば金属の熱伝導率を利用しフェイスダウン
回路金属基板の裏面のみ加熱して支持基板上にフェイス
ダウン接続することに依り、短時間で且つ容易に接続が
できるものである。(E) Function According to the present invention, by utilizing the thermal conductivity of metal to heat only the back side of the face-down circuit metal substrate and connect it face-down to the support substrate, connection can be easily made in a short time. It is something.
（へ）実施例
本発明に依る混成集積回路は第１図に示す如く、支持基
板（１）ハガラスエボキシ、セラミックオヨヒ金属等で
形成され、その表面にはスクリーン印刷等で所定のパタ
ーンの導電路（２）および接続電極（３）が形成され、
その接続電極（３）上には約２ｘｘ位の高さにハンダカ
ーディップされる。(F) Embodiment As shown in FIG. 1, the hybrid integrated circuit according to the present invention is made of a support substrate (1) made of glass epoxy, ceramic oyster metal, etc., and a predetermined pattern is printed on the surface of the substrate by screen printing or the like. A conductive path (2) and a connecting electrode (3) are formed,
A solder card is dipped onto the connection electrode (3) to a height of about 2xx.
フェイスダウン回路金属基板（４）は良熱伝導性の優れ
たアルミニウム基板を用い、そのアルミニウム基板の表
面には酸化アルミニウム膜を被覆し、さらに銅箔を貼着
する。その銅箔を所定のパターンにエツチングし導電路
（５）を形成する。その導電路（５）上にチップ抵抗、
チップコンデンサ、Ｔｒ等の電子部品（６）を搭載する
。さらに前記支持基板（１）に設けた接続電極（３）に
対応する位置にハンダを約２酩立の高さにディップしバ
ンプ電極（７）を形成する。The face-down circuit metal board (4) uses an aluminum board with excellent thermal conductivity, and the surface of the aluminum board is coated with an aluminum oxide film, and further a copper foil is attached. The copper foil is etched into a predetermined pattern to form a conductive path (5). A chip resistor is placed on the conductive path (5),
Electronic components (6) such as chip capacitors and transistors are mounted. Furthermore, bump electrodes (7) are formed by dipping solder to a height of approximately 2 cm at positions corresponding to the connection electrodes (3) provided on the support substrate (1).
支持基板（１）上に設けた複数の接続電極（３）と複数
のフェイスダウン回路金属基板（４）に設けたバンプ電
極（７）とを一致させた後、夫々のフェイスダウン回路
金属基板（４）の裏面をホット・アイロン（８）等で約
１８０℃程度に加熱し、バンプ電極（７）のハンダを溶
し支持基板（１）上に複数個のフェイスダウン回路金属
基板（４）を短時間でフェイスダウン接続することｂ′
−できる。After matching the plurality of connection electrodes (3) provided on the support substrate (1) with the bump electrodes (7) provided on the plurality of face-down circuit metal substrates (4), the respective face-down circuit metal substrates ( Heat the back side of 4) to about 180°C with a hot iron (8), etc. to melt the solder of the bump electrodes (7) and place multiple face-down circuit metal boards (4) on the support board (1). Connect face-down in a short time b'
-I can.
斯る本発明の混成集積回路に依れば、フェイスダウン回
路金属基板（４）の裏面のみ加熱し支持基板（１）上に
接続できるので短時間でフェイスダウン接続が行なえる
ものである。According to the hybrid integrated circuit of the present invention, since only the back side of the face-down circuit metal substrate (4) can be heated and connected to the support substrate (1), face-down connection can be performed in a short time.
（ト） 発明の効果
以上に詳述した如く本発明によれば、フェイスダウン回
路金属基板の裏面のみを加熱することにより、加熱装置
の小型化が行なえ極めて量産性の優れた混成集積回路が
できる。(G) Effects of the Invention As detailed above, according to the present invention, by heating only the back side of the face-down circuit metal substrate, the heating device can be miniaturized and a hybrid integrated circuit with extremely high mass productivity can be produced. .
また、本発明に於いてフェイスダウン回路金属基板裏面
にホット・アイロンを接して加熱し接続するのに対し、
従来はマザーボード全体を加熱し接続を行なっていたが
１本発明のフェイスダウン回路金属基板は小型で且つ熱
伝導率ｂ；優れている為短時間で接続が行なえるのに対
し、従来はマザーボード全体を加熱するのに時間ｂ′−
かかっていたので、接続時間の短縮す一行なえるので作
業性ｂｔ内向上る。In addition, in the present invention, a hot iron is brought into contact with the back surface of the face-down circuit metal board to heat the connection.
Conventionally, connections were made by heating the entire motherboard, but since the face-down circuit metal board of the present invention is small and has excellent thermal conductivity, connections can be made in a short time. It takes time b′- to heat
Since the connection time can be shortened, the work efficiency will be improved.
更に、本発明の混成集積回路は支持基板を加熱しない為
、ガラスエポキシ基板等の基板を支持基板として使用で
きるものである。Furthermore, since the hybrid integrated circuit of the present invention does not heat the support substrate, a substrate such as a glass epoxy substrate can be used as the support substrate.
更に、本発明の混成集積回路はフェイスダウン回路金属
基板に電子部品を搭載しフェイスダウン接続するので電
子部品のシールド効果が向上するものである。Further, since the hybrid integrated circuit of the present invention has electronic components mounted on a face-down circuit metal substrate and is connected face-down, the shielding effect of the electronic components is improved.
第１図は本発明による実施例を示す断面図、第２図は従
来例を示す断面図である。
（１）・・・支持基板、（２）・・・導電路、 （３）
・・・接続電極、（４）・・・フェイスダウン回路金属
基板、 （５）・・・導電路、（６）・・・電子部品、
（力・・・バンプ電極、 （８）１．・ホットアイロ
ン。FIG. 1 is a sectional view showing an embodiment according to the present invention, and FIG. 2 is a sectional view showing a conventional example. (1)...Supporting substrate, (2)...Conducting path, (3)
... connection electrode, (4) ... face-down circuit metal board, (5) ... conductive path, (6) ... electronic component,
(Force... bump electrode, (8) 1. Hot iron.
Claims (1)
支持基板上に形成した接続電極とフェイスダウン回路金
属基板に設けたバンプ電極とを接続して成る混成集積回
路に於いて、前記フェイスダウン回路金属基板を支持基
板上に接続する際、前記フェイスダウン回路金属基板を
裏面から加熱して支持基板にフェイスダウン接続するこ
とを特徴とした混成集積回路。1. In a hybrid integrated circuit in which conductive paths and connection electrodes are formed on a support substrate, and the connection electrodes formed on the support substrate are connected to bump electrodes provided on a face-down circuit metal substrate, 1. A hybrid integrated circuit characterized in that when connecting a down-circuit metal substrate to a support substrate, the face-down circuit metal substrate is heated from the back side and connected face-down to the support substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60152734A JPS6213039A (en) | 1985-07-11 | 1985-07-11 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60152734A JPS6213039A (en) | 1985-07-11 | 1985-07-11 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6213039A true JPS6213039A (en) | 1987-01-21 |
Family
ID=15546992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60152734A Pending JPS6213039A (en) | 1985-07-11 | 1985-07-11 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6213039A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489391A (en) * | 1987-09-29 | 1989-04-03 | Fujitsu Ltd | Soldering of printed board |
-
1985
- 1985-07-11 JP JP60152734A patent/JPS6213039A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489391A (en) * | 1987-09-29 | 1989-04-03 | Fujitsu Ltd | Soldering of printed board |
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