JPS6213040A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS6213040A
JPS6213040A JP60152735A JP15273585A JPS6213040A JP S6213040 A JPS6213040 A JP S6213040A JP 60152735 A JP60152735 A JP 60152735A JP 15273585 A JP15273585 A JP 15273585A JP S6213040 A JPS6213040 A JP S6213040A
Authority
JP
Japan
Prior art keywords
face
substrate
down circuit
circuit metal
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60152735A
Other languages
Japanese (ja)
Inventor
Yoshio Miura
三浦　敬男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP60152735A priority Critical patent/JPS6213040A/en
Publication of JPS6213040A publication Critical patent/JPS6213040A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To connect without positional displacement in a short time by forming an inserting portion on a face-down circuit metal substrate, inserting the inserting portion to the groove formed on a supporting substrate, and connecting by heating only the back surface of the face-down circuit metal substrate. CONSTITUTION:An inserting portion 3 if formed on a face-down circuit metal substrate 1, a groove 8 is formed on a supporting substrate 5 corresponding to the portion 3, and the portion 3 is inserted to prevent the substrates 1, 5 from displacing at the position occurred in case of connecting the substrates 1, 5. Further, since only the back surface of the substrate 1 is heated to be connected on the substrate 5, a face-down connection can be executed in a short time.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は混成集積回路のフェイスダウン接続に関し、特
に支持基板上にフェイスダウン接続する混成集積回路の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to face-down connection of hybrid integrated circuits, and more particularly to improvements in hybrid integrated circuits that are face-down connected onto a support substrate.

（ロ）従来の技術 従来の半導体装置は第４図に示す如く、チップキャリア
０Ｉ）の裏面に凹部を設け、その凹部の底部から側面お
よび壁体部（２２１上面まで導電路（ハ）ｂ−形成され
、その壁体部（２２１上面にはマザーボード２４）と接
続する接続電極（２つを設ける。(B) Prior art As shown in FIG. 4, a conventional semiconductor device has a recessed portion on the back surface of a chip carrier 0I), and conductive paths (c) b- Two connection electrodes are provided to connect to the wall portion (221 and the motherboard 24 on the upper surface).

半導体チップ（２（ｌｉｌはチップキャリア（２１）の
凹部の底部に固着され、ダイスポンドまたはワイヤーボ
ンドで前記導電路（ハ）に接続される。あらかじめチッ
プキャリア■υに配線形成されたマザーボード（２４）
との接続電極Ｃ２最と、スクリーン印刷等でノ・ンダが
塗布されたマザーボード（イ）とを重ね合せた後、マザ
ーボード（５）を加熱しチップキャリア０υとマザーボ
ード０４）とを接着させるものであるう上述した同様の
技術は特開昭６０−１７９３４号公報に記載されている
。The semiconductor chip (2) is fixed to the bottom of the recess of the chip carrier (21) and connected to the conductive path (c) with a die bond or wire bond. )
After overlapping the connecting electrode C2 with the motherboard (A) coated with No. by screen printing etc., the motherboard (5) is heated to bond the chip carrier 0υ and the motherboard 04). A technique similar to the above-mentioned one is described in Japanese Patent Laid-Open No. 17934/1983.

（ハ）発明ｂ′−解決しようとする問題点第２図に示す
従来技術では、マザーボード上にフェイスダウン接続を
行なう際にバンプ電極と接続電極とがずれることがあり
、ショートする欠点があった。(c) Invention b' - Problems to be Solved The conventional technology shown in Figure 2 has the drawback that the bump electrode and the connection electrode may be misaligned when making a face-down connection on the motherboard, resulting in a short circuit. .

また、マザーボード全体な加熱してフェイスダウン接続
を行なっていたので、加熱装置が大きくなる欠点があっ
た。In addition, because the entire motherboard was heated for face-down connection, the heating device had to be large.

更にマザーボード全体な加熱しノ・ンダが溶けるまでの
時間がかかるので作業性に問題があった。Furthermore, it took time for the entire motherboard to heat up and the adhesive to melt, which caused problems in workability.

更にマザーボードを加熱し接続を行なっていた為、ガラ
スエポキシ基板等の基板をマザーボードとして使用でき
ない欠点ｂ′−あった。Furthermore, since the motherboard was heated for connection, there was a drawback b'--that a substrate such as a glass epoxy substrate could not be used as the motherboard.

に）問題点を解決するための手段 本発明は上述した点に鑑みてなされたものであり、第１
図に示す如く、フェイスダウン回路金属基板（１）の相
対向する側辺に挿入部（３）を設けその挿入部（３）と
対応する支持基板＋５）　ｋ、、８部（８）を形成し、
その溝部（８）にフェイスダウン回路金属基板（１）に
設けた挿入部（３）す挿し、あらかじめ支持基板（５）
上に設けた接続電極（６）とフェイスダウン回路金属基
板（１）に設けたバンプ電極（７）とを位置合せした後
に、フェイスダウン回路金属基板（１）の裏面にホット
アイロン（１１１を接して加熱し支持基板（５）上にフ
ェイスダウン接続するものである。B) Means for Solving the Problems The present invention has been made in view of the above points, and
As shown in the figure, insert portions (3) are provided on opposite sides of the face-down circuit metal board (1), and a support substrate +5) k, 8 parts (8) corresponding to the insert portions (3) are formed. death,
Insert the insertion part (3) provided on the face-down circuit metal board (1) into the groove part (8), and insert the support board (5) in advance.
After aligning the connection electrode (6) provided above and the bump electrode (7) provided on the face-down circuit metal board (1), apply a hot iron (111) to the back side of the face-down circuit metal board (1). It is then heated and connected face down onto the support substrate (5).

（ホ）作用 本発明に依ればフェイスダウン回路金属基板に挿入部を
設け、あらかじめ支持基板上に設けられた溝部に挿入部
を挿入し、フェイスダウン回路金属基板の裏面のみ加熱
し接続することにより、短時間で且つ位置ずれを無くし
接続ができるものである。(e) Function According to the present invention, an insertion portion is provided on the face-down circuit metal board, the insertion portion is inserted into a groove provided in advance on the support substrate, and only the back side of the face-down circuit metal board is heated and connected. This allows connection to be made in a short time and without positional deviation.

（へ）実施例 本発明に依る混成集積回路は第１図に示す如く、フェイ
スダウン回路金属基板（１）は良熱伝導性の優れたアル
ミニウム基板を用いる。そのアルミニウム基板の表面に
は酸化アルミニウム膜を被覆し、さらにその上面に銅箔
を貼着する。その銅箔な所定のパターンにエツチングし
所望形状の導電路（２）を形成する。次にフェイスダウ
ン回路金属基板（１）の相対向する辺に非対称とをるよ
うに挿入部（３）を形成する。その挿入部（３）はフェ
イスダウン回路金属基板（１）の４隅をプレスで打抜き
突出部を形成し、本実施例では第２図に示す如く台形状
に形成するものである。台形状に形成した突出部を電子
部品（４）の搭載された方向に略直角に折曲げ挿入部（
３）を形成する。更に支持基板（５）上に設けた接続電
極（６）に対応する位置にハンダなディツプしバンプ電
極（７）を形成し、前記導電路（２）上にチップ抵抗、
チップコンデンサ、Ｔｒ等の電子部品（４）を搭載する
。(F) Embodiment As shown in FIG. 1, the hybrid integrated circuit according to the present invention uses an aluminum substrate having good thermal conductivity as the face-down circuit metal substrate (1). The surface of the aluminum substrate is coated with an aluminum oxide film, and a copper foil is further attached to the top surface. The copper foil is etched into a predetermined pattern to form a conductive path (2) of a desired shape. Next, insert portions (3) are formed asymmetrically on opposite sides of the face-down circuit metal board (1). The insertion portion (3) is formed by punching out the four corners of the face-down circuit metal board (1) to form protruding portions, and in this embodiment is formed into a trapezoidal shape as shown in FIG. Bend the trapezoidal protrusion approximately at right angles to the direction in which the electronic component (4) is mounted and insert the insertion portion (
3) Form. Further, solder dip bump electrodes (7) are formed at positions corresponding to the connection electrodes (6) provided on the support substrate (5), and chip resistors are placed on the conductive paths (2).
Electronic components (4) such as chip capacitors and transistors are mounted.

支持基板（５）はガラスエポキシ、セラミックおよび金
属等で形成される。更にフェイスダウン回路金属基板（
１）の挿入部（３）および電子部品（４）ｂ一対応する
位置には溝部（８）又は切欠孔（９）が設けられる。支
持基板表面にはスクリーン印刷等で所定のパターンの導
電路ａ〔および接続電極（６）？Ｊ′−形成され、その
接続電極（６）上にはハンダがディツプされる。The support substrate (5) is made of glass epoxy, ceramic, metal, or the like. In addition, face-down circuit metal board (
A groove portion (8) or a notch hole (9) is provided at a position corresponding to the insertion portion (3) and the electronic component (4) b of 1). A predetermined pattern of conductive path a [and connection electrode (6)?] is formed on the surface of the support substrate by screen printing or the like. J' is formed, and solder is dipped onto the connection electrode (6).

支持基板（５）上に設けた接続電極（６）とフェイスダ
ウン回路金属基板（１）に設けたバンプ電極（７）とを
一致させる様に支持基板（５）上に設けた溝部（８）に
フェイスダウン回路金属基板（１）の挿入部（３）す挿
入し位置合せした後、フェイスダウン回路金属基板（１
）の裏面をホットアイロン圓等で約１８０℃程度に加熱
しバンプ電極（７）のノ・ンダを溶し支持基板（５）上
にフェイスダウン回路金属基板（１）を７エイスダウン
接続するものである。A groove (8) provided on the support substrate (5) so as to match the connection electrode (6) provided on the support substrate (5) with the bump electrode (7) provided on the face-down circuit metal substrate (1). After inserting and aligning the insertion part (3) of the face-down circuit metal board (1), insert the face-down circuit metal board (1) into the
) is heated to approximately 180°C with a hot iron or the like to melt the nozzles of the bump electrodes (7) and connect the face-down circuit metal board (1) 7-eighth down to the support board (5). be.

斯る本発明の混成集積回路に依れば、フェイスダウン回
路金属基板（１）に挿入部（３）を設け、その挿入部（
３）と対応する支持基板（５）上に溝部（８）を設は挿
入部（３）を挿入することにより、フェイスダウン回路
金属基板（１）と支持基板（５）との接続の際に生じる
位置ずれを防止することができる。According to the hybrid integrated circuit of the present invention, the face-down circuit metal substrate (1) is provided with the insertion portion (3), and the insertion portion (3) is provided with the insertion portion (3).
By inserting the insertion part (3) into the groove part (8) on the supporting board (5) corresponding to 3), it is possible to connect the face-down circuit metal board (1) and the supporting board (5). Misalignment that occurs can be prevented.

更にフェイスダウン回路金属基板（１）の裏面のみ加熱
し支持基板（５）上に接続できるので短時間でフェイス
ダウン接続が行なえるものであるっ本発明の他の実施例
として第３図に示す如く、フェイスダウン回路金属基板
（１）の挿入部（３）の形状を凸形に形成し、その凸形
に形成した突起部（１２１を支持基板（５）上に形成し
た溝部（８）に挿入することにより支持基板（５）とフ
ェイスダウン回路金属基板（１）の間隙が保つことがで
きるので支持基板（５）上に切欠孔（９）を設けずフェ
イスダウン回路金属基板（１）が接続できるものである
。Furthermore, since only the back side of the face-down circuit metal board (1) can be heated and connected to the supporting board (5), face-down connection can be made in a short time.Another embodiment of the present invention is shown in FIG. As shown in FIG. By inserting the support board (5) and the face-down circuit metal board (1), the gap between the support board (5) and the face-down circuit metal board (1) can be maintained. It is something that can be connected.

（ト）発明の効果 以上に詳述した如く本発明に依れば、フエイスダウン回
路金属基板に挿入部を設け、その挿入部に対応する支持
基板上に溝部を設は前記挿入部を溝部に挿入しフェイス
ダウン接続を行なうことにより、従来発生していた位置
ずれから生じるジョートナ防ぐことができるので信頼性
が向上するものである。(G) Effects of the Invention As detailed above, according to the present invention, an insertion portion is provided on a face-down circuit metal board, and a groove portion is provided on a support substrate corresponding to the insertion portion, and the insertion portion is placed in the groove portion. By inserting and making a face-down connection, it is possible to prevent the jaw tensioner caused by positional displacement, which conventionally occurs, thereby improving reliability.

また、本発明の混成集積回路はフェイスダウン回路金属
基板の裏面のみを加熱することにより、加熱装置の小型
化が行なえ極めて量産性の優れた混成集積回路ｂ′−で
きる。Further, in the hybrid integrated circuit of the present invention, by heating only the back side of the face-down circuit metal substrate, the heating device can be miniaturized, and a hybrid integrated circuit b'-- can be produced which is extremely suitable for mass production.

更に１本発明の混成集積回路はフェイスダウン回路金属
基板裏面にホットアイロンを接して加熱し接続している
ので、従来のマザーボード全体を加熱し接続をするのに
対して、本発明のフェイスダウン回路金属基板は小をで
且つ熱伝導率が優れている為、短時間で接続が行なえる
が、従来はマザーボード全体を加熱していたので時間ｂ
−かかり、本発明を実施することにより接続時間の短縮
が行なえ作業性ｂ″−−向上ものである。Furthermore, since the hybrid integrated circuit of the present invention is connected by heating the back side of the face-down circuit metal board with a hot iron, unlike the conventional method in which the entire motherboard is heated and connected, the face-down circuit of the present invention Metal substrates are small and have excellent thermal conductivity, so connections can be made in a short time, but conventionally the entire motherboard was heated, which took a long time.
- Therefore, by implementing the present invention, connection time can be shortened and workability b''-- can be improved.

更に本発明の混成集積回路は支持基板を加熱しないので
、ガラスエポキシ基板等の基板を支持基板として使用で
きる。Further, since the hybrid integrated circuit of the present invention does not heat the supporting substrate, a substrate such as a glass epoxy substrate can be used as the supporting substrate.

更に本発明の混成集積回路はフェイスダウン回路金属基
板に電子部品な搭載しているので電子部品のシールド効
果が向上するものである。Furthermore, since the hybrid integrated circuit of the present invention has electronic components mounted on the face-down circuit metal substrate, the shielding effect of the electronic components is improved.

最後に本発明の混成集積回路のフェイスダウン回路金属
基板の挿入部を凸型にすることにより、支持基板に切欠
孔を設けずにフェイスダウン接続ｂＺできるものである
。Finally, by making the insertion portion of the face-down circuit metal substrate of the hybrid integrated circuit of the present invention into a convex shape, face-down connection bZ can be made without providing a notch hole in the support substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による実施例を示す断面図、第２図は本
実施を示す斜視分解図、第３図は他の実施例を示す斜視
分解図、第４図は従来例を示す断面図である。 （１）・・・フェイスダウン回路金属基板、　（２）・
・・導電路、（３）・・・挿入部、　（４）・・・電子
部品、　（５）・・・支持基板、　（６）・・・接続電
極、　（７）・・・バンプ電極、（８）・・・溝部、　
（９）・・・切欠孔、　（ＩＩ・・・導電路、　■・・
・ホットアイロン、　（１２１・・・突起部。Fig. 1 is a sectional view showing an embodiment according to the present invention, Fig. 2 is a perspective exploded view showing the present embodiment, Fig. 3 is a perspective exploded view showing another embodiment, and Fig. 4 is a sectional view showing a conventional example. It is. (1)...Face-down circuit metal board, (2)...
... Conductive path, (3) ... Insertion part, (4) ... Electronic component, (5) ... Support substrate, (6) ... Connection electrode, (7) ... Bump electrode, (8)...Groove,
(9)... Notch hole, (II... Conductive path, ■...
・Hot iron, (121... protrusion.

Claims (1)

【特許請求の範囲】[Claims] １．　支持基板上に導電路および接続電極を形成し、前
記支持基板上に形成した接続電極とフェイスダウン回路
金属基板に設けたバンプ電極とを接続して成る混成集積
回路に於いて、前記フェイスダウン回路金属基板の少な
くとも一側辺に挿入部を設け、該挿入部と対応する支持
基板上に溝部を設け、該溝に前記挿入部を挿入し前記接
続電極とバンプ電極とを位置合せした後、前記フェイス
ダウン回路金属基板を裏面から加熱して支持基板上にフ
ェイスダウン接続することを特徴とした混成集積回路。1. In a hybrid integrated circuit, a conductive path and a connection electrode are formed on a support substrate, and the connection electrode formed on the support substrate is connected to a bump electrode provided on a face-down circuit metal substrate. An insertion portion is provided on at least one side of the metal substrate, a groove is provided on the support substrate corresponding to the insertion portion, the insertion portion is inserted into the groove and the connection electrode and the bump electrode are aligned, and then the Face-down circuit A hybrid integrated circuit characterized by heating a metal substrate from the back side and connecting it face-down to a support substrate.
JP60152735A 1985-07-11 1985-07-11 Hybrid integrated circuit Pending JPS6213040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60152735A JPS6213040A (en) 1985-07-11 1985-07-11 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60152735A JPS6213040A (en) 1985-07-11 1985-07-11 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6213040A true JPS6213040A (en) 1987-01-21

Family

ID=15547012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60152735A Pending JPS6213040A (en) 1985-07-11 1985-07-11 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6213040A (en)

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