JPS62126718A - シリアル・パラレル変換回路 - Google Patents
シリアル・パラレル変換回路Info
- Publication number
- JPS62126718A JPS62126718A JP60267703A JP26770385A JPS62126718A JP S62126718 A JPS62126718 A JP S62126718A JP 60267703 A JP60267703 A JP 60267703A JP 26770385 A JP26770385 A JP 26770385A JP S62126718 A JPS62126718 A JP S62126718A
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- clock
- shift register
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 10
- 238000010586 diagram Methods 0.000 description 4
- 241000287828 Gallus gallus Species 0.000 description 1
Landscapes
- Shift Register Type Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60267703A JPS62126718A (ja) | 1985-11-27 | 1985-11-27 | シリアル・パラレル変換回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60267703A JPS62126718A (ja) | 1985-11-27 | 1985-11-27 | シリアル・パラレル変換回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62126718A true JPS62126718A (ja) | 1987-06-09 |
| JPH0583008B2 JPH0583008B2 (enExample) | 1993-11-24 |
Family
ID=17448369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60267703A Granted JPS62126718A (ja) | 1985-11-27 | 1985-11-27 | シリアル・パラレル変換回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62126718A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05233213A (ja) * | 1992-02-24 | 1993-09-10 | Fujitsu Ltd | 直列並列変換回路 |
| JPH06169260A (ja) * | 1992-11-30 | 1994-06-14 | Nec Corp | 直並列変換回路 |
-
1985
- 1985-11-27 JP JP60267703A patent/JPS62126718A/ja active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05233213A (ja) * | 1992-02-24 | 1993-09-10 | Fujitsu Ltd | 直列並列変換回路 |
| JPH06169260A (ja) * | 1992-11-30 | 1994-06-14 | Nec Corp | 直並列変換回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0583008B2 (enExample) | 1993-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6750692B2 (en) | Circuit and method for generating internal clock signal | |
| KR100362199B1 (ko) | 링 딜레이와 카운터를 이용한 레지스터 제어 지연고정루프 | |
| US5786715A (en) | Programmable digital frequency multiplier | |
| JP2001320280A (ja) | 並列−直列変換回路 | |
| KR100265610B1 (ko) | 데이터 전송속도를 증가시킨 더블 데이터 레이트 싱크로너스 디램 | |
| JP2004048729A (ja) | ディレイロックループにおけるクロック分周器及びクロック分周方法 | |
| US7075351B2 (en) | Method and apparatus for generating a multiphase clock | |
| US5774079A (en) | Circuit arrangement for converting a serial data signal into a parallel data signal | |
| JPS62126718A (ja) | シリアル・パラレル変換回路 | |
| EP0527636B1 (en) | Counter circuit using Johnson-type counter and applied circuit including the same | |
| JP2555978B2 (ja) | 分周回路 | |
| US6008676A (en) | Digital clock frequency multiplier | |
| US4741005A (en) | Counter circuit having flip-flops for synchronizing carry signals between stages | |
| JPH0865173A (ja) | パラレルシリアル変換回路 | |
| JP2702111B2 (ja) | 多段分周バイナリ・カウンタ | |
| JPH03240336A (ja) | ビット位相同期回路 | |
| US7519090B2 (en) | Very high speed arbitrary number of multiple signal multiplexer | |
| JP3072494B2 (ja) | 並列形フレーム同期回路のチャネル選択状態のモニタ回路 | |
| JPH05102861A (ja) | マルチプレクサ | |
| CN109547005A (zh) | 转换电路 | |
| JP2621205B2 (ja) | 分周回路 | |
| JPH04142116A (ja) | 可変分周器 | |
| CN120380699A (zh) | Ddr phy并行时钟路径架构 | |
| JP3853308B2 (ja) | 遅延回路および電子回路 | |
| JPH0611133B2 (ja) | フレ−ム位相制御回路 |