JPS62122241A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62122241A
JPS62122241A JP60261145A JP26114585A JPS62122241A JP S62122241 A JPS62122241 A JP S62122241A JP 60261145 A JP60261145 A JP 60261145A JP 26114585 A JP26114585 A JP 26114585A JP S62122241 A JPS62122241 A JP S62122241A
Authority
JP
Japan
Prior art keywords
ejector pin
index mark
double
semiconductor device
mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60261145A
Other languages
Japanese (ja)
Inventor
Katsuhiro Tabata
田畑 克弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60261145A priority Critical patent/JPS62122241A/en
Publication of JPS62122241A publication Critical patent/JPS62122241A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To simplify the structure of a sealing device, by forming an index mark, which is provided in the surface of a resin sealing type semiconductor device in a double-circle shape, thereby eliminating the directivity of the mark and omitting a preventing mechanism of the turning of an ejector pin. CONSTITUTION:A semiconductor chip is surrounded with a resin sealing material in a structure body 1A. When a press plate 41 of a sealing device 40 is compressed in the direction of an arrow 4, the part of a semiconductor chip is sealed with the compression of a top force 5, which is fixed to a template 7, and a bottom force 6. At this time a double-circle index mark is formed by the compressed trace of an ejector pin 2 of a tip part 2B. The pin has a circular protruded or recessed cross section. Since such a double-circle shaped index mark 30 is provided, even if a block shape part 2' of the upper part of the ejector pin 2 is turned in a space 10 within an ejector pin holder 8 with the cylinder shaped block, the same double-circule shaped mark is always obtained because of the double-circle shaped index mark. Therefore, external appearance does not look poor.

Description

【発明の詳細な説明】 [技術分野〕 本発明は、半導体装置に係り、特に、樹脂封止型半導体
装置のインデックスマークに適用して有効な技術に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to an index mark of a resin-sealed semiconductor device.

〔背景技術〕[Background technology]

実装基板に樹脂封止型半導体装置を実装する場合、樹脂
封止型半導体装置の多数のリードピンの各機能に対応し
た実装基板の所定の接続端子に接続する必要がある。現
状では、ある特定の実装基板の接続端子(例えば、電圧
端子)とこの特定の接続端子に対応する樹脂封止型半導
体装置のり一ドビンとの位置関係を示すインデックスマ
ークを樹脂封止型半導体装置の封止用樹脂の表面に設け
ている。前記インデックスマークを設ける手段として、
樹脂で半導体チップを封止する際のエジェクタピンの押
圧跡を利用している。
When mounting a resin-sealed semiconductor device on a mounting board, it is necessary to connect a large number of lead pins of the resin-sealed semiconductor device to predetermined connection terminals of the mounting board corresponding to each function. Currently, index marks indicating the positional relationship between a connection terminal (for example, a voltage terminal) on a specific mounting board and a resin-sealed semiconductor device glue dowel corresponding to this specific connection terminal are attached to a resin-sealed semiconductor device. It is provided on the surface of the sealing resin. As means for providing the index mark,
It uses the press marks left by the ejector pin when sealing the semiconductor chip with resin.

そのインデックスマークを樹脂封止型半導体装置に押圧
する装置の要部を第9図(断面図)に示す。第10図は
、第9図に示すa部の拡大図であり、第11図は、この
インデックスマークの問題点を示す平面図である。
FIG. 9 (cross-sectional view) shows the main part of the apparatus for pressing the index mark onto the resin-sealed semiconductor device. FIG. 10 is an enlarged view of section a shown in FIG. 9, and FIG. 11 is a plan view showing the problem with this index mark.

前記インデックスマークは、第9図に示すように、エジ
ェクタピン2の抑圧によって上型5と樹脂封止型半導体
装置1とを分離する際に施こされる。ここで、第9図に
おいて、エジェクタピン2の上部は、ブロック状部2′
になっており、このブロック状部2′は、エジエクタバ
ッキングプレ−ト9にエジェクタピンホルダー8を介し
て保持されている。そして、エジェクタピンホルダー8
と前記ブロック状部2′との間には、空間10を設けて
遊嵌合となっている。これは、エジェクタピン2にかな
りの負荷がかかるので、その負荷を緩和するためである
。また、エジェクタピン2の先端部2Aは、第10図及
び第11図に示すように、断面が円形状で先端面に直線
状の溝2A’ を設けたものである。第9図において、
6は下型。
The index mark is formed when the upper mold 5 and the resin-sealed semiconductor device 1 are separated by pressing the ejector pin 2, as shown in FIG. Here, in FIG. 9, the upper part of the ejector pin 2 is a block-shaped part 2'.
This block-shaped portion 2' is held on an ejector backing plate 9 via an ejector pin holder 8. And ejector pin holder 8
A space 10 is provided between the block-shaped portion 2' and the block-shaped portion 2', so that they are loosely fitted. This is to alleviate the considerable load that is placed on the ejector pin 2. Further, the distal end portion 2A of the ejector pin 2 has a circular cross section and a linear groove 2A' is provided on the distal end surface, as shown in FIGS. 10 and 11. In Figure 9,
6 is the lower mold.

7は型板であり、第10図において、4は凸状部3から
なるインデックスマークである。
7 is a template, and in FIG. 10, 4 is an index mark consisting of a convex portion 3.

しかしながら、前記封止装置1では、エジェクタピン2
の保持部に、前記空間10を設けなければならないため
、エジェクタピン2が半導体装置の表面を押圧し、イン
デックスマーク4の凸状部3が回転し、第11図の鎖線
で示すように回転するので、樹脂封止型半導体装置1の
外観は、見ばえが悪いという問題があった。
However, in the sealing device 1, the ejector pin 2
Since the space 10 must be provided in the holding portion, the ejector pin 2 presses the surface of the semiconductor device, and the convex portion 3 of the index mark 4 rotates as shown by the chain line in FIG. Therefore, there was a problem in that the resin-sealed semiconductor device 1 had a poor appearance.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、樹脂封止型半導体装置にお−て、均一
なインデックスマークを設けて外観上の見ばえを良くす
ることができる技術を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can improve the external appearance of a resin-sealed semiconductor device by providing uniform index marks.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図によって明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。
Outline of typical inventions disclosed in this application is as follows.

すなわち、樹脂封止型半導体装置において、封止樹脂上
にインデックスマークを設け、該インデックスマークが
二重丸であり、前記二重丸のインデックスマークは、そ
の先端部の断面が円形状の凸部状または凹部状に構成さ
れたエジェクタピンの押圧跡で形成されたものである。
That is, in a resin-sealed semiconductor device, an index mark is provided on the sealing resin, and the index mark is a double circle, and the double-circle index mark has a convex portion having a circular cross section at its tip. It is formed by the press marks of the ejector pin, which are shaped like a shape or a concave part.

以下1本発明の構成を実施例とともに説明する。The configuration of the present invention will be explained below along with examples.

なお、全図において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。
In all the figures, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

〔実施例〕〔Example〕

第1図は本発明の一実施例の樹脂封止型半導体装置(以
下、半導体装置という)の構成を示す平面図、第2図は
第1図の■−■切断線における断面図である。
FIG. 1 is a plan view showing the structure of a resin-sealed semiconductor device (hereinafter referred to as a semiconductor device) according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line 1--2 in FIG.

本実施例の半導体装[1は、第1図及び第2図に示すよ
うに、タブ基板25の上に半導体チップ26を取り付け
、その半導体チップ26とリードピン23をワイヤー2
6Aでボンディングして電気的に接続し、それらを樹脂
20で封止してなるものである。この半導体装置1の表
面の上面又は下面の特定のり−ドピン23に対応する位
置に二重丸状のインデックスマーク30を設けたもので
ある。この二重丸状のインデックスマーク30は、リー
ドピン23のうち特定のリードピン23A。
As shown in FIGS. 1 and 2, the semiconductor device [1 of this embodiment] includes a semiconductor chip 26 mounted on a tab substrate 25, and the semiconductor chip 26 and lead pins 23 connected by wires.
They are electrically connected by bonding with 6A and sealed with resin 20. A double round index mark 30 is provided on the upper or lower surface of the semiconductor device 1 at a position corresponding to a specific glued pin 23. This double round index mark 30 corresponds to a specific lead pin 23A among the lead pins 23.

例えば、第1リードピンの位置を表示するためのもので
あり、後述する封止装置のエジェクタピンの押圧跡とし
て形成されるものである。
For example, it is for displaying the position of the first lead pin, and is formed as a pressing trace of an ejector pin of a sealing device, which will be described later.

なお、第1図において、24は、もう片方のエジェクタ
ピンの押圧跡である。
In addition, in FIG. 1, 24 is a pressing trace of the other ejector pin.

次に前記二重丸状のインデックスマーク30の形成方法
について第3図乃至第7図を用いて説明する。
Next, a method for forming the double round index mark 30 will be explained with reference to FIGS. 3 to 7.

本実施例の半導体装置1の製造工程において。In the manufacturing process of the semiconductor device 1 of this embodiment.

半導体チップを樹脂封止材で包囲した構造体IAは、第
3図(封止及びインデックスマークを施す装置の断面図
)に示すように、封止装置40の封止装置台42の摺動
面42A上を摺動する下型6に保持され、下型6に設け
ている位置決め穴38に、リターンピン37の先端部3
7Aが係合して。
The structure IA, in which a semiconductor chip is surrounded by a resin sealing material, is attached to the sliding surface of the sealing device stand 42 of the sealing device 40, as shown in FIG. The tip 3 of the return pin 37 is held by the lower mold 6 sliding on the 42A, and the tip 3 of the return pin 37 is inserted into the positioning hole 38 provided in the lower mold 6.
7A is engaged.

所定の位置に停止する。この所定位置に装着された構造
体LAは、封止装置40のプレス板41を、矢印C方向
にプレス(図示していない)により押圧したとき、型板
7に固定している上型5と下型6との圧着により半導体
チップ部分が封止される。
Stops in place. When the press plate 41 of the sealing device 40 is pressed by a press (not shown) in the direction of arrow C, the structure LA mounted at this predetermined position is pressed against the upper mold 5 fixed to the mold plate 7. The semiconductor chip portion is sealed by pressure bonding with the lower mold 6.

そして、前記プレス板41が押圧されるとき、スプリン
グ50の弾力でエジェクタピンバッキングプレート9と
エジェクタピンホルダー8がエジェクタピン2の上部の
ブロック状部2′を押圧し、エジェクタピン2の先端部
2Bを前記構造体IAの上面に押圧する。これにより、
封止された構造体IA(半導体装置1)の上面に、二重
丸状のインデックスマーク30が施される。そして、前
記封止と二重丸状のインデックスマーク30を施した後
、プレスでプレス板41をD方向に引き上げ型板7に固
定されている上型5と一緒に、その上型5に入っている
構造体LA(半導体装置l)をも引き上げる。
When the press plate 41 is pressed, the ejector pin backing plate 9 and the ejector pin holder 8 press the upper block-shaped part 2' of the ejector pin 2 due to the elasticity of the spring 50, and the tip part 2B of the ejector pin 2 is pressed. is pressed onto the upper surface of the structure IA. This results in
A double circular index mark 30 is provided on the upper surface of the sealed structure IA (semiconductor device 1). After the sealing and the double round index mark 30 are applied, the press plate 41 is pulled up in the D direction with a press and placed into the upper mold 5 together with the upper mold 5 fixed to the mold plate 7. Also pull up the structure LA (semiconductor device 1) that is currently in use.

その時、構造体IAは、前記スプリング50の弾力によ
り前記エジェクタピン2の先端部2Bで押圧されている
ので、上型5からはずれて分離する。
At this time, the structure IA is pressed by the tip 2B of the ejector pin 2 due to the elasticity of the spring 50, and is therefore separated from the upper mold 5.

なお、第3図において、32は当て板、33は断熱材、
34は取り付は板、35は連結スペーサーブロックであ
る。
In addition, in FIG. 3, 32 is a patch plate, 33 is a heat insulating material,
34 is a mounting plate, and 35 is a connecting spacer block.

前記エジェクタピン2の先端部2Bは、第4図に示すよ
うに、断面が円形状の凹部状になっており、これを前記
のように押圧することにより二重丸状のインデックスマ
ーク30が半導体装置1の上面または下面に施される。
As shown in FIG. 4, the tip end 2B of the ejector pin 2 has a concave shape with a circular cross section, and by pressing this as described above, a double round index mark 30 is formed on the semiconductor. It is applied to the top or bottom surface of the device 1.

この二重丸状のインデックスマーク30を施すためにの
エジェクタピン2の先端部は、種々のものが考えられる
。例えば、第5図に示すように。
Various types of tip portions of the ejector pin 2 can be considered for forming the double round index mark 30. For example, as shown in FIG.

エジェクタピン2の先端部2Cが、おわん状の凹部で形
成されているもの、第6図に示すように。
The tip end 2C of the ejector pin 2 is formed with a bowl-shaped recess, as shown in FIG.

エジェクタピン2の先端部2Dが凸状で形成されている
もの、第7図に示すように、エジェクタピン2り先端部
2Eがおわん状の凸部で形成されているものなどが考え
られる。
The ejector pin 2 may have a tip 2D formed in a convex shape, or as shown in FIG. 7, the tip 2E of the ejector pin 2 may be formed as a bowl-shaped convex portion.

以上の説明かられかるように1本実施例によれば、半導
体装置上に前記二重丸状のインデックスマーク30を設
けることにより、第3図に示すように、エジェクタピン
2の上部のブロック状部2′がたとえ1円柱状ブロック
でエジェクタピンホルダー8内の空間lOにより回転し
たとしても、二重丸状のインデックスマーク30である
ため、常に同形の二重丸状のマークとなるので、外観上
見ばえが良くなる。
As can be seen from the above description, according to the present embodiment, by providing the double round index mark 30 on the semiconductor device, the block shape on the upper part of the ejector pin 2 is created as shown in FIG. Even if part 2' is a cylindrical block and rotates due to the space 10 in the ejector pin holder 8, since it is a double round index mark 30, it will always be the same double round mark, so the appearance will be different. The appearance improves.

なお、前記インデックスマークを二重丸状のものと異な
るマーク、例えば、背景技術の項で述べた円形状のマー
クの中に直線の入ったマークであっても、エジェクタピ
ン2を回転しないようにしてやればよいと考えることが
できるが、第8図に示すように、エジェクタピン2の頭
部のブロック状部2′の一部を欠き、これと嵌合する長
穴60を設けてエジェクタピンが回転しないようにする
Note that even if the index mark is a mark different from a double round mark, for example, a mark with a straight line inside the circular mark mentioned in the background art section, the ejector pin 2 should not be rotated. However, as shown in Fig. 8, a part of the block-shaped part 2' of the head of the ejector pin 2 is cut out, and an elongated hole 60 is provided to fit there. Avoid rotating.

半導体装置上のインデックスマークを1本実施例の二重
丸状のインデックスマーク30にすることにより、前記
エジェクタピン2の回転防止機構を設けなくてもよいの
で、封止袋[40の構造を簡単にすることができる。
By using the double round index mark 30 of this embodiment as the index mark on the semiconductor device, there is no need to provide a rotation prevention mechanism for the ejector pin 2, and the structure of the sealing bag [40] can be simplified. It can be done.

〔効果〕〔effect〕

以上説明したように、本願で開示した新規な技術によれ
ば、次に述べるような効果を得ることができる。
As explained above, according to the new technology disclosed in this application, the following effects can be obtained.

(1)半導体装置の表面の上面または下面に二重丸状の
インデックスマークを設けたことにより。
(1) By providing a double circular index mark on the top or bottom surface of the semiconductor device.

この半導体装置の外観上の見ばえを良くすることができ
る。
The external appearance of this semiconductor device can be improved.

(2)半導体装置の表面の上面または下面に二重丸状の
インデックスマークを設けたことにより、エジェクタビ
ン回転防止機構を設けなくてもよいので、封止装置を構
造上簡単にすることができる。
(2) By providing a double circular index mark on the top or bottom surface of the semiconductor device, there is no need to provide an ejector bin rotation prevention mechanism, so the structure of the sealing device can be simplified. .

以上1本発明を実施例にもとずき具体的に説明したが1
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変形可能であること
はいうまでもない。
The present invention has been specifically explained above based on examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例の樹脂封止型半導体装置の
構成を示す平面図。 第2図は、第1図の■−■接断線断線ける断面図。 第3図は、本実施例の構造体を封止して樹脂封止型半導
体装置を形成し、同時にインデックスマークを施す封止
装置の断面図。 第4図乃至第7図は1本実施例の二重丸状インデックス
マークを施すエジェクタピンの先端部の実施例を示す部
分拡大図、 第8図は1本実施例の一つの効果を説明するための図。 第9図乃至第11図は、従来の問題点を説明するだめの
図である。 図中、1・・・樹脂封止型半導体装置、IA・・・構造
体、2・・・ブロック状部、2A、2B、2C,2D。 2E・・・先端部、3・・・凸状部、4・・・凸状部3
からなるインデックスマーク、5・・・上型、6・・・
下型、30・・・二重丸状のインデックスマーク、40
・・・封止装置である。 第  1  図 第  2  図 2さ 第  3  図
FIG. 1 is a plan view showing the configuration of a resin-sealed semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view taken along line 1--2 in FIG. 1. FIG. 3 is a sectional view of a sealing device that seals the structure of this embodiment to form a resin-sealed semiconductor device and at the same time applies index marks. 4 to 7 are partially enlarged views showing an embodiment of the tip of an ejector pin to which a double round index mark is applied according to the first embodiment, and FIG. 8 illustrates one effect of the first embodiment. Illustration for. FIGS. 9 to 11 are diagrams for explaining conventional problems. In the drawings, 1: resin-sealed semiconductor device, IA: structure, 2: block-shaped portions, 2A, 2B, 2C, 2D. 2E... Tip portion, 3... Convex portion, 4... Convex portion 3
Index mark consisting of 5... upper die, 6...
Lower mold, 30...Double round index mark, 40
...It is a sealing device. Figure 1 Figure 2 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 1、封止樹脂上にインデックスマークを設けた樹脂封止
型半導体装置であって、前記インデックスマークが二重
丸であることを特徴とする半導体装置。 2、前記二重丸のインデックスマークは、その先端部の
断面が円形状の凸部状または凹部状に構成されたエジェ
クタピンの押圧跡で形成されて成ることを特徴とする特
許請求の範囲第1項記載の半導体装置。
[Scope of Claims] 1. A resin-sealed semiconductor device having an index mark provided on a sealing resin, wherein the index mark is a double circle. 2. The double-circular index mark is formed by a pressing trace of an ejector pin whose tip section has a circular convex or concave shape. The semiconductor device according to item 1.
JP60261145A 1985-11-22 1985-11-22 Semiconductor device Pending JPS62122241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60261145A JPS62122241A (en) 1985-11-22 1985-11-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60261145A JPS62122241A (en) 1985-11-22 1985-11-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62122241A true JPS62122241A (en) 1987-06-03

Family

ID=17357722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60261145A Pending JPS62122241A (en) 1985-11-22 1985-11-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62122241A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008252133A (en) * 2008-07-10 2008-10-16 Sanyo Electric Co Ltd Semiconductor device
JP2009188423A (en) * 2009-04-16 2009-08-20 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008252133A (en) * 2008-07-10 2008-10-16 Sanyo Electric Co Ltd Semiconductor device
JP2009188423A (en) * 2009-04-16 2009-08-20 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof

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