JPS62117370A - Manufacture of double-gate electrostatic induction thyristor - Google Patents

Abstract

PURPOSE:To obtain an SIT whose forward direction voltage drop is small and switching speed is extremely high, by making a first gate and a second gate in a plane structure and a buried structure respectively, and drawing out both of the gate electrodes from the single surface of an Si substrate. CONSTITUTION:On the (111) face of a P<+> Si substrate 10, a P-epitaxial layer 11 of specified thickness is laminated, which is subjected to a selective ion implantation and annealing to make a second gate layer 12 of N<+> type. This is buried under an N<-> eptaxial layer 14 on which an SiO2 mask 16 is formed to diffuse B, and a first gate layer 15 of P<+> type is formed with a specified spacing and depth. Apertures are formed selectively, and a shallow N<+> layer 17 is formed from a P-added poly Si layer 18. Apertures are made on the P<+> layer 15, and the N<+> layer 12 is exposed by an etching in which an Si3N4 mask 19 is applied. P ion is implanted in the N<+> layer where an Al mask 20 is applied. The masks 19 and 20 are eliminated, and Al deposition electrodes 21-24 are formed. The injection of electrons and position holes is increased by the forward bias voltage of the two gate electrodes, so that the ON voltage is decreased and the rapid OFF state without tailing can be obtained by a reverse bias voltage. Thus the electric potential of both gates can be made high simultane ously, so that carrier injection is rapidly blocked and a high current gain is obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a double gate electrostatic induction thyristor (Double QateS) in which a first gate has a surface gate structure and a second gate has a buried gate structure. tatic I
nduc mouth on 7 hyristor, hereinafter DG
SIThy). By using the manufacturing process of the present invention, DGSIThy,
can be realized. The DGSI Thy realized by the manufacturing process of the present invention can perform orthogonal conversion of medium to small power at very high speed and with high efficiency.

[Prior art] Conventionally, gate turn-off thyristors (Gate T
urn off thyristor (hereinafter abbreviated as GTO) and static induction thyristor (static induction thyristor)
duction T hyristor, hereinafter 5 IT
In order to improve the turn-off speed, lifetime control using an anode-emitter short-circuit structure, gold diffusion, or heavy metal diffusion is widely used.

On the other hand, the dual gate type 5IThy, which has a switching speed even faster than the above method and has a lower A current JtJ, has already been proposed by the inventor Kiwan, and has been published in Japanese Patent No. 111565.
No. 6 [Electrostatic Induction Thyristor] and Patent No. 108907
No. 4 [Method for manufacturing electrostatic induction thyristor], the structure and manufacturing method thereof are proposed. Patent No. 1115656-54 discloses that the first gate and the second gate are planar gates, the first gate is a planar gate and the second gate is a buried gate, the first gate and the second gate are buried gates, and the first gate is a buried gate. A structural example of DGSI Thy has been proposed in which the second gate is a planar gate. Moreover, the manufacturing method thereof is proposed in Japanese Patent No. 1115656 and Japanese Patent No. 108907'1.

A high-resistance substrate is used as the substrate, and a process of chemically or mechanically polishing it to a thickness of about 30 to 100 microns is included. Furthermore, in order to remove the electrodes from the first and second gates, etching from both sides of the substrate or very deep etching is required. Furthermore, in the manufacturing process of DGSrThy, which has a structure in which control electrodes are taken out from both sides of the substrate, a masking process from both sides of the substrate is required.

[Problem to be solved by the invention] Since DGSIThy is a 4-terminal element, its M4
The structure and manufacturing method become complicated. Said patent No. 111565
The manufacturing methods shown in No. 6 and Patent No. 1089074 both use a high-resistance substrate and include a process of chemical or mechanical polishing to a thickness of about 30 to 100 μl, so they cannot be used with large-diameter wafers. It is very difficult to handle when using. In addition, in order to remove electrodes from the first and second gates, silicon etching from both sides of the semiconductor substrate, relatively shallow silicon etching and relatively deep silicon etching, or deep silicon etching with several tens of micrometers of the semiconductor substrate left, etc. An etching process must be performed. Furthermore, in the structure in which control electrodes are taken from both sides of the semiconductor substrate, masking processes must be performed from both sides, which poses difficulties in handling and manufacturing.

[To solve the problem - 1 stage 1] In the present invention, the first gate 1 has a top gate structure, the second gate has a buried gate structure, and both gate electrodes are
DG with a structure that can be taken out from one side of the conductor base
This paper provides a method for manufacturing SIrhV, and there have been no proposals regarding the manufacturing process for this structure so far. This WJ fabrication process uses a p'' substrate, all mask processes are performed from one side, epitaxial growth is performed twice, and the anode
The silicon etching required to form the region between the second gates and between the first gate and the second gate and take out the two control electrodes may be performed only once.

Therefore, the above-mentioned manufacturing process is solved, and the DGSI Thy can be manufactured relatively easily.

Production according to the present invention ■ 1) GSIT hy realized by culm
, the first gate goes to the plane Goo 1 and the second gate goes to the buried gate! Therefore, it can handle small to medium power applications such as 600V to 1000V in terms of withstand voltage and 100A or less in terms of current, but the switching speed is extremely fast compared to conventional single gate electrostatic induction thyristors. , and the forward voltage drop is further reduced.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1(a) to FIG. 1 ((1> is the DGS of the present invention [
It is a sectional view showing a manufacturing method of Thy.

The substrate is a p+ silicon wafer 10 with a (111) orientation.
Use. Since the p+ silicon wafer 10 forms the p+ anode region, the resistivity should be as low as possible.

Next, as shown in FIG. 1<a>, a p+ silicon wafer 1 is
For example, a p (p) type epitaxial layer 11 having a resistivity ρ=7o, a culmability of 4 Ωcm, and a thickness of about 12.5 μl is formed on the substrate 0. The resistivity ρ and the thickness of the p(p-) type epitaxial layer 11 are the same as those of the second gate of the DGSrThy of the present invention.
It is determined by the withstand voltage value of i1 between the anodes and the characteristics of the element.

Next, as shown in FIG. 1(b), selective diffusion is performed to form the buried n" second gate region 12. For example, aluminum 13 as a mask material is placed on the p-type epitaxial layer 1. After vapor deposition and a mask process, for example, arsenic ions ΔS+ are implanted under conditions of a surface temperature of 1 x 10" ions 7 cm2 and an acceleration voltage of 80 keV. After implanting ions, the diffusion depth xJ was increased to 4.6/l by annealing at 1150°C for 6 hours in a nitrogen atmosphere! 1 of n+ second gate regions 12 can be formed. The diffusion depth XJ of the n+ second gate region 12 and the distance between the n+ second gate region 12 are:
This is a factor that determines the voltage sum mu by the second gate of DO8I'l''hV of the present invention.The voltage amplification factor μ is the voltage (Vet or It is the ratio of the voltage VATo.The formation of the n+ second gate region 12 may be performed by thermal diffusion, and the impurity is not limited to bΔS, but may also be phosphorus P, etc. It is doped with a mixed impurity such as As, Sb, or the like. A T-bi layer may also be used.

Next, as shown in FIG. 1C, an n-epitaxial layer 14 is formed between the first gate and the second gate. For example, silicon tetrachloride 5iC14 and hydrogen H2 as carrier gas, P CI! as impurity source! 110 using 3
Growth at 0°C increases impurity density from 2x1013 to 5x101'
CIM-3, for example, n- with a thickness of about 210 to 100μ
Epitaxial layer 14 is grown. Epitaxial growth of silicon is performed at a temperature of about 1100°C, so n
+Autodoping from the second gate region 12 to the epitaxial growth layer occurs. For this reason, the n+ second gate regions are likely to be connected in a region with a high n-type impurity density, and the characteristics of the device are likely to become normally-off. Particularly in order to obtain normally-on type device characteristics, it is preferable to form the n--bitaxial layer 14 after growing a thin p-type epitaxial layer. For example, 1 using silicon tetrachloride 3iCf4, hydrogen 1-17 as a carrier gas, and BBrB as an impurity source.
Growth at 100℃ -11 = Impurity density 1 = IX10 cm, thickness: 1-
371m of p-type Evita 4: After forming a shall layer, flush the tank 12 for 5 minutes to purge 1lBr in the reaction tube. This is a method of 1 bitagiliter growth. n-
Kobita 1. Sittle! The thickness and impurity density of 141/I are
6n- determined from the cord breakdown voltage etc. of DGSrT-by.
Epitaph: After forming the t-seal layer 14, as shown in FIG.
) After oxidation and mask 1- or so, boron B is selectively thermally diffused to form the p+ first gate region [15 t! Ru. p+diffusion depth Xj of first gate region 15
The distance between the first gate region and the p+ first gate region is J: the voltage gain μ to the first gate region of the double gate SI thyristor of the present invention.
This is the determining factor. Depending on the thickness of the high-resistance JV layer, for example, the diffusion depth Xj is selected to be approximately 3 .mu.m to 15 .mu.m.

Next, as shown in FIG. 1(e), the 0+ cathode region 17
form. The impurity density in the n+ cathode region 17 is large, and the smaller the diffusion depth Xj, the lower the on-resistance and the better the device characteristics. In order to realize this region, an n0 cathode region 17 is formed using CVD polysilicon doped with phosphorus P as a diffusion source, and CVD polysilicon W41B is
is used as an aluminum electrode and a buffer layer for the n+ cathode region 17. For example, after a mask process for diffusing impurities into the n+ cathode region 17, about 3500 A of phosphorus doping is performed by growing at 700°C for 45 minutes in a system using S I@4, 1''2 as a carrier, and PCf as an impurity source. Form a polysilicon layer. For example, by annealing at 950°C for 20 minutes, the diffusion depth y, J-Q, 5 to 0
．． A 9 μm n+ cathode region can be formed. After that, through a well-known mask process, the polysilicon layer is patterned by plasma 1 zing, and the polysilicon region 1 is patterned.
form 8. Furthermore, after forming a contact hole between the first gate region 15 and the aluminum electrode, a silicon nitride film is deposited. This silicon nitride film layer 19 has n+
A silicon etching mask 4rA that exposes a part of the second gate region 12 and steps the electrode to the second gate 1.
Use F+. The silicon nitride film is, for example, N11.
In a system using 3D Sil+4 and 1-12 as the 21-Yaria gas, growth at 780℃ for 15 minutes resulted in approximately 1300Δ culm degree J.
11% 1) It is possible. The silicon etching mask material used in this process must be formed at a low temperature that does not change the impurity profile formed in the previous process.
It has a high etching selectivity with silicon, and C
V D S n O2, CV I) S I O2, etc. can also be used. After the mask process, the nitride film is patterned by plasma etching, and the Si:1-nitride film formed under the Si:1-nitride film removed by plasma etching is further etched. Then, using the silicon nitride film layer 19 as a mask, the n:I-pitaxylene layer 14 is etched, and the n+ second gate region 12 is etched.
expose a part of This etching is performed by plasma etching or chemical etching. Whether the n+ gate region 12 is exposed or not can be monitored by measuring resistivity using the four-probe method. For example, t-IF: HNOa: C1-13C
OOH-15: Silicon is etched with an etching solution having a volume ratio of 100:5 at an etching rate of about 10 μl Il/n+in at room temperature. There is a possibility that the surface impurity density of the p+ region exposed by the above-mentioned silicon etching culm is considerably reduced in some parts depending on the controllability of silicon etching and the distribution of etching depth within the surface. This increases the contact resistance with the aluminum electrode, leading to a decrease in the switching characteristics of the DGS [Thy]. In order to solve the above-mentioned problem, phosphorus P is ion-implanted to cover the exposed surface portion of the n+ second gate region 12 after the silicon cladding shown in FIG. 1(f). For example, aluminum is used as the mask material. Accelerating voltage 80keV, 3x 101Ston 10
After ion implantation of phosphorus R2, annealing is performed at 950° C. for 20 minutes to obtain a sheet resistance of several Ω/hole.

Next, as shown in FIG. 1 ((J)), aluminum as an electrode is deposited and patterned.The masking process of the aluminum electrode is performed so that the thickness of the 11-]pi full taxi 1 full 14 is relatively shallow, and oGsiT'hV, if the interval between the aluminum electrode patterns is relatively wide, it can be done in one time.However, n''''J
If the bitaxy 1 aluminum layer is 14 layers thick, or if the aluminum electrode pattern is thin and the spacing is narrow, it is better to perform the masking process for the cathode Raijin 21, the first gate electrode 22, and the second gate electrode 23 separately. ,stomach. Furthermore, before the masking process of the aluminum electrode, the part where the series T was formed was resist 1.
~! By filling and planarizing with AII+, polyimide resin, cD polysilicon film (or CVD5i02 film, etc.), even finer electrodes can be patterned.

According to the above manufacturing method, eight mask steps and a relatively easy process [II? DGSIThy with Susakujutsu.

Can be Okawa.

Next, we will explain the operation of DGSTThy, 11-ru, DG-
16=81dhy, is off, the potential barrier at the first true point 1, which is the saddle point of the potential generated in the channel region between the first gate regions, is kept sufficiently high, and the potential barrier from the cathode to Electron injection into the channel is suppressed. Similarly, the potential barrier at the second true gate point, which is the saddle point of the potential generated in the channel region between the second gate regions, is kept sufficiently high, and the injection of holes from the anode to the channel is also suppressed. There is. Next, DGSI
In order to turn on Thy, a forward bias is applied to the first gate and the second gate. Forward biasing the region to the first gate 1 lowers the potential barrier at the first true gate point and increases electron injection from the cathode to the channel.

On the other hand, since the second gate region is forward biased and the potential barrier at the second true gate point is lowered, the injection of holes from the anode to the channel also increases. The injected electrons are the second
Accumulating in the gate region, the potential barrier at the second true gate point becomes lower, further increasing hole injection. The injected holes accumulate in the first gate region, the potential barrier at the first true gate point is lowered by J, and the injection of electrons further increases. Finally, I) Q S I 1'-hy, is the turn
Turn on. Compared to the tl-gate type s+1-hy,
3. DGSNTby has a fast turn-on speed because the potential of two gates can be lowered at the same time. In addition, the hole injection efficiency is 6 tr due to the second gate structure.
Since it increases compared to the i-gate structure, the A current Lt b decreases. Next, to turn off the DGSIThy, the first
A reverse bias can be applied to the gate and the second gate. When the first gate region is reverse biased, the electrons accumulated near the first gate region and the electrons in the channel are sucked out from the first gate region, and the potential barrier at the first true gate point becomes high. Therefore, electrons can be injected from the cathode. At the same time, the second gate region is reverse biased, so that the holes accumulated near the second gate region and the holes in the channel are sucked out from the second gate region, and the second true The potential barrier at the gate point becomes high and the injection of holes from the anode is stopped. DGSIThy turns off when electron and hole injection is closed. Single gate type 5IThV.

Then, at the time of turn-off, the holes accumulated in the second base region can only be reduced by disappearing by recombination or flowing away to the anode side, so there is a so-called tilling time, and the turn-off time is become longer. On the other hand, D.G.S.
In IThy, in order to forcibly extract holes from the second gate region, there is no tilling and the turn-off speed is
Significantly improved. Furthermore, since the potentials of the first and second gates are simultaneously raised, carrier injection is immediately blocked and the current gain flowing to the first and second gates is also increased.

[Effects of the Invention] Among the embodiments of the present invention described above, DGSIThy manufactured by the manufacturing method of the embodiment shown in FIG. 1(a) to FIG. 1(0), which is the most basic part, An example of the characteristics will be explained.

The area of the manufactured element is 1.24 x 2.34 mm,
Number of channels: 66, p''-first gate]-interval and n+second gate I-interval is 10 μm, tunnel length is 1.
At 385m+n, (i rir. The first and second gates are 4'r-,)'C in parallel.

The circuit of current-voltage characteristics f1, l+,'l by the first gate control of the fabricated DGS I 1 hy is shown in Figure 2 (
In Fig. 2(b), the current generated by the second goo (a) and the electric current generated by the opening 11 and the circuit at that time are shown in Fig. 2(b). Second
In Figure (a), measurements were taken with the second gate open. A voltage of 120V between the anode and the cathode is blocked with a bias of 1 to the first gate, and a voltage of about 180V is blocked with a first gate bias of -1.5V. It is turned on at the first gate bias of 0.6V. The first gate is in an open state in the electric current-electric control circuit shown in FIG. 2(b) due to the second gate control. The second gate bias O is the bias voltage between the anode and the second gate.
V, approximately 120V is closed, and the second group 1 is turned on at bias -0.6V. The characteristics of 7S: DG = 20 - 8IThy shown here are that both the first gate control characteristic and the second control characteristic are normally off, but there are combinations such as the first gate being normally on and the second gate being normally off. Conceivable. FIG. 3(a) shows the switching waveform of 1) GSIThV, in which the first gate is driven electrically and the second gate is driven optically, and the measurement circuit at that time is shown in FIG. 3(b). In Figure 3 <a>, V^ is the anode voltage waveform, IAK is the anode current waveform, and Vol is the first
It shows the gate pulse waveform applied to the MOS I-run lister that drives the gate. Also, in Figure 3(b), n
Channel 5IPT is an n-channel static induction transistor for optically driving the second gate, p-channel M
O8 and n-channel MO8 are MOS t-run listers for driving and overturning the first gate, and LQ is a quenching optical pulse. In addition, in FIG. 3(b),
=1.04Vs VcTIQ=3.94V,,V
62Q=5. OV, Ω at Rt=10, Ω at R2=10,
R3=100Ω, R4=500, Vl=1.82V
1 V2 = 3. 5V, V! l-5V, RL-1
00Ω. Pulse voltage of the first gate drive -9,
4V, Rinji light pulse intensity 10nlW/cm2 J3
, anode voltage H: vAK-100V, anode current IAK-18, turn-on time 830 ns, turn-on time 8/1. Switched by Ons-
(The anode current 1A is equal to the anode current 191f of approximately 30A/CI1+2.)
It is equivalent to 1α. Also, A current 1 when the anode current is 1A]
- is 1.6v. As a driving method for D G 84 T hy, there is a method of driving the first gate and the second gate with light, and of course, it is also possible to drive both gates 1- electrically, or to drive the first gate electrically. Drive the second gate with light.

According to the manufacturing method according to the present invention, high efficiency and high speed DGSI can be achieved with a relatively easy process of using 8 masks. The present invention is particularly suitable for high speed, small and medium power sectors.
Provides high-efficiency switching elements and has high industrial value.

[Brief explanation of drawings]

FIGS. 1(a) to 1(a) show the DGsy-
2 (a) is a cross-sectional view showing an example of the manufacturing method of rhy.
) is a photo and circuit diagram of the oscilloscope waveform showing the current-voltage characteristics due to the first gate control of DGSIThy, Figure 2(b)
is DGSIThy. Figure 3(a) is a photograph of an oscilloscope waveform showing the current-voltage characteristics due to the second gate control of DGSIThy, and a circuit diagram thereof.
) is a switching measurement circuit diagram of oGsrrhy. DESCRIPTION OF SYMBOLS 10...p+ silicon wafer, 11...p(p) epitaxial layer, 12...n+ second gate region, 13
．． 20... Aluminum for mask, 14... N- epitaxial layer, 15... P+ first gate region, 16...
Silicon oxide film, 17...n+ cathode region, 18.
...Polysilicon region, 19...Silicon nitride film layer,
21... Cathode electrode, 22... First gate electrode,
23... Second gate electrode, 24... Anode electrode = 23 - r-do5\mo A 〆-1 (] r) \←) qtun and -1 1 also VGIK (V) <a-an VG2A (V) (G) ts2 diagram

Claims (2)

[Claims] (1) an anode region of a first conductivity type, a first low impurity density region of the first conductivity type adjacent to the anode region, and a second conductivity type adjacent to the first low impurity density region; a second conductivity type cathode region adjacent to the second low impurity density region and having a higher impurity density than the second low impurity density region; a first conductivity type surface gate region adjacent to the low impurity density region and forming a first pn junction between the first low impurity density region and the second low impurity density region; a second conductivity type buried gate region adjacent to the low impurity density region and forming a second pn junction with the first low impurity density region; and a second conductivity type buried gate region formed on the cathode region. a conductive type polycrystalline silicon region, a cathode electrode formed on the polycrystalline silicon region, and an anode electrode provided on a surface exposed portion of the anode region;
a first gate electrode formed on an exposed surface portion of the front gate region; and a second gate electrode formed on an exposed surface portion of the buried gate region, and between the anode electrode and the cathode electrode. A double gate electrostatic induction thyristor characterized in that a flowing current is controlled by a voltage applied between the first gate electrode and the cathode electrode and a voltage applied between the second gate electrode and the anode electrode. a first step of growing a first low impurity density silicon epitaxial layer of a first conductivity type on the surface of a semiconductor substrate of a first conductivity type; a second step of oxidizing the surface exposed portion of the impurity density silicon epitaxial layer and then diffusing a second conductivity type impurity through a mask step to form the buried gate region; a third step of growing a second low impurity density silicon epitaxial layer of a second conductivity type on the high density silicon epitaxial layer; and oxidizing the exposed surface portions of the semiconductor substrate and the second low impurity density silicon epitaxial layer. After that, a first conductivity type impurity is diffused through a mask step to form the surface gate region, and after oxidizing the surface exposed portions of the semiconductor substrate and the second low impurity density silicon epitaxial layer, A second conductivity type polycrystalline silicon layer is deposited through a mask process for diffusing impurities into the cathode region, and the second conductivity type impurities are transferred from the polycrystalline silicon layer to the second low impurity density silicon layer. A fifth step of plasma etching the polycrystalline silicon layer after the mask step for forming the cathode region by diffusing it into the epitaxial layer and forming the polycrystalline silicon region, and a mask such as a silicon nitride film. The second low impurity density silicon epitaxial layer is etched through a masking process to expose a portion of the buried gate region, and a second conductivity type is applied to the surface exposed portion of the buried gate region. a sixth step of ion-implanting impurities and annealing; depositing an electrode material; and after a masking step, the electrode material is etched to form the cathode electrode, the anode electrode, the first gate electrode, and the second gate electrode; and a seventh step of forming a gate electrode. (2) In the method for manufacturing a double-gate static induction thyristor according to claim 1, between the second step and the third step, the first low impurity density silicon epitaxial layer is A method for manufacturing a double-gate static induction thyristor according to claim 1, further comprising the step of growing a silicon epitaxial layer of the first conductivity type.