JPS62115877A - Junction field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form an ohmic electrode to an active layer in a self-aligning manner by recess etching the gate of a field effect transistor active layer, and then implanting an impurity having different conductivity type from the active layer only in the recess. CONSTITUTION:An N-type InGaAs layer 2 of one conductivity type active layer, and an InP layer 3 are sequentially grown on an SI-InP substrate 1. Then, the entire substrate is covered with an SiO2 film 4 as a first etching layer, and a gate forming portion is opened. Then, with the layer 4 as a mask a groove 5 which arrives at the layer 2 is formed by etching of bromomethanol. Then, the layer 4 is removed, and a P-type impurity or Cd is diffused in the entire substrate to form a P<+> type layer 6 of other conductivity type layer. Then, the groove 5 is covered by lithography, and an SiO2 layer 7 is formed as a second etching layer at an interval from source, drain electrodes formed in later steps separately from the groove 5. Then, the layer 3 is removed by etching with hydrochloric acid, covered with Au/AuGe of conductive layer to form Au/AuGe layers 8S, 8D, 8G in a self-aligning manner. Thus, a high speed junction FET having small source resistance and gate capacity can be obtained.

Description

[Detailed Description of the Invention] [Summary] After etching a recess (indentation, groove) in the gate part of the active layer of a field effect transistor (hereinafter abbreviated as FET), an impurity having a conductivity type different from that of the active layer is added only in the recess. We introduce a structure in which an ohmic electrode to an active layer is formed using a self-line, and a manufacturing method.

[Industrial Application Field] The present invention is a junction type FE with reduced source resistance and gate capacitance.
Regarding the structure and manufacturing method of T.

Indium gallium arsenide (InGaAs) has higher mobility and better high-speed response than gallium arsenide (InGaAs), and can be expected to have higher mutual conductance gm.

In addition, optical integrated circuits (OBIC, 0pto-
IElectronic Integrated C1
research and development of rcuits) is about to become more active.

However, InGaAs has a small forbidden band width, and GaAs
Since it is more difficult to create a Schottky barrier, a junction type FET is used. There are also MIS type structures,
The characteristics are not good.

Therefore, there is a need for a structure and manufacturing method that can produce an InGaAs junction FET using a self-line process, obtain good characteristics, and be applicable to 0EIC.

[Conventional technology]

FIG. 4 is a cross-sectional view illustrating the process of forming a junction in a conventional junction FET.

In the figure, 41 is a substrate made of semi-insulating indium phosphide (Sr).
-InP) substrate, on which n-type indium gallium arsenide (n-1nGaAs) N42 is grown as an active layer, a gate mW region is opened in the diffusion mask 43, and zinc (Zn) is grown as a p-type impurity. -1nGaAs layer 42 to form a p'' type region 46.

In this way, when diffusion is performed in the flat active N42, when the active layer is thin, the lateral spread of the diffusion is small, so the gate capacitance is relatively small, but the source resistance becomes large.

On the other hand, if the active layer 42 is made thicker in order to reduce the source resistance, the diffusion must be deep, which increases the lateral spread of the diffusion, resulting in an increase in gate capacitance.

[Problem that the invention seeks to solve]

It has been difficult to simultaneously reduce the source resistance and gate capacitance of conventional junction FETs.

[Means for solving problems]

The above problem can be solved by forming a layer (6) of another conductivity type on the surface of the groove (5) formed on the semiconductor active layer (2) of -g type, and forming the layer (6) of the other conductivity type. The semiconductor active N
(2) Depositing N (3) made of a more easily soluble substance,
A first etching-resistant layer (4) with an opening in the gate region is formed on this layer, and etching is performed using the first etching-resistant layer (4) as a mask. 3) and a portion of the semiconductor active layer (2) in the thickness direction is removed to form a groove 5.
the first etching-resistant layer (4) is removed, and impurities of a different conductivity type are introduced from the exposed surfaces of the layer (3) made of the easily soluble substance and the semiconductor active layer (2). to form a layer of another conductivity type (6), and a second anti-corrosion layer (7) covering the groove 5.
was formed, the layer (3) made of the easily soluble substance was removed by etching using this as a mask, a conductive layer was deposited, and conductive layers (8G), (8S), (
8D) and removing a second 100 etching layer (7) and a conductive layer (8G), and a semiconductor active layer (2) of one conductivity type. A first anti-corrosion layer (4) with an opening in the gate 6i region is formed on top of the semiconductor active layer (2) by etching using the first anti-corrosion layer N(4) as a mask. A5 is formed by removing a part of the semiconductor active layer (2) in the thickness direction, and the first anti-etching layer (4) is removed, and an impurity of another conductivity type is introduced from the exposed surface of the semiconductor active layer (2). to form a layer of other conductivity type (6),
A second anti-corrosion layer (7) is formed to cover the groove 5, a part of the semiconductor active layer (2) in the thickness direction is removed by etching using this as a mask, and a conductive layer is deposited. , manufacturing a junction field effect transistor including the steps of forming conductive layers (8G), (8S), (8D) in a self-line, and removing a second anti-etching layer (7) and a conductive layer (8G) This is accomplished by a method.

[Effect]

(1) By forming a junction within the recess formed in the gate portion, source resistance and gate capacitance can be reduced.

(2) Growing an easily soluble upper layer on the FET active layer,
After performing recess etching to reach the active layer, impurities with different conductivity from the active layer are introduced into the entire surface of the active layer, the gate area is covered with an anti-corrosion layer, and the upper layer is selectively removed. An ohmic electrode to the active layer is formed using self-alignment.

(After performing recess etching on the 31FEET active layer,
Introducing impurities with different conductivity from the active layer to the entire surface of the active layer,
The impurity-introduced layer (other conductivity type layer) other than the gate portion is removed by etching, and the lateral etching is used to form an ohmic electrode to the active layer with a self-line.

〔Example〕

FIG. 1 (11, (2)) is a cross-sectional view and a plan view illustrating the structure of a junction FET according to the present invention.

In the figure, 1 is a substrate of 5I-InP, 2 is an n-InGaAs active layer of one conductivity type, 5 is a groove, 6 is a p-type layer of another conductivity type, 8S and 8D are source and drain electrodes. ,
Gold/gold germanium (Au/AuGe) as conductive layer
layer 9 is a gate electrode made of gold/zinc/gold (8u/Zn/Au
) layer.

Figures 2 (1) to (6) show junction FETs according to the second invention.
FIG.

In FIG. 2 (1), 1 is a substrate, which is a 5l-InP substrate, on which an active layer of one conductivity type is formed with a carrier concentration of 1×10110l.
7', n-InGaAs layer 2 with a thickness of 0.3 μm, InG
An InP layer 3 is successively grown as a layer that is more soluble than aAs.

Next, a silicon dioxide (SiOz) layer 4 is deposited as a first etching layer over the entire surface of the substrate, and a gate forming area is opened by normal lamination lithography.

In the second [1(2)], using the SiO
A groove 5 is formed so as to reach the aAs layer 2.

Next, the SiO□ layer 4 is removed.

In Figure 2 (3), Z
n or cadmium (Cd) is diffused to form a p" type layer 6 as a layer of another conductivity type.

In FIG. 2 (4), a SiO□ layer is formed as a second etching layer by lithography to cover the groove 5, to be separated from the groove 5, and to have a predetermined distance from the source and drain electrodes to be formed in a later process. form 7.

In Fig. 2 (5), “InP” was formed by hydrochloric acid etching.
Selectively remove layer 3.

In Figure 2 (6), the thickness of the conductive layer is 2700/3.
After depositing 0000000 Au/AuGe, the u/AuGe layers 8S, 8D, and 8G are formed in the self-line.

After this, the SiO□ layer 7 is etched and Au/AuG
The p layer is removed together with the e layer 8G, as shown in FIG.
A with a thickness of 2400/300/300 on the type layer 6
The main process is completed by forming the u/Zn/Au layer 9.

Figures 3 (1) to (7) show the joint type FIE according to the third invention.
It is a sectional view explaining the process of T.

In Figure 3 (1), ■ is a 5l-1nP substrate, on which a gearia concentration of 1 x is formed as an active layer of one conductivity type.
10"cm-', 0.3 prn thickness n-InGaA
Grow s-layer 2.

Finally, a SiO□ layer 4 is deposited as a first etching layer over the entire surface of the substrate, and a gate formation portion is opened by lithography.

In FIG. 3(2), using the Sin layer 4 as a mask,
Perform bromo-methanol etching to obtain n-InGa
Grooves 5 are formed in the As layer 2.

Next, the SiO□ layer 4 is removed.

In Figure 3 (3), Z is added as a p-type impurity to the entire surface of the substrate.
n is diffused to form a p° type layer 6 as a layer of another conductivity type.

In FIG. 3(4), a Sin2 layer 7 is formed as a second etched layer by lithography to cover the groove 5 and to be separated from the groove 5 and at a predetermined distance from the source and drain electrodes to be formed in a later process. form.

In FIG. 3(5), using the Si02 layer 7 as a mask,
n-InGa is etched by methanol-based etching.
Part of the AsN2 is removed in the thickness direction.

At this time, the etching also proceeds in the lateral direction, forming 20 mesas of n-InGaAs having a width corresponding to the gate length.

In Figure 3 (6), the thickness of the conductive layer is 2700/3.
When uGe is deposited on U/00 people, Au/AuGe layers 8S, 8D, and 8G are formed in the self-line.

In FIG. 3(7), the SiO□ layer 7 is etched and removed together with the Au/ΔuGe layer 8G, and a layer of 2400/300/300/300 in thickness is deposited on the p° layer 6 as shown in FIG.
The main process is completed by forming 300 Au/Zn/Au layers 9.

In the example, InGaAs was used for the active layer, but GaA
Other semiconductors such as s may also be used.

〔Effect of the invention〕

As described above in detail, according to the present invention, a high-speed junction FET with low source resistance and low gate capacitance can be obtained.

[Brief explanation of drawings]

Figures 1 (1) and (2) are cross-sectional views and plan views illustrating the structure of a junction FET according to the present invention, and Figures 2 (1) to (6) are junction FETs according to the second invention.
3 (1) to (7) are cross-sectional views explaining the process of the junction type FET according to the third invention.
FIG. 4 is a sectional view illustrating the process of forming a junction of a conventional junction FET. In the figure, ① is a 5I-1nP substrate, and 2 is an active layer of n-1nGaAsF. 5 is a recess, 6 is a p-type layer 8S which is a layer of other conductivity type, 8D is an Au/AuGe layer which is a source and drain electrode, and 9 is a gate electrode which is a ^u/Zn/Au layer. None) CI) A-A trace Menki Iaki Q Pressure T's morning wholesale plan m1 Figure l Flash 4.3iO2 弗3 Figure oJsri'I+J-3FETf)'folk7) (Figure 4 Procedure Fu Zhengshi (method % formula % 2, name of the invention Junction field effect transistor and its manufacturing method 3,
Relationship with the person making the amendment Patent applicant address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture (5
22) Name: Fujitsu Co., Ltd. Company 4; Agent Address: 1015 Kamiodanaka, Nakahara-ku, Yozaki-shi, Kanagawa Prefecture Tomi
Shitsu Co., Ltd. January 280, 1980 (Shipping date) 66 Subject of amendment

Claims (3)

[Claims] (1) A layer of another conductivity type (6) is formed on the surface of the groove (5) formed on the semiconductor active layer (2) of one conductivity type, and is separated from the layer of other conductivity type (6). Conductive layer (8S) on both sides,
A junction field effect transistor characterized in that (8D) is formed. (2) A layer (3) made of a substance more soluble than the semiconductor active layer (2) is deposited on the semiconductor active layer (2) of one conductivity type, and a first layer (3) with a gate region opened thereon is deposited. Corrosion-resistant engraving layer (
4) and etching using the first anti-etching layer (4) as a mask,
A groove 5 is formed by removing a portion of the layer (3) made of the easily soluble substance and the semiconductor active layer (2) in the thickness direction of the opening, and the first anti-corrosion layer (4) is removed. After removal, an impurity of a different conductivity type is introduced from the exposed surface of the layer (3) made of the easily soluble substance and the semiconductor active layer (2) to form a layer (6) of the other conductivity type, and a groove 5 is formed. A second anti-corrosion layer (7) is formed covering the second anti-corrosion layer (7), and the layer (3) made of the easily soluble substance is removed by etching using this as a mask.A conductive layer is deposited and conductive in a self-aligned manner. layer (8G),
(8S) and (8D), forming a second corrosion-resistant etching layer (7),
A method for manufacturing a junction field effect transistor, comprising the steps of: and removing a conductive layer (8G). (3) A first etching-resistant layer (4) with an opening in the gate region is formed on the semiconductor active layer (2) of one conductivity type, and etching is performed using the first etching-resistant layer (4) as a mask. Then, a part of the opening in the thickness direction of the semiconductor active layer (2) is removed to form a groove 5.
The first etching-resistant layer (4) is removed, and an impurity of another conductivity type is introduced from the exposed surface of the semiconductor active layer (2) to form a layer (6) of another conductivity type. , a second anti-etching layer (7) is formed covering the groove 5, a part of the semiconductor active layer (2) in the thickness direction is removed by etching using this as a mask, and a conductive layer is deposited. , self-aligned conductive layer (8G),
(8S) and (8D), forming a second corrosion-resistant etching layer (7),
A method for manufacturing a junction field effect transistor, comprising the steps of: and removing a conductive layer (8G).