JPS61222272A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD This invention relates to semiconductor circuits, and more particularly to semiconductor circuits including various substrate structures.

Misara Natsumi In both communication technology and computer technology, m-v
Demand for the field of integrated circuit technology is increasing. These demands include higher speed, higher sensitivity, greater gain, higher packing density, and tighter tolerances of circuit elements.

Of particular importance in the manufacture of m-v integrated circuits is the nature of the substrate material. In particular, the resistance of the substrate for isolating the various elements of the integrated circuit and the trap density at the substrate-to-circuit interface are important. High trap densities create hysteresis effects in the current-voltage characteristics of integrated circuits, which can provide desirable properties such as noise efficiency and circuit stability.

Conventional integrated circuits using field effect transistor (FET) or junction field effect transistor (JFET) devices typically use semi-insulating indium phosphide substrates to provide electrical isolation between circuit elements. There is. Such circuits can be found in many publications, such as D. Wake et al.
lectron Device Letters LV
ol, EDL-5, No. 7 (July 1984).

Quit. Y, G, Chai et al. Electron Device Letters%Vo1
．． See EDL-4, No. 7 (July 1983), although these circuits using semi-insulating indium phosphide substrates operate, the circuits have a substantially low defect density between the substrate and the circuit elements. is strongly desired. moreover.

In semiconductor circuits using multiple FET elements or FET elements incorporated into other device elements such as photodetector elements or diode elements, semi-insulating substrates offer flexibility, ease of integration, or advantageous integration. It often interferes with the shape.

1 Lesson 111 Summary The present invention is a device including one or more m-v semiconductor integrated circuits, and the substrate of this integrated circuit is a p-type -
(2) Primarily consisting of highly doped indium phosphide (n-type or p-type) whose surface is in contact with an m-v semiconductor integrated circuit made of a semiconductor compound.The present invention includes several specific substrate configurations. One board configuration is P1In as a whole.
Consists of P. A typical dopant for such substrate materials is zinc in a concentration range of 2-40.times.10@17 atoms/33. (Cd, Mg and Be are also useful.)
Another substrate configuration is N”I covered with a p-type epitaxial layer.
It is a flat plate of nP. The p-type epitaxial layer contacts the integrated ■-■-■ body circuit. Typically, N”In
The P plate is doped with S or Sn in a concentration range of about 2-40xlO17 atoms/cs3. (Si and Te are also useful.) The p-type epitaxial layer can be any layer that is consistent with the N''InP surface and is generally lattice matched to the N''InP. Semiconductor semiconductor gold compound.

A typical example is P”I, which has a composition lattice matched to InP.
n Ga As (habo I n,,, Ga,
,4. A s ) and S P” InG which is P”InP
A typical dopant for aAs and P''InP epitaxial layers is Be in a concentration range of 2-60.times.10'' atoms/alI3. Such a substrate configuration is highly advantageous due to the low defect density at the interface between the substrate and the integrated circuit structure. Typical integrated circuit configurations incorporate amplifier structures (field effect transistor structures), particularly junction field effect transistors (JFETs). Generally, the integrated structure includes a multiplex structure of JFETs or other circuit elements, often optical circuit elements such as photodetectors (e.g. PINF
It is a multiple structure of JFET integrated with ET)). Such circuits have better frequency response, lower noise characteristics, higher yield, higher reliability, and are easier to fabricate. Another advantage is that it creates the possibility of using the back gate electrode, which is used to electrically control the gain of the JFET.

The present invention relates to the discovery that a variety of novel substrate structures are useful in semiconductor devices and that these novel substrate structures provide surfaces on which the active elements of the devices are formed. It is based on the use of p-type materials for this purpose. This p
The surface of the mold material is often used as a channel-defining surface or layer in field-effect devices; potential applications include FE, including integrated circuits and integrated optoelectronic circuits.
There are amplifiers, logic circuits or memory circuits that use T or JFET devices.

The invention is best explained by describing a single junction field effect transistor. A side view of such a structure is shown in Figure 1, which is a specific example of a JFET and an FE
This is for explaining the use of a p-type substrate or p-layer as a channel defining layer in a T structure or a 'JFET structure.

The JFET structure 10 is made of a substrate 11 of P''InP with a layer 12 of n-type lattice matched indium gallium arsenide on top. functions as

A drain electrode 13 and a source electrode 1 are formed on the channel layer.
There are 4. These are usually made of gold-germanium, gold-silicon or gold-tin and are usually heat treated to make ohmic contacts. Between the source and drain there are small pillars 15 of p-type semiconductor, which together with the n-type channel layer 12 form the p-n junction of the structure.

For convenience, this p-layer is referred to as the Goo-82 layer. The gate electrode 16 is located on the goo 82 layer 15. The gate electrode typically protrudes from the trabeculae by about 0.1 to 1.0 μm.

The gate electrode is generally made of a gold alloy such as palladium-gold, zinc-gold, or a non-alloy material such as chromium-gold, although other electrode materials can be used.

Particularly desirable are short columns of P-type material.

Typically the length of the columns is less than 5 μm, and even 2 μm.
Or less than 1 μm.

The essential feature of this structure is that the gate electrode 16 is made of p-type material (
It protrudes from the 15 pillars (82 layers). It is this protrusion of the gate electrode from the p-type material column that allows precise alignment of the source and drain electrodes with respect to the p-n junction without the need for special readjustment steps.

Here, the gate electrode acts as a shadow mask when depositing the drain and source electrodes. The amount of protrusion is controlled by undercutting in the etch process that removes most of the p-layer. The source and drain electrodes are generally formed by vapor deposition, and the degree of proximity of the source and drain electrodes to the pn junction is determined by the amount of protrusion of the gate electrode.

Implants may be used prior to metal deposition to form suitable source and drain electrodes.
8) can be reduced by implanting ions into the surface. Various alloys and metal mixtures can be used for similar purposes.

FIG. 2 shows a plan view of the same structure with drain electrode 13, source electrode 14 and gate electrode 16, and also shows the gate pad 21 and a portion 22 of the gate electrode in which the air bridge is located.

It may be useful to make a note about naming here.
The dimension of the gate electrode that points toward the source and drain electrodes in the plane of the channel layer is called the gate length, although it is usually the shorter dimension of the gate electrode. The direction perpendicular to the length, which typically extends between the source and drain electrodes and is often the longer dimension of the gate electrode, is referred to as the gate width. The directions in which the width and length of the gate electrode are measured are shown in FIG. 2 (direction W represents width and direction W represents length). It is desirable that these devices be oriented in some way with respect to the crystal plane of the semiconductor material, such that the plane on which the epitaxial layers and devices are deposited (plane of the paper in Figure 2) is [10
01 crystal plane, and the gate width is made along the <110> crystallographic direction.

The above structure consists of a channel layer and a Goo 82 layer (pillar 1 in Figure 1).
It should be recognized that 5) can be fabricated using a wide variety of semiconductor materials.

For example, the n-type and p-type materials can be the same or different.

Semiconductor material systems with high mobility and saturation velocity, or materials related to such materials (generally lattice matched), are desirable; such materials include indium.
Phosphorus, indium gallium arsenide (generally has a composition of approximately I no, s 3G a a 4 t A 8 and is lattice matched to choleheinium phosphorus), aluminum indium arsenide (for example A Q , 4゜In ,,
, □As), and indium gallium arsenide phosphide and indium gallium arsenide phosphide lattice matched to indium phosphide
It is a quaternary compound such as aluminum arsenic.

Such a composition is H,C,Ca
5ay) and M, B, Vanish (M, B, Pa
n1sh)'s "Heterostructure Laser" (Heterogt
ructura la5ers), published by Academic Press, New York, 1978, in particular Part B ``Materials and Operat J.
ing Characteristics).

I n as n-type material 6. B @ G a e, 47
As p-type material, InP or In 11
．． 13 Ga 0.4? It is most convenient to use A s.

It may be useful at this point to briefly outline various preferred dopants and their preferred concentrations for use in the p-type and n-type layers. It is to be understood that these are typical dopants and typical concentration ranges, and that the present invention may be practiced with other dopants and other concentration ranges; furthermore, the dopant concentrations may vary with the thickness of the various layers. However, it may be very high near various electrodes to improve electrical contact characteristics. A typical n-type dopant is Sn with a typical concentration range of 101m to 1017 atoms/cm'.

They are Si, S and Te. For InP and InAlAs, the range of 8-9×10 "i/cm" is In
4-7 x 1011 atoms/am for Ga As
"range is 6-8X10" for InGaAsP
A range of atoms/cm' is most preferred. For the p-type layer, typical dopants are Cd, Zne M& and Be, with a concentration range of 101 m-1o L@atoms/cm''. In order to obtain a low resistance ohmic contact between the electrode and the p-layer Near the gate electrode the doping concentration may exceed this range (usually approaching xo20 atoms/am').

The thickness of the n-type and p-type layers may vary widely depending on the desired application. Thicknesses of a few μm are useful. Usually 1
The thickness of the n-type layer, which is preferably less than .mu.m thick, generally depends on the material, doping concentration, desired characteristics of the device, etc., but is typically in the range of 0.1 to 0.7 .mu.m. p
The layer thickness is usually less than 1 μm.

The thickness of the p-layer is often close to the desired undercut under the gate electrode, often around 0.5 μm.

An important feature of the invention is the use of PInP as the substrate. This also functions as a channel definition layer.

Conduction electrons are pinched off to this channel defining layer during operation.

The advantage of such a structure is the low defect density at the substrate-channel layer interface, which results in a low defect density not only at the interface but also throughout the channel and goo 82 layers.

Another substrate structure is shown in FIG. This figure is shown in Figures 1 and 2.
3 is a side view of a JFET structure 3o similar to the structure shown; FIG. Here, the substrate is made of a relatively thick layer 31 of N''InP.

Layer 31 may alternatively be P''InP, and is generally grown in large quantities. On top of this layer is approximately lattice matched (or at least properly grown on) N+InP 31.
An epitaxial layer of p-type material is disposed. A typical layer is P” InGaAs (e.g. 2-40X10” atoms/
In doped with Be in the range of cm3,
, 3G a , , , As ) and P InP doped as described above.

The remainder of the structure is similar to FIG. P
A channel layer 33 is disposed on the + type epitaxial layer 32, which is typically n −I n Ga
As or n-InP. Part of the channel layer is covered with n-type contacts (one for the drain electrode and one for the source electrode). These electrodes are generally made of gold-germanium, gold-silicon or gold-tin and are heat treated so that the n-type dopant diffuses into the channel layer to form a narrow region 36 of highly doped (n+) surface. administered. This provides excellent ohmic contact. Ion implantation may also be used to form highly doped surface region 36. Also shown are a goo 82 layer 37 and a gate electrode 38.

Large arrays of JFET structures made as described above are useful for a variety of applications including, for example, logic circuits, memory circuits, etc., where even more complex structures may be used in practicing the invention.

The invention can be further illustrated using more complex structures, for example where optical and electronic structures are integrated on the same substrate structure. In particular, an integrated photodetector amplifier structure is described using a PIN photodetector and a JFET amplifier. This structure is commonly called a PINFET.

The schematic structure of a PINFET is best seen from its side view. The side view of the PINFET shows the epitaxial structure,
JFET from p-diffused region and p-contact on PIN photodetector
The air bridge to the gate electrode of the structure is clearly shown. A side view of the PINFET is shown in FIG. 4 as a cross section of the PIN photodetector portion and the gate of the field effect transistor. The PINFET 40 is made of layers of m-v semiconductor compound starting with a substrate 41, which is generally 1- 5×10
N InP doped with tin or sulfur in the range of 1@atom/cm". This layer is typically about 150 μm thick. On top of this layer is I lattice matched to the InP.
nGaAs (schematic composition I no, sa Ga 0.
4. There is a true layer 42 of As).

This layer generally contains a lightly n-type doping impurity at a concentration of about 5.times.10"atoms/cm". The thickness of this layer is approximately 5 μm. The bandgap of this layer (0,75
eV) is such as to ensure the absorption of radiation incident on this layer (radiation with energy greater than 0.75 eV or wavelength shorter than 1.65 μm), and the doping level is such that the electric field gradient is distributed across the layer. (as low as theoretically possible).

Above this layer 42 is placed a thin layer 43 of p-type semiconductor material lattice matched (or at least compatible) with the InP system. This layer is called the channel definition layer. Materials with large band gaps (e.g. band gap 1
．． 35eV P-InP or bandgap 1.4e
P -I n A Q A s ) of V is often preferred to avoid voltage breaktown, but especially if compatibility with the underlying layer 42 and the overlying layer 44 makes manufacturing easier. Other materials may be advantageous; for example, when absorption layer 42 and channel layer 44 are InGaAs, p-InGaAs may be preferred.

Two semiconductor layers used to form the n and p layers of the JFET are arranged on the channel defining layer 43. These layers are n-type I n Ga As 44
and p-type InGaAs 45, both of which are lattice matched to InP. Other materials (InP or InGaAsP according to JJK rules) may be used for these layers; typical thickness is 0.4 μmpI n for n-InGaAs.
In the case of G a As , it is 0.6 μm. , these layers are the n-type JFET layer or channel layer, and the p-type JFET layer or channel layer.
It is sometimes called the FET layer or Goo82 layer. These layers are detailed below.

Various metallizations are also included as part of the P I NFET structure. For example, the N-InP substrate 41 has an n-type contact 46 (typically an A
u −S n ) is added 1 Usually, n-type contact 4
The surface of the N''-InP exposed by the aperture in
flexion, AR) coating 47.

Additionally, several p-contacts, typically made of CrAu alloys, are also shown. For example, such an alloy forms the p-contact 48 for the PIN gate and the p-contact 49 for the JFET gate electrode of the structure. Similar metallization forms an air bridge 50 connecting the PIN portion of the circuit to the gate 49 of the JPET. Contact to the pack gate is via contact 54, typically made of the same metal composition as gate electrode 49.

Furthermore, a P+ type region 51 forming a P region of a PIN structure.
is also shown. This is generally true.

Zinc is added to the top two layers (
44, 45). Doping concentrations are typically in the range of lo-m-101'' atoms 7 cm''. Some passivation layer (e.g. 5iNx) may be used, but is not shown.The source and drain electrodes are not shown in Figure 4, as the portion shown runs down the center of the gate electrode. Not yet.

Since the p-layer is used as the channel defining layer, other variations are possible in forming the PIN junction. Here, instead of the P+- type region 51, a p-contact of a PIN structure is formed for direct contact with the channel defining layer 43.

This is done as follows. That is, first, the two layers 4 located below the channel layer and the P contact region of the PIN structure.
A small portion of 5 is etched or removed so that the p-contact then contacts channel defining layer 43 to form a PIN junction.

Two important features of the invention are worth highlighting. namely, a gap 52 under the air bridge 50 that isolates the PIN electrode from the JFET gate electrode, and a mesa isolation moat 53 that surrounds and isolates the PIN structure from the JFET structure. Another advantage is that the p layer is used as the channel defining layer. This allows the use of better semiconductor materials with lower defect densities at various interfaces.

FIG. 5 shows a perspective view of a similar structure with a p-contact 4e, an air bridge 50 and a gate electrode 49 of a JFET structure on the PIN photodetector.

Furthermore, P-type InGaAs45 and n-type InGaAs present in both the PIN and JFET parts of the structure
s layer 44 is shown. The p-type I n Ga As in the JFET part of the structure lies below the gate electrode. These layers connect the PIN and J portions of the structure to provide electrical isolation between the photodetector and amplifier portions of the structure.
It is removed between the PETPE tops (at the bottom of the air bridge 52). A channel defining layer 43 is present below these layers to electrically isolate the PIN portion of the structure from the JFET portion of the structure and to function as a channel defining layer in the JFET structure.

Next is the absorption layer 42, typically InP and N''-I
It is made of InGaAs which is lattice matched to the nP structure 41. N-type contact layer 55 serves as one of the electrical contacts to the structure.

A p-type contact layer 49 is shown on top of the structure.

What is highlighted in FIG.
It extends to 3. This forms a p-n junction of the photodetector and provides conduction to the p-contact 48 of the PIN photodetector. Furthermore, a circuit diagram of the structure is shown in the figure. As previously mentioned, another way to contact the p regions for a PIN junction is to drill holes in p and layers 44 and 45 to form a p contact on channel defining layer 43. This avoids the formation of p region 51.

Further shown in the figure are a drain electrode 55, a source electrode 56, and a back gate electrode 54. Again, for the drain and source electrodes, the protrusion of the gate electrode acts as a shadow mask, and these electrodes are made of PInGaΔS.
It is configured to act in such a way that it can be accessed without actual electrical contact to the pillar.

A particular advantage of the structure of the invention is its ease of manufacture in obtaining optimum operation. It is convenient to begin the description of the manufacturing method with the layer structure 60 shown in FIG. This structure is N
It can be made using various epitaxial layer growth techniques starting from +-InP substrates.

Structure 60 includes an N-InP substrate 61 doped with sulfur or tin in the range of 1-5X10"atoms/(!l", which substrate 61 is typically reduced to a thickness of 1 mm later in the manufacturing process.
The final thickness is reduced to 50 μm. An undoped layer 62 of InGaAs about 5 μm thick is formed over the substrate. This layer is generally Ina, so that it is approximately lattice matched to InP. It has a composition of Ga 6,47 A 8. Due to impurities, this layer has a density of 1-30×1014 atoms/1
It becomes n-type with doping concentrations in the range of 3. Next is the channel defining layer 63, which is usually made of p-type InP or p-type InAlAs.
Made with. p-type InG lattice matched to InP
aAs is also used. This type of layer is particularly useful when InGaAs is used for one or more adjacent layers.The thickness of the 9-layer 63 is about 1 μm.The zero order has two J
This is a FET layer.

One is a layer 64 of n-type InGaAs doped with silicon with a concentration range of 4-8X10''atoms/cs'.
The 0 layer 64, which is usually called a channel layer, is generally 0.3 to 0.5 μm thick.

Another JFET layer is p −I n Ga As
The doping concentration is different in different parts of the layer 65, typically doped with Be. The thickness of the p-InGaAs layer, including the interface with the n-InGaAs layer, is typically 0.
．． Doping concentration over most of the 5 to 0.6 µm) is about 1-5 XIO"atoms/cm"tar'J, a thin layer (typically 500 N) on top of the two layers adjacent to the p-contact.
For , the doping concentration is about 1-2:〈10'' atoms/
cxa'. An example of a method for manufacturing this structure is as follows. First, the structure shown in Figure 6 is
Orient so that the <110> direction is oriented into the [100] wafer so that the long dimension of the gate (gate width) is along this direction.

A p-diffusion step is performed to form a p-n junction of the PIN structure. S on p −' I n G a A s
An iN layer is formed. This is the active PTN region 2 in Figure 2.
patterned to act as a diffusion mask to define 1.

In the zinc diffusion process, the diffusion depth is as shown in Figure 1.
It is carried out just through the top of the aAs layer 12. After diffusion, the SiN mask is removed.

Next, p-contact metal pattern (PIN contact and various FETs)
(including the gate contact) is made of Cr-Au or other suitable p
Defined photolithographically using contact metal.

These metal contacts are made so that they can function as shadow masks when the JFET source and drain are formed.

An important part during the manufacturing process is to remove the p-layer (including some undercut of the gate electrode) without substantially affecting the n-layer or the substrate. In general, the exact process depends on the nature of the 1-2 semiconductor materials in the n-layer and 2-layer.

It is particularly important in practicing the invention to obtain the proper geometry for the p-type material so that the gate electrode functions as an effective shadow mask and the deposited source and p-InGaAs layers are 50 with hydrogen peroxide
% by volume of citric acid solution and to obtain an electrical monitoring device to measure the progress during the etching process. The current-voltage characteristics of two adjacent gate electrodes are measured and the resistance characteristics disappear, back-to-back (back-t).

-back) Etching is terminated when only diode characteristics remain. This means that p-
This shows that the p layer between adjacent gate electrodes was removed with only the n junction remaining. Additionally, removal of the p-layer results in an undercut below the gate electrode of a distance substantially equal to the original thickness of the p-layer. The protrusion of the gate electrode from the two-layer pillar ensures self-alignment of the source and drain electrodes formed later.

The source and drain n-contact metallization of the J FFT is typically formed by standard photolithographic techniques using Go Au. This is a self-aligning process since the undercut gates are protruding. This allows for very close placement of the drain and source contacts (typically 2 μm) without the risk of contact with the p-layer.
) can be carried out.

Next, cover the JFET structure and include the bridge region with n-I
Etch the nGaAs and p-InGaAs layers. Mesa isolation is performed by τ. A typical etchant is 50% by volume citric acid with hydrogen peroxide.

At this point, the substrate (N"-InP) may be thinned to 150 .mu.m.

On the opposite side of the substrate (N''-InP), an n-contact is formed except for an opening directly below the active PIN region to receive the incident light.

Many variations may be used in practicing the invention. For example, other ■−■ semiconductor materials can be used for the two JFET layers, provided they are lattice matched to the InP substrate (or materials that are lattice matched to other substrate materials). . The above-described devices shown in FIGS. 1.2 and 3 use lattice-matched InGaAs (approximate composition I n, . . . 3G aoo, 7A s ). I n Ga in either the n-layer or the p-layer
Other materials that can be used in place of As are: InGaAsP lattice matched to InP;
InP, other ternary or quaternary ■-■ compounds that can be lattice matched to InP.

Typical combinations and etching methods are as follows.

1. Both the p layer and n layer are InP. A typical etchant is a hydrochloric acid-phosphoric acid mixture (concentrated hydrochloric acid, typically 1:4 by volume) with a small amount of hydrogen peroxide sometimes added. Alternatively, a monitoring technique similar to that described above, bromine-methanol (usually in a dilute solution), can be used.

2. Two-layer InGaA lattice matched to InP
For s (or InGaAsP) and n-layer InP,
A typical etchant is citric acid, with or without the aqueous hydrogen peroxide mentioned above.

This etchant removes the p-layer and stops at n-type InP. The etch rate is about 800-1200 people/minute. Monitoring techniques similar to those described above can be used to monitor the etching process. However, once InP is reached, the etch rate decreases so much that the technique shuts off on its own, so electrical monitoring techniques are not important.

3. The P layer is InP and the n layer is InGaAs or InGaAs P lattice matched to InP.

Typical etchant is hydrochloric acid in phosphoric acid (composition above)
, which etch InP but In Ga
As or InGaAsP is not etched. Again, although not essential to the method, the etching process can be monitored using the techniques described above. The etching rate of InP using this etchant is 3000-6000 people/min.

Another PINFET structure 70 is shown in FIG.

This uses two layers as channel defining layers.

This shows another modification of the invention. To reduce the long dimension (width) of the gate electrode.

In addition, this structure employs a double-gate structure in order to reduce the stray capacitance of the drain and back gate electrodes and change the gain of the device. It should be noted that a back gate electrode is only possible if two layers are used as channel defining layers. A circuit diagram of this device is also shown. where G is the gate, G' is the back gate, N is the n-contact, and S is the source (sources S1 and 82 are normally coupled).
, D is the drain.

FIG. 8 shows a typical circuit in which the present invention will most likely be used, where RB is the bias resistor and RL is the load resistance of the circuit.

In most circuits, the resistors (RB and RL) are usually made in the form of FETs appropriately biased and placed in a semiconductor structure to obtain the desired characteristics. Generally, the load resistor is made by a JFET structure that is very similar to the JFET structure described above. This is to minimize capacitance and obtain good electrical properties even if the doping is not optimal. Such FETs often have a gate electrode connected to a source electrode. The bias resistor is also typically provided in a FET structure, but need not be in the structure described above. Furthermore, the gate length is longer than that of the above-mentioned JFET.

More complex circuits are also useful in implementing the invention. FIG. 9 shows a typical transimpedance optical receiver circuit including a cascode stage useful in implementing the present invention.

[Brief explanation of the drawing]

Figure 1 shows a J with a substrate made of p-type ■-■ semiconductor material.
Figure 2 is a side view of the FET structure, Figure 2 is a perspective view of the JFET structure in Figure 1, and Figure 3 is a side view of the JFET structure in Figure 1.
J The structure is very similar to that in Figures and 2, but the substrate structure is different.
4 is a side view of a PINFET structure having a substrate structure of the present invention; FIG. 5 is a perspective view of the PINFET structure of FIG. 4; and FIG. 6 is a side view of the PINFET structure of FIG. ．． I
Diagram showing skin structure, Figure 7 shows PINFE with double gate and back gate.
8 shows a typical circuit utilizing the JFET and PINFET structures, and FIG. 9 shows a photodetector, JFET structure.
1 shows a typical optoelectronic circuit with ET and cascode stages; FIG. [Explanation of symbols of main parts] Board...11. First epitaxial region...
・12, Second epitaxial region...15, Source electrode...13, Drain electrode...14, Gate electrode...16 Procedural Amendment April 18, 1988 Commissioner of the Japan Patent Office U Ka Michibe 1, Indication of the case Patent Application No. 27763 of 1985 2, Name of the invention Semiconductor device 3, Person making the amendment Relationship to the case Patent applicant 4, Attorney (1) Details written as attached. We will submit one copy of the letter. (2) We will submit one official drawing as shown in the attached sheet.

Claims (1)

[Scope of Claims] 1. a. a substrate; b. a first epitaxial region comprising a III-V semiconductor compound having n-type conductivity and contacting at least a portion of the substrate; c. having p-type conductivity. a second epitaxial region contacting at least a portion of the first epitaxial region and having a length; d; source and drain electrodes contacting the first epitaxial region; e. a gate electrode in contact with the second epitaxial region, wherein at least a portion of the substrate in contact with the first epitaxial region is made of a p-type III-V semiconductor compound; A semiconductor device characterized by: 2. The device of claim 1, wherein the portion of the substrate in contact with the first epitaxial region comprises p-type InP, and the III-V semiconductor compound in the first and second epitaxial regions comprises: A semiconductor device characterized by being substantially lattice matched to InP. 3. The device according to claim 2, wherein the substrate contains p-type InP. 4. The device according to claim 1, wherein the portion of the substrate in contact with the first epitaxial region is made of p-type InG lattice matched to InP.
A semiconductor device comprising aAs. 5. The device according to claim 4, wherein the substrate contains p-type InP. 6. The semiconductor device according to claim 4, wherein the substrate contains n-type InP. 7. The semiconductor device according to claim 1, wherein the gate electrode is disposed on the second epitaxial region so as to protrude from the second epitaxial region. 8. The device of claim 1, wherein the length of the gate is less than or equal to the distance between the source and drain electrodes and the length of the second epitaxial region measured along the interface with the first epitaxial region. A semiconductor device characterized in that the length of the epitaxial region is shorter than the length of the gate electrode. 9. The device according to claim 1, wherein the first and second epitaxial regions have a composition lattice matched to InP, and include InGaAs, InGaAsP, I
A semiconductor device comprising a III-V semiconductor compound selected from the group consisting of nGaAlAs, InAlAs and InP. 10. The semiconductor device according to claim 1, wherein the gate electrode is electrically connected to a gate pad, and an air bridge exists between the gate electrode and the gate pad. 11. The semiconductor device according to claim 7, wherein the gate electrode protrudes from the second epitaxial region by 0.3 to 1.0 μm. 12. a. A first region comprising an n-type III-V semiconductor compound; b. A second epitaxial region comprising an intrinsic III-V semiconductor compound and contacting at least a portion of the first region; c. III- a third epitaxial region comprising a III-V semiconductor compound and contacting at least a portion of the second epitaxial region; d, comprising a III-V semiconductor compound of n-type conductivity and contacting at least a portion of the third epitaxial region; a fifth epitaxial region having a length and comprising a III-V semiconductor compound of p-type conductivity and contacting at least a portion of the fourth epitaxial region; an epitaxial region; f a source and drain electrode in contact with the fourth epitaxial region; g a gate electrode having a length in contact with the fifth epitaxial region; a PIN portion of a PINFET structure comprising a sixth epitaxial region contacting at least a portion of the third epitaxial region but not contacting the fourth or fifth epitaxial region; i, III-V of p-type conductivity; a seventh epitaxial region comprising a semiconductor compound and contacting at least a portion of the sixth epitaxial region but not contacting the fourth or fifth epitaxial region, j forming the p-type portion of the PIN junction; A semiconductor device comprising at least one PINFET structure comprising: a p-contact comprising a conductive material contacting at least a portion of a p-type region; and means for electrically connecting the p-contact to the gate electrode. A semiconductor device, wherein the three epitaxial regions include a p-type III-V semiconductor compound. 13. The device according to claim 12, wherein the p-type region forming the p-type portion of the PIN junction is formed from below the p-contact through at least a portion of the seventh epitaxial region, and A semiconductor device extending through a portion of a sixth epitaxial region and at least contacting the third epitaxial region. 14. The device according to claim 12, wherein the p-contact electrically contacts the third epitaxial region via the sixth and seventh epitaxial regions. 15. The device according to claim 13, wherein the gate electrode is disposed on the fifth epitaxial region so as to protrude from the fourth epitaxial region. 16. The device according to claim 12, wherein the length of the fifth epitaxial region measured along the interface with the fourth epitaxial region is shorter than the length of the gate electrode. . 17. The device according to claim 16, wherein the first region is an n-type InP substrate, and the second, third, fourth, fifth, sixth and seventh epitaxial regions are InP.
A semiconductor device characterized in that it is a III-V semiconductor compound having a composition lattice matched to P. 18. The device according to claim 17, wherein the III-V semiconductor compound in the second epitaxial region is intrinsic InGaAs having a composition substantially lattice matched to InP. 19. The device according to claim 18, wherein the third epitaxial region is undoped InAlAs having a composition lattice matched to InP. 20. The semiconductor device according to claim 18, wherein the third epitaxial region is semi-insulating InP. 21. The device of claim 20, wherein the semi-insulating InP is Fe-doped InP formed by metal-organic chemical vapor deposition. 22. The device according to claim 12, wherein the fourth and sixth epitaxial regions and the fifth and seventh epitaxial regions contain the same III-V semiconductor compound. 23. The device according to claim 22, wherein the fourth and sixth epitaxial regions include n-type InP, and the fifth and seventh epitaxial regions include p-type InP.
A semiconductor device comprising type InP. 24. The device according to claim 23, wherein the fourth and sixth epitaxial regions are n-type InGaAs, and the fifth and seventh epitaxial regions are p-type InP. .