JPS62114254A - リ−ドフレ−ムの製造方法 - Google Patents

リ−ドフレ−ムの製造方法

Info

Publication number
JPS62114254A
JPS62114254A JP60254330A JP25433085A JPS62114254A JP S62114254 A JPS62114254 A JP S62114254A JP 60254330 A JP60254330 A JP 60254330A JP 25433085 A JP25433085 A JP 25433085A JP S62114254 A JPS62114254 A JP S62114254A
Authority
JP
Japan
Prior art keywords
etching
lead frame
inner leads
pressing
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60254330A
Other languages
English (en)
Japanese (ja)
Other versions
JPH036663B2 (enExample
Inventor
Katsufusa Fujita
勝房 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP60254330A priority Critical patent/JPS62114254A/ja
Priority to US06/875,134 priority patent/US4704187A/en
Publication of JPS62114254A publication Critical patent/JPS62114254A/ja
Publication of JPH036663B2 publication Critical patent/JPH036663B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP60254330A 1985-11-13 1985-11-13 リ−ドフレ−ムの製造方法 Granted JPS62114254A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP60254330A JPS62114254A (ja) 1985-11-13 1985-11-13 リ−ドフレ−ムの製造方法
US06/875,134 US4704187A (en) 1985-11-13 1986-06-17 Method of forming a lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60254330A JPS62114254A (ja) 1985-11-13 1985-11-13 リ−ドフレ−ムの製造方法

Publications (2)

Publication Number Publication Date
JPS62114254A true JPS62114254A (ja) 1987-05-26
JPH036663B2 JPH036663B2 (enExample) 1991-01-30

Family

ID=17263503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60254330A Granted JPS62114254A (ja) 1985-11-13 1985-11-13 リ−ドフレ−ムの製造方法

Country Status (2)

Country Link
US (1) US4704187A (enExample)
JP (1) JPS62114254A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148667A (ja) * 1986-12-12 1988-06-21 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
JPH02228052A (ja) * 1989-02-28 1990-09-11 Nec Kyushu Ltd 半導体装置用リードフレームの製造方法
JPH02229457A (ja) * 1989-03-02 1990-09-12 Hitachi Ltd 半導体装置の製造方法
JPH05251603A (ja) * 1992-03-05 1993-09-28 Hitachi Cable Ltd 複合リードフレーム

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849857A (en) * 1987-10-05 1989-07-18 Olin Corporation Heat dissipating interconnect tape for use in tape automated bonding
US4827376A (en) * 1987-10-05 1989-05-02 Olin Corporation Heat dissipating interconnect tape for use in tape automated bonding
US4845842A (en) * 1987-11-25 1989-07-11 National Semiconductor Corporation Process for reducing lead sweep in integrated circuit packages
US5004521A (en) * 1988-11-21 1991-04-02 Yamaha Corporation Method of making a lead frame by embossing, grinding and etching
US5063432A (en) * 1989-05-22 1991-11-05 Advanced Micro Devices, Inc. Integrated circuit lead assembly structure with first and second lead patterns spaced apart in parallel planes with a part of each lead in one lead pattern perpendicular to a part of each lead in the other lead pattern
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
US5253415A (en) * 1990-03-20 1993-10-19 Die Tech, Inc. Method of making an integrated circuit substrate lead assembly
US5053852A (en) * 1990-07-05 1991-10-01 At&T Bell Laboratories Molded hybrid IC package and lead frame therefore
JPH05102364A (ja) * 1991-10-11 1993-04-23 Rohm Co Ltd 電子部品用リードフレームの製造方法
US5541447A (en) * 1992-04-22 1996-07-30 Yamaha Corporation Lead frame
DE69323419T2 (de) * 1992-11-24 1999-06-10 Hitachi Construction Machinery Co., Ltd., Tokio/Tokyo Herstellungsverfahren für einen leiterrahmen.
DE4429002A1 (de) * 1994-08-16 1996-02-22 Siemens Nixdorf Inf Syst Anschlußstiele für elektronische Bausteine mit flächigen Anschlußfeldern
CN100557781C (zh) * 2002-08-05 2009-11-04 Nxp股份有限公司 用于制造封装半导体器件的方法和设备,和适用于该方法的金属载体
US7192809B2 (en) * 2005-02-18 2007-03-20 Texas Instruments Incorporated Low cost method to produce high volume lead frames

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119970A (en) * 1974-08-12 1976-02-17 Nippon Electric Co Riidofureemuno seizohoho

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3537175A (en) * 1966-11-09 1970-11-03 Advalloy Inc Lead frame for semiconductor devices and method for making same
JPS5946421B2 (ja) * 1977-07-01 1984-11-12 日本電気株式会社 半導体装置用リ−ドフレ−ム
JPS58173858A (ja) * 1982-04-06 1983-10-12 Tomoegawa Paper Co Ltd リ−ドフレ−ムの製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119970A (en) * 1974-08-12 1976-02-17 Nippon Electric Co Riidofureemuno seizohoho

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148667A (ja) * 1986-12-12 1988-06-21 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
JPH02228052A (ja) * 1989-02-28 1990-09-11 Nec Kyushu Ltd 半導体装置用リードフレームの製造方法
JPH02229457A (ja) * 1989-03-02 1990-09-12 Hitachi Ltd 半導体装置の製造方法
JPH05251603A (ja) * 1992-03-05 1993-09-28 Hitachi Cable Ltd 複合リードフレーム

Also Published As

Publication number Publication date
JPH036663B2 (enExample) 1991-01-30
US4704187A (en) 1987-11-03

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