JPS6182259A - 入出力アダプタ制御方法 - Google Patents

入出力アダプタ制御方法

Info

Publication number
JPS6182259A
JPS6182259A JP18598284A JP18598284A JPS6182259A JP S6182259 A JPS6182259 A JP S6182259A JP 18598284 A JP18598284 A JP 18598284A JP 18598284 A JP18598284 A JP 18598284A JP S6182259 A JPS6182259 A JP S6182259A
Authority
JP
Japan
Prior art keywords
input
output
command
cpu
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18598284A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0359464B2 (enrdf_load_stackoverflow
Inventor
Tadashi Hanada
正 花田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18598284A priority Critical patent/JPS6182259A/ja
Publication of JPS6182259A publication Critical patent/JPS6182259A/ja
Publication of JPH0359464B2 publication Critical patent/JPH0359464B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP18598284A 1984-09-05 1984-09-05 入出力アダプタ制御方法 Granted JPS6182259A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18598284A JPS6182259A (ja) 1984-09-05 1984-09-05 入出力アダプタ制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18598284A JPS6182259A (ja) 1984-09-05 1984-09-05 入出力アダプタ制御方法

Publications (2)

Publication Number Publication Date
JPS6182259A true JPS6182259A (ja) 1986-04-25
JPH0359464B2 JPH0359464B2 (enrdf_load_stackoverflow) 1991-09-10

Family

ID=16180285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18598284A Granted JPS6182259A (ja) 1984-09-05 1984-09-05 入出力アダプタ制御方法

Country Status (1)

Country Link
JP (1) JPS6182259A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01122447A (ja) * 1987-11-06 1989-05-15 Fujitsu Ltd プリンタ制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01122447A (ja) * 1987-11-06 1989-05-15 Fujitsu Ltd プリンタ制御方式

Also Published As

Publication number Publication date
JPH0359464B2 (enrdf_load_stackoverflow) 1991-09-10

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