JPS6174373A - Formation for fine electrode - Google Patents

Abstract

PURPOSE:To obtain a gate electrode; which has the thick gate film thickness, is formed in a T shape and has the large sectional area; by a method wherein a high-temperature bakelite resin layer is used as the intermediate layer and an electrical insulating layer; which is the bakelite resin layer with the temperature lower than that of the high-temperature bakelite resin layer, has the superior sputtering resistant property and is corroded with weak acid; is used as the gate mask. CONSTITUTION:A buffer layer 12, an SiO2 layer 13 and a PMMA resist 14 are formed in order on a GaAs substrate 11, and after that, a gate opening part is formed on the resist 14. Then, after an opening part 15 is transferred on the film 13, an overetching is performed on the film 12 to form an opening part 16, and furthermore, an opening part 17 to reach the substrate 11 is formed. Then, a tungsten film 18 is coated and after the film 13 is removed, a metal film 19 is coated thicker than the layer 12. Then, after the metal film 19 is etched up to reach the layer 12 using a resist pattern 20 as a mask, the layer 12 is removed and the purposive gate electrode is obtained on the substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming fine electrodes, particularly for reducing gate resistance in high frequency transistors.

[Prior art]

Recently, high-frequency transistors have operating frequencies in the X band (8 to 1
2GHz) to (18-26GHz), K
Research and development is actively being conducted with the aim of improving performance in the A-band (26 to 40 GHz) and higher frequency ranges. In order to achieve high performance (Il-), it is necessary to reduce the parasitic resistance and to reduce the number of gate electrodes, that is, to realize a sub-micron gate. Conventionally, the method of forming such a sub-micron gate is to The inventors made a report at the 1985 National Conference of the Society of Electronics and Communications Engineers, but this is the second
As shown in Figure (a), first, M32 It, which is a gate metal, is deposited on a semi-duplex substrate 31, and a photoresist pattern is formed by ordinary photolithography. As shown in FIG. 2(b), the M32' is overetched to realize the sail 5 micron gate 34 shown in FIG. 2(c). Another conventional method of forming spacers 3 on a semiconductor substrate 41 was reported by K. Ohata et al. in IEDM in 1979, as shown in FIG. 3(a).
After forming the resist pattern 42 formed on the resist pattern 42 with a mask and over-etching the spacer 5iOz 42t, and subsequently digging into the substrate 41, a gate gold 6M 44 is deposited as shown in FIG. Next, a 0.5 micron gate 45 is realized by a lift-off method in which the resist pattern 43 is removed as shown in FIG. 4(c).

[Problem that the invention seeks to solve]

However, in the conventional method of forming a gate electrode with a submicron length or less using such side etching method and lift-off method, the cross-sectional shape of the gate electrode obtained is is deposited, the gate becomes trapezoidal or triangular instead of rectangular, resulting in an increase in gate resistance.

In particular, if the gate length is further shortened to 0.2 microns in order to further improve transistor characteristics, the gate height will be 2.5 times as large to obtain the same gate resistance. ,According to the above statement, in reality, Fig. 4(a)
, (b) As shown in the shape of the middle gates 51 and 52, the gate height cannot be increased, resulting in a further increase in gate resistance, which is a major drawback in terms of improving the performance of the transistor.

The object of the present invention is to provide a method for forming fine electrodes which eliminates such conventional drawbacks and reduces resistance.

[Level for solving problems]

The present invention includes a process of etching an opening in an intermediate layer provided on a semiconductor substrate to a size wider than a first mask patterned to minute dimensions, and an etching process until the opening of the intermediate layer provided on a semiconductor substrate reaches the same size as that of the first mask. etching away the metal layer; depositing a first metal layer over the exposed substrate; and after removing the first mask, depositing a second metal layer thicker than the intermediate layer at the gate opening; The process of depositing the second gold+? This method of forming a fine electrode is characterized by performing a step of etching and removing all four second layers and an intermediate layer using the second pattern that cuts the i-layer as a mask.

[Effect]

The present invention has solved the problems of the prior art by adopting the above-described configuration. That is, for the intermediate layer that will become a spacer, the opening width on the substrate is the gate dimension, the gate length is determined across the first thin Schottky area, the mask side has a wide opening in the overhang structure, and after the mask is removed, the second The conventional problem of not being able to obtain a gate height greater than 9 degrees when the opening is covered by depositing the metal layer on the side surface of the mask is solved, and the gate resistance is reduced. A high and short gate length can be obtained. In addition, by using a highly baked resin layer as the intermediate layer, the above-mentioned shape can be obtained only by dry etching with excellent controllability, and it can also be easily removed by, for example, plasma etching, making it suitable as a lift-off spacer. be. On the other hand, a small one using a spin-coated and baked electrically insulating layer as the first mask,
1. It can be formed by baking at a lower temperature than the baking temperature of the resin layer used for the intermediate layer, and its spatter resistance is comparable to that of a diluted film deposited by the G method. Moreover, it can be easily removed using a weak chemical etching solution without damaging the first six gold layers, which is extremely effective for realizing the present invention.

〔Example〕

Hereinafter, as a specific example of the present invention, a drawing is shown in which tungsten is used as the first four gold layers and gold is used as the second metal layer on a gallium arsenide (hereinafter referred to as GaAs) substrate. This will be explained in detail with reference to the following. Figure 1(a)~
(g) is a top view showing an example of the present invention in the order of steps. After that, the buffer layer 12 is formed as an intermediate layer by baking at 300° C. for 1 hour in a nitrogen atmosphere.Next, Si5.9
(%) OCD film (trade name manufactured by Tokyo Ohka Co., Ltd.) was applied and baked in nitrogen at 250°C for 30 minutes to form a 5-ins film 13, and then PMMA (Poly meth
yl meth-acrylate) resist 14 was applied and baked in monoxide at 170°C for 20 minutes.
A gate opening 1 of 0.3 μm is formed in the PMMA resist 14.
5 is formed using electron beam exposure. Subsequently, using the resist pattern as a mask, the opening 15 is transferred onto the SiO2 film 13 by parallel plate reactive ion etching using CF4 gas.

Next, the buffer layer 12 is over-etched by cylindrical plasma etching using 1Z02 gas to form an opening 16 wider than the mask (FIG. 1(b)).
), Subsequently, the buffer layer 12 is etched with GaAs by parallel plate type reactive ion etching using O2 gas.
G plate 11 is etched until it is fully etched to form an opening 17 having the same dimensions as the mask (FIG. 1(C)).

At this time, the uppermost layer P1A14 is removed by etching. Subsequently, tungsten 18, which is the first gold layer, is deposited by sputter deposition (FIG. 1(d)).

Next, after removing the 5-inch film 13 with hydrofluoric acid + water (1:LO), gold 19, which is the second gold 4, is deposited thicker than the buffer layer 12 at the gate opening by sputter deposition (first gold 4).
(e)), then wider than the gate opening 16,
Using a resist pattern 20 formed by ordinary photolithography to cover the gold 19 as a mask, the gold 19 is etched by ion milling until it reaches the buffer layer L2 (FIG. 1(f)), and then 02 gas is etched. The gate electrode 21 is obtained on the GaAs substrate 11 by etching away the buffer layer by cylindrical plasma etching using cylindrical plasma etching (FIG. 1(g)). At this time, the resist pattern 20 is also etched away.

〔Effect of the invention〕

The gate electrode obtained by the present invention (shown in FIG. 1(g)) and the gate electrode prepared by the conventional formation method (see FIG.
When compared with those shown in Figures (a) and (b), the present invention has a high-temperature baked resin layer as an intermediate layer and is spin-coated as a gate mask, has better spatter resistance than the resin layer when baked at a lower temperature, and Since we used an electrical insulating layer that is etched away by the process, the gate gold 4 does not adhere to the side surface of the mask, resulting in a triangular cross-sectional shape or a limit on the thickness. It is possible to form a T-shaped gate electrode with a large cross-sectional area.
The effect of using a resin layer as an intermediate layer is that unlike an oxide film spacer, which may attack the metal layer using a hydrofluoric acid-based chemical etching solution, it can be easily etched and gate lift-off with 02 plasma. Here are some things you can do.

The gate electrode thus obtained has a reduced gate resistance compared to conventional ones, and can be expected to improve microwave characteristics when applied to, for example, ultra-high frequency field effect transistors. In the embodiments of the present invention, GaAa is used as the semiconductor substrate, tungsten is used as the first gold 6 layer, and tungsten is used as the second gold layer.
Although we have shown examples using gold as the metal of A silicide film, a nitride film, and a second gold blocking layer may be titanium or a two-layer gold layer of platinum and gold in which a high conductivity metal for reducing gate resistance and a stopper metal for a gold reaction are laminated. The bait material does not limit the invention in any way.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) are cross-sectional views showing the gate electrode forming method of the present invention in the order of steps; FIGS. 2(a) to (C) are cross-sectional views showing the conventional gate electrode forming method in process order; Figure 3(a)
~(C) are cross-sectional views showing another conventional gate electrode forming method in the order of steps, and FIGS. 4(a) and 4(b) are cross-sectional views showing the conventional gate electrode
FIG. 3 is a cross-sectional view of a gate electrode obtained by the electrode forming method. 11- GaAs substrate, 12...- buffer layer, 13-
Sin, 14...PMMA resist, 15...
Gate opening, 16...first buffer layer opening, 1
7... Second buffer layer opening, 18... Tungsten, 19... Gold, 20.43... Resist pattern, 21, 34, 45.51.52-... Gate electrode,
31, 41... semiconductor substrate, 32, 44...M
, 33... Photoresist, 42... Spacer Si
O□ 1q large for patent NEC Corporation Fig. 1 (b) Ka 1's θfa M opening (C) ) Also forgot the buffer layer gate of 2 Fig. 1 (e) (f) Fig. 1 Figure 2 (Q) 33 Futoshi cyst Figure 2 (b) Infant Figure 2 Figure 3 Figure 3

Claims (2)

[Claims] (1) A step of etching an intermediate layer provided on a semiconductor substrate to a size wider than a first mask patterned to minute dimensions, and etching the intermediate layer until it reaches the semiconductor substrate with the same dimensions as the first mask. etching away the layer; and depositing a first metal layer on the exposed substrate;
After removing the first mask, depositing a second metal layer thicker than the intermediate layer at the electrode opening, and applying a second metal layer using a second pattern as a mask to cover the second metal layer wider than the opening. 2. A method for forming a fine electrode, comprising performing the step of etching away the metal layer and the intermediate layer. (2) A resin layer baked at a high temperature as the intermediate layer is used as the first layer.
2. The method of forming a fine electrode according to claim 1, wherein an electrically insulating layer that has been spin-coated and baked is used as a mask.