KR100488475B1 - Manufacturing method of ultra high frequency semiconductor device - Google Patents
Manufacturing method of ultra high frequency semiconductor device Download PDFInfo
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- KR100488475B1 KR100488475B1 KR1019960075440A KR19960075440A KR100488475B1 KR 100488475 B1 KR100488475 B1 KR 100488475B1 KR 1019960075440 A KR1019960075440 A KR 1019960075440A KR 19960075440 A KR19960075440 A KR 19960075440A KR 100488475 B1 KR100488475 B1 KR 100488475B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 239000010410 layer Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
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- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
본 발명은 lμm 이상의 선폭을 갖는 마스크를 이용하여 0.2μm 이하의 게이트 길이를 갖는 소자를 제작하여 생산성을 향상시킬 수 있는 초고주파 반도체 소자의 제조방법을 제공하는 것으로, 반절연성 화합물 반도체 기판 상의 게이트 예정 영역에 소정 길이의 선폭을 갖는 절연막 패턴을 형성하는 단계; 절연막 패턴 양 측벽과 접하도록 기판 상에 감광막 패턴을 형성하는 단계; 감광막 패턴 사이의 절연막을 식각하여 게이트 예정 영역을 노출시켜 리세스를 형성하는 단계; 및, 리세스에 게이트 물질을 형성하고 리프트 오프하여 게이트 패턴을 형성하는 단계를 포함하고, 절연막 패턴을 형성하는 단계는 기판 상에 소정의 형태로 패터닝된 감광막 패턴을 형성하는 단계; 감광막 패턴이 형성된 기판 전면에 선폭의 두께로 절연막을 형성하는 단계; 감광막 패턴 측벽에만 절연막이 남도록 절연막을 식각하는 단계; 및, 감광막 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.The present invention provides a method for manufacturing an ultra-high frequency semiconductor device capable of improving productivity by fabricating an element having a gate length of 0.2 μm or less using a mask having a line width of 1 μm or more, and a gate predetermined region on a semi-insulating compound semiconductor substrate. Forming an insulating film pattern having a line width of a predetermined length on the substrate; Forming a photoresist pattern on the substrate to be in contact with both sidewalls of the insulation pattern; Etching the insulating film between the photoresist patterns to expose a gate predetermined region to form a recess; And forming a gate material by forming a gate material in the recess and lifting off to form a gate pattern, wherein forming the insulating film pattern comprises: forming a patterned photoresist pattern on a substrate in a predetermined form; Forming an insulating film having a thickness of a line width on the entire surface of the substrate on which the photoresist pattern is formed; Etching the insulating film so that the insulating film remains only on the photoresist pattern sidewalls; And, it characterized in that it comprises a step of removing the photosensitive film pattern.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 1μm 이상의 패턴을 이용하여 0.25μm 이하의 길이를 갖는 게이트를 형성할 수 있는 초고조파 반도체 소자의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of an ultra-high frequency semiconductor device capable of forming a gate having a length of 0.25 μm or less using a pattern of 1 μm or more.
통신기술이 발달함에 따라 1GHz부터 100GHz 주파수 대역의 고주파 영역은 현재 통신 시스템에 있어서 점점 더 그 중요성이 커지고 있다.With the development of communication technology, the high frequency range of 1 GHz to 100 GHz frequency band is becoming more and more important in current communication systems.
일반적인 초고주파용 반도체 소자로서 GaAs를 기초로 하는 금속-반도체 FET(Metal-Silicon Field Effect Transistor; 이하, MESFET)이 사용되는데, 이러한 GaAs가 Si 대신에 고주파 소자로서 적합하다. 즉, GaAs의 전자 이동도가 Si 보다 높고 천이시간이 짧아 고주파 능력이 크다. 또한, GaAs는 높은 온도에서 잘 견딜 수 있을 뿐만 아니라, 에너지 갭이 크기 때문에 상온에서 동작하는 저전력 GaAs 증 폭소자는 열생성량이 매우 작고 누설전류도 낮으므로 잡음에 강한 특성을 갖는다.As a general ultra-high frequency semiconductor device, a metal-semiconductor field effect transistor (FET) based on GaAs is used. Such GaAs is suitable as a high-frequency device instead of Si. That is, GaAs has higher electron mobility than Si and its transition time is short, so that the high frequency capability is high. In addition, GaAs is not only able to withstand high temperatures but also has a large energy gap, and thus, low-power GaAs amplifiers operating at room temperature have a low heat generation and low leakage current.
또한, 상기 MESFET을 개선한 변조 도핑된 FET(Modulation Doped FET; MODFET)이라고도 하는 이종 접합을 이용한 HEMT(High Electron Mobility Transistor)는 도핑되지 않은 GaAs를 채널영역으로 사용하여 불순물 산란을 없애고 이동도를 증가시킴으로써, 상기 MESFET과 더불어 초고주파 집적회로 소자의 제조에 사용된다.In addition, HEMT (High Electron Mobility Transistor) using heterojunction, also called Modulation Doped FET (MODFET), which improves the MESFET, eliminates impurity scattering and increases mobility by using undoped GaAs as a channel region. In addition, it is used in the manufacture of ultra-high frequency integrated circuit elements together with the MESFET.
한편, 상기한 GaAs MESFET과 HEMT는 고주파 특성을 개선하기 위하여 FET의 게이트 길이를 감소시키는 것이 중요한 요소로 제시되고 있다.On the other hand, the GaAs MESFET and HEMT has been proposed as an important factor to reduce the gate length of the FET to improve the high frequency characteristics.
그러나 일반적인 1μm 이상의 마스크 패턴을 형성하는 I-라인 포토리소그라피를 이용하여 0.25μm 이하의 게이트 패턴을 형성하는 것이 매우 어렵기 때문에 0.25μm 이하의 게이트 패턴을 형성하기 위하여 전자 빔 리소그라피 방법을 이용함에 따라 공정 비용이 증가할 뿐만 아니라 공정시간이 길기 때문에 생산성이 저하되는 문제가 있었다.However, since it is very difficult to form a gate pattern of 0.25 μm or less using I-line photolithography that forms a mask pattern of 1 μm or more in general, an electron beam lithography method is used to form a gate pattern of 0.25 μm or less. In addition to the increase in cost, the process time is long, there is a problem that the productivity is lowered.
이에, 본 발명은 상기한 문제점을 감안하여 창출된 것으로서, 1μm 이상의 선폭을 갖는 마스크를 이용하여 0.25μm 이하의 게이트 길이를 갖는 소자를 제작하여 생산성을 향상시킬 수 있는 초고주파 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in view of the above problems, and provides a method for manufacturing an ultra-high frequency semiconductor device capable of improving productivity by manufacturing a device having a gate length of 0.25 μm or less using a mask having a line width of 1 μm or more. Has its purpose.
상기 목적을 달성하기 위한 본 발명에 따른 초고주파 반도체 소자의 제조방법은 반절연성 화합물 반도체 기판 상에 소정의 형태로 패터닝된 감광막 패턴을 형성하는 단계: 상기 감광막 패턴이 형성된 기판 전면에 소정의 선폭의 두께로 절연막을 형성하는 단계: 상기 감광막 패턴 측벽에만 상기 절연막이 남도록 상기 절연막을 식각하는 단계; 상기 감광막 패턴을 제거하는 단계; 상기 남은 절연막의 양 측벽과 접하도록 상기 기판 상에 감광막 패턴을 형성하는 단계; 상기 감광막 패턴 사이의 절연막을 식각하여 리세스를 형성하는 단계; 상긴 리세스에 게이트 물질을 증착하고 리프트 오프하여 게이트를 형성하는 단계; 상기 게이트 상에 금속층을 적층하여 T형 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing an ultra-high frequency semiconductor device, the method including: forming a patterned photoresist pattern on a semi-insulating compound semiconductor substrate in a predetermined shape: a thickness of a predetermined line width on the entire surface of the substrate on which the photoresist pattern is formed Forming an insulating film in a furnace: etching the insulating film so that the insulating film remains only on the sidewalls of the photoresist pattern; Removing the photoresist pattern; Forming a photoresist pattern on the substrate to be in contact with both sidewalls of the remaining insulating film; Etching the insulating film between the photosensitive film patterns to form a recess; Depositing and lifting off the gate material in the longer recess to form a gate; Stacking a metal layer on the gate to form a T-type gate.
상기와 같은 구성으로 된 본 발명에 의하면, 절연막 패턴을 이용한 리세스 형성을 통하여 게이트의 길이를 감소시킬 수 있다.According to the present invention having the above configuration, the length of the gate can be reduced by forming the recess using the insulating film pattern.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1A 내지 도 1F는 본 발명의 실시예에 따른 초고주파 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a microwave semiconductor device according to an embodiment of the present invention.
먼저, 도 1A에 도시된 바와 같이, p-HEMT 형성을 위하여 GaAs버퍼층, 절연성 InGaAs 등의 활성층, 절연성 AIGaAs 등의 스페이서층, n형 AIGaAs 등이 캐리어 공급층 및 n+형 GaAs 등의 저항성 접촉층 등이 형성되거나, MESFET 형성을 위하여 절연성 GaAs 버퍼층, n형 GaAs 활성층 및 n+GaAs 저항성 접촉층 등이 형성된 반절연성 GaAs 기판(1) 상부에 0.25μm 이하의 T-게이트를 형성하기 위하여 포토리소그라피로 제1감광막 패턴(2)을 형성한다. 그리고, 제1감광막 패턴(2) 및 기판(1) 상에 리세스 형성을 위한 질화막(SiN) 또는 산화막(SiO2) 등의 절연막(3)을 형성한다. 이때, 절연막(3)의 두께로 이후 형성되는 게이트의 길이를 조절할 수 있다.First, as illustrated in FIG. 1A, a GaAs buffer layer, an active layer such as insulating InGaAs, a spacer layer such as insulating AIGaAs, an n-type AIGaAs, and the like are provided as a carrier supply layer and an ohmic contact layer such as n + type GaAs to form p-HEMT. Photolithography to form a T-gate of 0.25 μm or less on top of the semi-insulating GaAs substrate 1 having the insulating GaAs buffer layer, the n-type GaAs active layer, the n + GaAs resistive contact layer, or the like, for forming the MESFET. 1 Photosensitive film pattern 2 is formed. Then, an insulating film 3 such as a nitride film (SiN) or an oxide film (SiO 2) for forming a recess is formed on the first photoresist film pattern 2 and the substrate 1. In this case, the length of the gate formed after the thickness of the insulating film 3 can be adjusted.
도 1B에 도시된 바와 같이, 절연막(3)을 반응성 이온 식각(Reactive Ion Etching) 방식으로 이방성 식각하여 제1감광막 패턴(2) 측벽에만 절연막(3)이 남도록 패터닝하고, 공지된 방법으로 제1감광막 패턴(2)을 제거하여 0.25μm 이하의 게이트 예정 영역을 정의한다.As shown in FIG. 1B, the insulating film 3 is anisotropically etched by a reactive ion etching method, so that the insulating film 3 remains only on the sidewalls of the first photoresist pattern 2, and the first method is known. The photosensitive film pattern 2 is removed to define a gate predetermined area of 0.25 μm or less.
도 1C에 도시된 바와 같이, 패터닝된 절연막(3) 양 측벽과 접하도록 기판(1)상에 제2감광막 패턴(4)을 형성한다.As shown in FIG. 1C, a second photoresist layer pattern 4 is formed on the substrate 1 so as to contact both sidewalls of the patterned insulation layer 3.
도 1D에 도시된 바와 같이, 제2감광막 패턴(4)을 식각 마스크로 하여 습식식각으로 절연막(3)을 제거하여 리세스를 형성함으로써, 상기 게이트 예정 영역의 기판(1)을 노출시킨다.As shown in FIG. 1D, the substrate 1 in the gate predetermined region is exposed by removing the insulating film 3 by wet etching using the second photoresist pattern 4 as an etching mask to form a recess.
도 1E에 도시된 바와 같이, 상기 리세스 및 제2감광막 패턴(4) 상에 게이트 물질(5)을 증착하고, 리프트 오프(lift off)하여 게이트(5)를 형성한다. 이와 같이 리세스에 게이트 물질을 증착하면 형성된 게이트(5)의 표면이 매끄럽게 되므로 게이트(5)의 접촉저항을 감소시키기 위한 후속공정인 게이트(5) 상의 금속층(10) 적층을 용이하게 할 수 있다.As shown in FIG. 1E, the gate material 5 is deposited on the recess and the second photoresist pattern 4, and lifted off to form the gate 5. By depositing the gate material in the recess as described above, the surface of the formed gate 5 is smoothed, thereby facilitating the stacking of the metal layer 10 on the gate 5, which is a subsequent process for reducing the contact resistance of the gate 5. .
이어서, 후속 공정을 진행하여, 도 1F에 도시된 바와 같이, 게이트(5)에 상부 금속층(10)을 적층하여 T형 게이트를 완성함과 더불어, 제1층간절연막(6) 및 제2층간절연막(8)에 의해 게이트(5)와 서로 절연되고 기판(1)과 콘택하는 소오스(7a,9a) 및 드레인 전극(7b,9b)을 형성한다.Subsequently, a subsequent process is performed, as shown in FIG. 1F, the upper metal layer 10 is stacked on the gate 5 to complete the T-type gate, and the first interlayer insulating film 6 and the second interlayer insulating film are completed. (8) forms source (7a, 9a) and drain electrodes (7b, 9b) insulated from the gate (5) and in contact with the substrate (1).
한편, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위 내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
상기 실시예에 의하면, 절연막의 두께를 용이하게 조절하여 게이트의 길이를 제어할 수 있기 때문에 게이트의 길이를 감소시켜 고주파 특성을 향상시킬 수 있는 효과가 있다.According to the above embodiment, since the length of the gate can be controlled by easily adjusting the thickness of the insulating film, there is an effect of reducing the length of the gate to improve the high frequency characteristics.
또한, 1μm 이상의 선폭을 갖는 마스크를 이용하여도 0.25μm 이하의 게이트 길이를 갖는 소자의 제작이 가능하므로 생산성을 향상시킬 수 있고 원가 절감의 효과를 얻을 수 있다.In addition, since a device having a gate width of 0.25 μm or less can be manufactured even with a mask having a line width of 1 μm or more, productivity can be improved and cost reduction can be obtained.
또한, 리세스를 형성하여 리세스에 게이트 물질을 증착함으로써 접촉저항 감소를 위한 T형 게이트 제작을 용이하게 할 수 있는 효과가 있다.In addition, by forming a recess and depositing a gate material in the recess, the T-type gate for reducing contact resistance may be easily manufactured.
도 1A 내지 도 1F는 본 발명의 실시예에 따른 초고주파 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a microwave semiconductor device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 반절연성 GaAs 기판 2, 4 : 제1 및 제2감광막 패턴DESCRIPTION OF SYMBOLS 1 Semi-insulating GaAs board | substrate 2 and 4: 1st and 2nd photosensitive film pattern
3 : 절연막 5 : 게이트3: insulating film 5: gate
6, 8 : 제1 및 제 2층간절연막 7a, 9a : 소오스 전극6, 8: first and second interlayer insulating films 7a, 9a: source electrode
7b, 9b : 드레인 전극 10 : 금속층7b, 9b: drain electrode 10: metal layer
Claims (4)
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| KR1019960075440A KR100488475B1 (en) | 1996-12-28 | 1996-12-28 | Manufacturing method of ultra high frequency semiconductor device |
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| KR1019960075440A KR100488475B1 (en) | 1996-12-28 | 1996-12-28 | Manufacturing method of ultra high frequency semiconductor device |
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| KR19980056176A KR19980056176A (en) | 1998-09-25 |
| KR100488475B1 true KR100488475B1 (en) | 2005-08-04 |
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