KR100681842B1 - T-type gate electrode and method for fabricating the same - Google Patents

Abstract

A T-type gate electrode and a method for forming the same are provided to control easily a fine CD(Critical Dimension) of the gate electrode itself without the generation of short by using a dummy gate layer. An electronic beam resist pattern is formed on a semiconductor substrate with a buffer layer, a barrier layer, a second etch stop layer, a dummy gate layer, a first etch stop layer, a cap layer and a passivation layer(S101). The passivation layer is selectively removed by using first etching process(S102). The cap layer and the first etch stop layer are selectively removed by using second etching process(S103). A gate mask is formed in the cap layer and the first etch stop layer(S104). A recess etching process is performed on the dummy gate layer(S105). A metal film for a gate electrode is deposited on the gate mask(S106).

Description

T-type gate electrode and method for fabricating the same

1A to 1E are cross-sectional views of a semiconductor substrate according to a prior art process;

2 is a process flow chart according to the invention, and

3A-3H are cross-sectional views of a semiconductor substrate in accordance with the process of the present invention.

Recently, the demand for the processing and transmission of a large amount of information such as an image signal has exploded, and as the information progresses rapidly, the necessity of ultra-high speed information processing has gradually increased. In addition, due to the rapid development of wireless communication, communication systems that operate at high speed in a wide frequency band are required.

Accordingly, in order to develop next-generation electronic devices that are essential for the construction of ultra-high-speed information systems, advanced countries such as the US, Japan, and Germany are trying to increase the operation speed by reducing the size of existing devices. Research, research on quantum functional devices to achieve super high speed by using quantum effect generated in nano-structure, and super fast speed of Ⅲ-V ultra high speed devices using Ⅲ-V semiconductor material with excellent transmission characteristics There is a lot of research into the implementation.

The fastest speeding field is the optical communication system. The current trend is to implement a time division system that operates at the maximum speed that can be implemented in order to benefit from the practicality, reliability, and price of the system, and it is predicted that a wavelength division system will be used in a higher speed system. Currently, 10Gb / s-class optical communication systems are commercially available and are gradually being expanded to systems with transmission speeds of 40Gb / s, 80Gb / s and higher. In order to realize the ultra-fast time division optical communication system, it is necessary to develop high-speed digital circuits such as MUX / DEMUX and decision circuits, high-frequency analog circuits such as an optical modulator driver and a pre-amplifier. Development is mandatory.

Among them, integrated circuits operating at frequencies above the X-band, including low-noise receivers, power amplifiers, and monolithic microwave integrated circuits (MMICs) in the millimeter wave band. High-speed devices such as high electron mobility transistors (HEMT), which are mainly applied in (IC), are the most advantageous advantages of constructing high performance ultra-large scale integrated circuits operating at low temperature among the current high speed electronic devices. have. The HEMT should have a short gate length for high modulation operation and a wide cross-sectional area to improve the noise characteristics by reducing the gate resistance. Therefore, in order to satisfy the above requirement, a gate electrode having a T-shaped cross section is used.

In the case of manufacturing the fine T-type gate electrode, an opening for determining the size of the gate length in the lower layer of the laminated resist using a laminated resist and an opening for determining the size of the over gate portion in the upper layer of the laminated resist. Forming each of them is conventionally performed. In this case, in order to obtain a laminated resist in which openings of different sizes are formed in separate layers from each other, a plurality of resist materials having different sensitivity are required. In addition, when the lift-off method is used for the production of the T-type gate electrode, it is necessary to provide a resist for an intermediate layer in the laminated resist that ensures easy lift-off. Since many electron beam resists have different sensitivity, since the necessity of the gate length of the lower end part in the said T-type gate electrode being 0.1 micrometer or less, the T-type gate electrode is made using the electron beam resist and expensive electron beam lithography. Manufacturing has been generally done. However, in this case, the process cost is very expensive, a large amount of T-type electrode cannot be manufactured with a small amount of throughput, and there is a problem that a T-type electrode having a lower process yield and a gate length of several tens of nanometers cannot be formed. have.

Referring to FIGS. 1A to 1E, a T-type gate forming process of a conventional HEMT device will be described in detail as follows. FIGS. 1A to 1E illustrate only a region where a T-type gate electrode is formed.

The first electron beam resist layer 50 and the PMGI are formed on the semiconductor substrate 10 on the epitaxial layer formed of the etch stop layer 20 and the cap layer 30 and the passivation layer formed of the Si ₃ N ₄ layer 40. The layer 60 and the second electron beam resist layer 70 are formed. FIG. 1A illustrates a pattern of a T-gate electrode. After forming a second electron beam resist pattern using an E-beam lithography process, the PMGI layer is wet-etched as shown in FIG. 1A. Etch it. The first electron beam resist layer exposed through the etching of the PMGI layer is formed using an electron beam lithography process.

FIG. 1B illustrates a step of etching the Si ₃ N ₄ layer by using the formed first electron beam resist pattern. When the portion of the cap layer 30 is etched by the portion of the Si ₃ N ₄ layer exposed through the etching process, a portion of the cap layer is etched as shown in FIG. 1C, and the T-type gate electrode of the T-type gate electrode is formed in the empty space 100 of the cap layer. The lower end may be formed.

Subsequently, as illustrated in FIG. 1D, when the metal material is deposited 110 on the area where the empty space of the cap layer is formed, and the first and second electron beam resist patterns and the PMGI layer are removed, the T-type gate electrode 115 as shown in FIG. 1E is removed. Can be implemented. However, in the process of depositing the lower gate portion of the metal material in the patterned empty region, a pattern must be formed in the empty space of the cap layer through the open region of the Si ₃ N ₄ layer, which is a passivation layer, but Si ₃ N ₄ If the gap of the open area of the layer is tens of nanoscales, and the aspect ratio is large, the problem is that the gate electrode is first filled with a metal material and eventually the gate electrode is broken, which acts as a main cause of disconnection. There are various process problems such as lowering the temperature.

Further, even when the gap of the open region of the Si ₃ N ₄ layer is first filled with the metal material, the metal layer is deposited on the open region 100 of the cap layer to form the bottom portion 120 of the T-type gate. As shown in FIG. 1f, as the lower portion 120 of the T-type gate formed on the etch stop layer 20 is closer to the bottom surface, the deposited metal is formed into a shape 125. Therefore, there is a problem in the process that it is difficult to implement the desired fine line width, and in addition, the shape 125 with a lot of metal layers as described above becomes the lower width (L _Go ) of the T-type gate electrode to form the T-type gate of the HEMT element. When applied to, there is a problem that the modulation operation of the HEMT device is lowered, causing deterioration of the characteristics of the device.

Accordingly, the present invention additionally forms a dummy gate layer in a conventional epitaxial layer formed on a semiconductor substrate to solve the above problems, and in the formation process of the T-type gate electrode, the dummy gate existing under the gate mask. An object of the present invention is to provide a T-type gate electrode having a gate bottom width of several tens of nanometers and a forming method by recessing the layer to form a lower portion of the T-type gate electrode.

In addition, an object of the present invention is to provide a method for forming a T-type gate electrode to facilitate the adjustment of the fine line width of the T-type gate electrode.

T-type gate electrode forming method according to the present invention for achieving the above object is a buffer layer, a channel layer, a barrier layer, a second etching stop layer, a dummy gate layer, a first etching stop layer, a cap layer and a passivation layer (passivation layer) Forming an E-beam resist pattern on the formed semiconductor substrate (S1), etching a passivation layer formed on the lower portion of the electron beam resist pattern (S2), and etching the region of the passivation layer Etching the cap layer and the first etch stop layer formed at a lower portion (S3), forming a gate mask inside the etched cap layer and the first etch stop layer (S4), and at the bottom of the gate mask. Recessing the dummy gate layer formed on the second etch stop layer (S5) and depositing a metal layer for forming a gate electrode on the gate mask The T-type gate electrode including the system S6 and manufactured by the T-type gate electrode forming method according to the present invention includes a lower region having the smallest width among the T-type gate electrodes formed on the semiconductor substrate, and an upper portion of the lower region. A gate mask for forming the lower region, a single layer or a multi-layer diffusion barrier metal layer for preventing diffusion of the gate mask and the gate electrode head, and a cross-sectional area of the T-type gate electrode; This is made up of the widest gate heads.

Preferably, the passivation layer is Si ₃ N ₄ , and after the step (S6), further comprises the step of heat treatment to metallize the recess-etched dummy gate layer.

Preferably, the step (S1), the step of sequentially forming a first electron beam resist, a PMGI layer, a second electron beam resist on the cap layer, forming the second electron beam resist pattern, the PMGI layer Side etching and forming the first electron beam resist pattern.

Preferably, the first electron beam resist and the second electron beam resist are ZEPs as positive electron beam resists, and the PMGI layer is wet etched using an etching solution of tetramethylammonium hydroxide aqueous solution.

Preferably, the etching of the passivation layer is dry etching using a mixed gas of SF ₆ and Ar, and etching the part of the cap layer and the first etching stop layer is citric acid (C ₆ H ₈ O ₇ ) Wet etching using a solution of hydrogen peroxide (H ₂ O ₂ ) 7: 1 and a solution of hydrochloric acid series (HCl: H ₃ PO ₄ : H ₂ O = 1: 1: 1).

Preferably, the step (S5) uses a solution in which phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O) in a ratio of 1: 1: 400.

Preferably, the step S6 includes depositing a diffusion barrier layer in a single layer or multiple layers on top of the gate mask and depositing a gate head layer on the diffusion barrier layer.

Preferably, as for the semiconductor substrate to form a HEMT device, and one of a GaAs-based, InP-based substrate, and the lower region is non-doped In _{0 .52} AlAs, said gate mask Ni / Pt, the diffusion The protective metal layer is Ti / Pt and the gate head is Au.

Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

Hereinafter, a method of forming a photosensitive film pattern according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a process flow chart of the present invention.

According to the present invention, after forming an electron beam resist pattern on a semiconductor substrate having an epitaxial layer including a dummy gate layer and a passivation layer (S101), and etching the passivation layer which is a lower layer of the electron beam resist pattern (S102), The cap layer and the first etch stop layer are sequentially etched (S103). Thereafter, a gate mask is formed in the etched cap layer and the first etch stop layer (S104) to recess-etch the dummy gate layer (S105). Finally, the gate electrode to be formed is deposited (S106) and heat treated (S107) to form a T-type gate electrode.

A method of forming a T-type gate electrode according to an exemplary embodiment of the present invention may include forming a T-type gate pattern and etching a portion of a cap layer on a semiconductor substrate having an epitaxial layer and a passivation layer including a dummy gate layer, and etching. Forming a gate mask in the cap layer, recessing the dummy gate layer using the gate mask to determine the length of the lower portion of the T-type gate, and forming a metal layer for forming the gate electrode It includes the process to make it, and further includes the process selected suitably as needed.

A semiconductor substrate having an epitaxial layer and a passivation layer including a dummy gate layer

The T-type gate electrode forming method according to the present invention first uses a semiconductor substrate having an epitaxial layer including a dummy gate layer and a passivation layer.

Referring to FIG. 3A, a semiconductor substrate may use a GaAS or InP-based material to manufacture a HEMT, and may include a single wafer of semiconductor material. However, in the present invention, in the preferred embodiment for manufacturing InP HEMT device, an InP series substrate is applied.

The epitaxial layer 245 formed on the semiconductor substrate is formed of a buffer layer / channel layer / barrier layer / second etch stop layer / dummy gate layer / first etch stop layer / cap layer.

First buffer layer 180 and the barrier layer formed on the semiconductor substrate (barrier, 200) is a channel formed of a _{0 .52} In AlAs (channel, 190) layer is formed by InGaAs. The second etch stop layer 210 is sequentially formed on the barrier layer 200. In the future, the second etch stop layer may be formed to have a thin thickness in order to diffuse the metal to the barrier layer during the heat treatment process of the gate electrode, and the second etch stop layer may be formed of InP.

After the deposition of the second etch stop layer, a dummy gate layer 220 is formed on the top. Since the present invention forms a T-type gate electrode by inserting a dummy gate layer into a conventional epitaxial layer, the lower region of the T-type gate electrode can be realized in a width of several tens of nanometers by overcoming the limitation of the conventional electron beam lithography equipment. The width of the lower region of the T-type gate electrode can be easily adjusted. The dummy gate layer is formed of a non-doped layer to form a gate electrode material of type T, for example, it is formed by applying a _{0 .52} In AlAs. The dummy gate layer may be thickly formed to reduce the parasitic capacitance between the gate mask and the channel and the smooth etching under the gate mask, which is a subsequent process. It is most preferable to form about 200 GPa.

The first etch stop layer 230 is deposited on the formed dummy gate layer. The first etch stop layer is preferably formed thin for ohmic characteristics, and may be formed of InP, which is the same material as the second etch stop layer.

Next, a cap layer 240 is formed on the first etch stop layer. The cap layer may be thicker than the thickness of the gate mask layer for an etching process of the dummy gate layer, which is performed later. After etching the gate layer, a metal material is deposited between the passivation layer and the gate mask during deposition of the final gate head, thereby forming an appropriate thickness because an unwanted gate foot is generated. The doping of the cap layer may be formed by separating the doping concentration in two stages in order to improve the ohmic characteristics and prevent interlayer mixing of the silicon dopant due to heat treatment. have. In one embodiment, a cap layer is formed of In _{0 .53} GaAs.

Thereafter, only the epitaxial layer of the active region to be operated as a transistor is etched and the remaining portions are etched in order to isolate the devices, and the active region is formed in a mesa shape. The source and drain electrodes of the region are deposited to form ohmic contacts, and a passivation layer is formed on the active substrate on which the ohmic contacts are formed. The passivation layer functions to prevent deterioration of characteristics that occur during the manufacturing of the HEMT device. In the present invention, the passivation layer is formed using Si ₃ N ₄ (250).

The process of forming the mesa process and the ohmic contact and passivation layer is the same as the conventional process, except that a dummy gate layer is inserted into the epitaxial layer formed on the semiconductor substrate during the HEMT device formation process. Is performed. Subsequently, the process is performed to form the T-type gate electrode of the present invention, and FIGS. 3B to 3H show only the formation region G of the T-type gate electrode.

Electron Beam Resist Pattern Formation

In order to form a T-type gate pattern, a multilayer resist forming process having an electron beam resist sensitive to an electron beam is performed on the passivation layer.

FIG. 3B of the present invention shows that the electron beam resist and the PMGI layer are applied on the passivation layer, and FIG. 3C of the present invention shows that the pattern of the electron beam resist and the PMGI layer is formed. The first electron beam resist 260, the PMGI layer 270, and the second electron beam resist 280 on the semiconductor substrate on which the coating process for forming the T-type gate electrode is completed, that is, on the Si ₃ N ₄ layer 250. Are applied sequentially, and then patterned. In this case, the patterned width D ₂ of the second electron beam resist is formed to be wider than the patterned width D ₁ of the first electron beam resist so that an upper portion of the second electron beam resist is formed wider than the lower portion thereof.

In detail, the second electron beam resist pattern formed on the top of the semiconductor substrate is defined as the upper width of the T-type gate electrode. The second electron beam resist may be a ZEP that can be implemented with a minimum line width as a positive electron beam resist, and is formed using an electron beam lithography apparatus.

Thereafter, the PMGI film is etched using the patterned second electron beam resist as a mask. The PMGI film, which is an intermediate layer between the first electron beam resist and the second electron beam resist, was subjected to side etching by controlling the etching degree by controlling the time by a wet etching method using tetramethylammonium hydroxide aqueous solution or the like. The width D ₃ of the side-etched PMGI layer is larger than the pattern width of the second electron beam resist, which is T-shaped to form a wide cross-sectional area of the upper part in order to reduce noise of the T-type gate electrode and improve noise characteristics. This is to define the head area of the gate.

Subsequently, a first electron beam resist pattern formed on the bottom surface of the etched PGMI film is formed. The first electron beam resist defines the length of the lower portion of the T-type gate and is implemented with a line width of 0.1 μm or less. The first electron beam resist pattern is a positive electron beam resist, and a resist such as ZEP capable of realizing a minimum line width is applied, and is formed using an electron beam lithography apparatus.

After all of the patterns of the first electron beam resist are defined, the Si ₃ N ₄ 250 formed under the first electron beam resist pattern is etched. The etching of Si ₃ N ₄ may be performed by a dry etching process using a mixed gas of SF ₆ / Ar. At this time, the first electron beam resist and react to the residue 300 to the etching side of the Si ₃ N ₄ mixed gas of SF ₆ / Ar of the etching process of the Si ₃ N ₄ is present in the upper portion of the Si ₃ N ₄ remains And is etched to a width smaller than the width defined by the first electron beam resist.

Etch of Cap Layer and First Etch Stop Layer

After the electron beam resist pattern forming process for forming the T-type gate electrode is performed, a process of etching a portion of the cap layer and the first etch stop layer under the electron beam resist pattern is performed.

3D is a cross-sectional view of a semiconductor substrate in which a cap layer and a first etch stop layer of the present invention are etched. In the process of etching a portion of the cap layer 240 and the first etch stop layer 230, a process for forming a gate on the barrier layer is performed in the same process for manufacturing a conventional HEMT device. . The cap layer is subjected to a wet etching process using a solution of citric acid (citric acid, C ₆ H ₈ O ₇ ) and hydrogen peroxide (H ₂ O ₂ ) in a ratio of 7: 1, and the first etching stop layer is hydrochloric acid (HCl). A wet etching process using an etching solution of: H ₃ PO ₄ : H ₂ O = 1: 1: 1) can be applied.

Formation of gate mask

A process of forming a gate mask in the etched regions of the cap layer and the first etch stop layer is performed in the structure etched to the first etch stop layer of the substrate on which the process is completed. The gate mask layer is used as a mask in the subsequent etching process of the dummy gate layer, and after being used, the base gate mask can stably metallize the gate layer through a heat treatment process performed finally. Structure. The gate mask is formed of nickel (Ni) and platinum (Pt), and may be deposited by an electron beam evaporator. 3E is a cross-sectional view of a semiconductor substrate on which a gate mask 320 is formed in a structure etched to a cap layer and a second etch stop layer.

Dummy Gate Layer Etch

After forming the gate mask layer, a recess process of etching a portion of the dummy gate layer under the gate mask is performed by applying the gate mask layer as a mask to form a lower region of the T-type gate electrode. do. 8 illustrates a result of performing a recess process using the gate mask 320. The recess process for etching the dummy gate layer wets only the dummy gate layer by applying a second etch stop layer as an etch stop layer. The solution used for the wet etching is etched using a solution of phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O) in a 1: 1: 400 mixture. In this case, the etching rate of the gate layer from the lower side of the gate mask is larger than that of other regions due to the effect of electrochemical etching by Ni / Pt constituting the gate mask layer. 330 is formed as shown in FIG. 3F.

Deposition of final gate electrode material

After the etching of the gate layer is completed, a process of sequentially depositing a T-type gate electrode to be finally formed is performed. As shown in FIG. 3G, the gate electrode is deposited by sequentially depositing titanium (Ti), platinum (Pt), and gold (Au). Therefore, the formed T-type gate electrode is formed in a multilayer structure of Ni / Pt 320 / Ti 340 / Pt 350 / Au 360 based on the lower portion. The Ti serves to prevent diffusion of the bottom of the Pt, and the Pt deposited on the Ti is used to prevent diffusion of Au, which functions as a head of the T-type gate electrode, and the Ti 340 and the Pt 350. Is the diffusion barrier layer 380 of the T-type gate. In addition, Au, which is a head material of the gate electrode, may have a low resistance, thereby improving noise characteristics of the T-type gate electrode, thereby improving reliability of the HEMT device in the future.

Lift off and gate heat treatment

After removing the first electron beam resist, the PMGI layer, and the second electron beam resist among the structures on which the final gate electrode material is deposited by a lift-off method, the dummy gate layer 330 under the gate mask is opened. Metallization is used to form the lower part of the T-type gate electrode. The heat treatment process uses a rapid thermal treatment (RTA) apparatus, and the process is performed by injecting nitrogen gas into the chamber at a flow rate of 5 torr.

Accordingly, the present invention forms a lower portion 330 of the gate electrode by applying a dummy gate layer to the bottom surface of the gate mask layer 320, so that the width L _GO of the lower portion of the conventional T-type gate electrode is shown in FIG. 3H. It is possible to form a lower width (L _G ) of the gate electrode even narrower, thereby overcoming the limitations of the electron beam lithography equipment to achieve a narrower line width than the minimum possible line width that can be implemented, thereby, HEMT There is an advantage of improving the cutoff frequency characteristic and the reliability of the device.

As described above, according to the present invention, the width of the lower region of the T-type gate electrode may be realized at several tens of nanoscales, and the effect of overcoming the limitations of existing equipment may be achieved.

In addition, according to the present invention, the gap of the open region of the passivation layer is first filled with a metal material in several tens of nanometers to prevent the problem of disconnection of the gate electrode, thereby improving the process yield, thereby improving the characteristics of the HEMT device There is an effect that can increase the reliability by preventing degradation.

Claims (22)

Forming an electron beam resist pattern on the semiconductor substrate on which the buffer layer, the channel layer, the barrier layer, the second etch stop layer, the dummy gate layer, the first etch stop layer, the cap layer, and the passivation layer are formed (S1); Etching the passivation layer formed under the electron beam resist pattern (S2); Etching (S3) the cap layer and the first etch stop layer formed under the etched region of the passivation layer; Forming a gate mask in the etched cap layer and the first etch stop layer (S4); Recess etching the dummy gate layer formed under the gate mask and above the second etch stop layer (S5); And Depositing a metal layer for forming a gate electrode on the gate mask (S6) T-type gate electrode forming method comprising a. The method of claim 1, After the step (S6), further comprising the step of heat treatment to metallize the recess-etched dummy gate layer. The method of claim 1, The passivation layer is Si ₃ N ₄ T-type gate electrode forming method. The method of claim 1, The step (S1), Sequentially forming a first electron beam resist, a PMGI layer, and a second electron beam resist on the cap layer; Forming the second electron beam resist pattern; Side etching the PMGI layer; And Forming the first electron beam resist pattern T-type gate electrode forming method comprising a. The method of claim 4, wherein And the first electron beam resist and the second electron beam resist are positive electron beam resists. The method of claim 5, And the positive electron beam resist is ZEP. The method of claim 4, wherein The etching in the side etching step of the PMGI layer is a wet etching method using an etching solution of tetramethylammonium hydroxide aqueous solution. The method of claim 1, The etching in the step (S2) is a dry etching using a mixed gas of SF ₆ and Ar T-type gate forming method of the HEMT device. The method of claim 1,  The etching in the step (S3) is a wet etching method of forming a T-type gate electrode. The method of claim 9, The method of claim 1, wherein the capping layer is etched using a solution obtained by mixing citric acid (C ₆ H ₈ O ₇ ) and hydrogen peroxide (H ₂ O ₂ ) at 7: 1 in the wet etching solution. The method of claim 9, And forming a first etching stop layer using a solution of hydrochloric acid (HCl: H ₃ PO ₄ : H ₂ O = 1: 1: 1) as the etching solution in the wet etching. The method of claim 1, Etching in the step (S5) is T-type wet etching using a solution of phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O) in a ratio of 1: 1: 400 Gate electrode formation method. The method of claim 1, The step (S6), Depositing a diffusion barrier layer in a single layer or multiple layers on top of the gate mask; And Depositing a gate head layer on top of the diffusion barrier layer T-type gate electrode forming method comprising a. The method of claim 1, The first and second etch stop layers are InP. The method of claim 1, In the cap layer of GaAs _{0 .53} T-shaped gate electrode forming method. A lower region of the T-type gate electrode formed on the semiconductor substrate; A gate mask formed on the lower region to form the lower region; A diffusion barrier metal layer of one or more layers that prevents diffusion of the gate mask and the gate electrode head; And A gate head formed on the diffusion preventing metal layer T-type gate electrode comprising a. The method of claim 16, The semiconductor substrate is a T-type gate electrode for forming an HEMT device, which is any one of a GaAs-based and an InP-based substrate. The method of claim 16, The lower region is a non-doped T-type gate electrode. The method of claim 18, The lower region is In _0.52 AlAs T-type gate electrode. The method of claim 16, And the gate mask is Ni / Pt. The method of claim 16, The diffusion barrier metal layer is Ti / Pt T-type gate electrode. The method of claim 16, And the gate head is Au.

Images