JPS6281769A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To make the length of a gate extremely short, by reducing the gate length shorter than a size determined by exposure technology. CONSTITUTION:A metal film 20 is etched by a etching method such as ion milling. At this time, the thickness in the depth direction of the metal film, which is deposited in a groove 21, is thicker than the other part. Therefore, the metal film at this part remains and a gate electrode 22 is formed. At this time, the length lg of the gate electrode 22 is reduced by twice the thickness t1 of an SiO film 19 with respect to the length l of an opening hole of an SiN film 17. For example, when l is 0.5-1.0mum, which can be implemented by ordinary exposure technology, the lg becomes 0.1 or less - about 0.6mum. Since the gate length lg can be reduced by twice the thickness t1 of the SiO2 film 19 with respect to the size l determined by the exposure technology, the very short gate length can be implemented.

Description

[Detailed description of the invention] [Industrial application field] The present invention has an extremely short gate length and low gate resistance.

This invention relates to a method of manufacturing a field effect transistor that has extremely low source resistance and is suitable for ultra-high speed and ultra-high frequency applications.

[Conventional technology]

Conventionally, in the manufacturing method of this type of field effect transistor (hereinafter abbreviated as FET), the valley dimension is miniaturized.

Self-line technology is used to improve yield. FIG. 3 shows a typical manufacturing method of a conventional FET. In the manufacturing method shown in FIG. 3, a mouth-shaped semiconductor layer 2 is formed on a high-resistance semiconductor substrate 1 by, for example, ion implantation, and then a gate electrode 3 is formed across this semiconductor layer.
(Fig. 3(a)). Next, a silicon oxide film 4 is deposited on the entire surface by thermal CVD (Fig. 3(b)).
Etched by reactive ion etching (hereinafter abbreviated as RIE) having anisotropic etching characteristics,
A side wall 5 of a silicon oxide film is formed on the side surface of the gate electrode 3 (FIG. 3(C)). Next, an ohmic metal 6 such as a gold-germanium alloy and nickel are sequentially deposited on the entire surface, and a resist 7 is further applied to a thickness such that the resist surface is flattened (@3 (d)). Next, the resist 7 is etched by RIE to expose the ohmink metal 6 on the gate electrode 3 and the silicon oxide sidewalls 5 (
Figure 3(e)). Furthermore, after removing the exposed ohmic metal by ion milling, the resist 7 is removed by RIE or plasma etching, and the source electrode 8.
A drain electrode 9 is formed.

[Problem that the invention seeks to solve]

The conventional FET manufacturing method described above has various drawbacks. 1. Shortening the gate length (Fig. 3(a)) is extremely important for improving FET performance, but with this method, shortening the gate length depends on the exposure technology, and the smallest E
Even using the B exposure technology, it is difficult to realize a gate length of 0.3 μm or less with a good yield. In addition, a region 10 directly under the gate electrode 3 of the F'ET (Fig.
The carrier concentration and thickness of the semiconductor N (hereinafter referred to as the active layer of the FET) in f)) are determined to a certain value depending on the threshold voltage of the FET.
(FIG. 3(f)), the higher the carrier concentration and the thicker the thickness, the lower the source resistance and the higher the high frequency performance. However, the above manufacturing method has the disadvantage that reduction in source resistance is structurally limited because the regions 10 and 11 have the same carrier concentration and thickness.

An object of the present invention is to solve the above-mentioned drawbacks of the conventional FET manufacturing method and to provide an FET manufacturing method suitable for ultra-high speed and ultra-high frequency applications.

[Failure to solve the problem]

In the present invention, as a semiconductor substrate, an n-type semiconductor layer which becomes an active layer of an FET is formed in advance on a high-resistance semiconductor substrate to a thickness thicker than that at which a predetermined threshold voltage of the FET is obtained, and then a high electron concentration By using an n-type semiconductor layer, only the active layer in the region immediately below the gate electrode can be selectively etched using the first insulating film as a mask, so the area directly below the gate electrode can be etched to a predetermined thickness of 1. The n-type semiconductor layer is used as an active layer, while the source electrode i
■The lower region is made of two layers: a thick n-type semiconductor layer and a high-concentration n-type semiconductor layer, making it possible to reduce the source resistance. The second (or even third) insulating film makes it possible to simultaneously shorten the υ gate length and control the source-gate electrode spacing, the drain-gate electrode spacing, and the spacing between the high-concentration n-type semiconductor layer and the gate electrode. The most important feature is that by leaving an ohmic layer at the top of the gate electrode, the thickness of the gate electrode can be increased and the gate resistance can be reduced.

[Effect]

According to the above, it is possible to make the region directly under the source electrode a thicker semiconductor layer with higher carrier concentration than the active layer directly under the gate electrode, and to increase the gate length using fine exposure techniques such as FJ exposure. It can be shortened without using it, and the thickness of the gate electrode can be increased.

〔Example〕

FIG. 1 shows a first embodiment of the FET manufacturing method according to the present invention, in which a high-resistance semiconductor substrate such as GaA, etc.
For example, υFET is formed on the
For example, the active layer has a carrier concentration of 1 to 3 × 10
"cm-", the n-type semiconductor layer 13 with a thickness of about 0.1 to 0.5 μm and a carrier concentration of 10 cm or more and a thickness of 0.1 to 0.5 μm, for example, to reduce the source resistance of the FET.
A semiconductor layer 15 made of a highly doped n-type semiconductor layer 14 of about 3 μm is formed (FIG. 1(a)). Next, a first insulating film is formed on the entire surface 16 of the semiconductor layer using, for example, plasma CVD.
For example, a silicon nitride film 17 (hereinafter abbreviated as SiN film) is formed to a thickness of about 0.5 to 1.5 μm by method D, and then a resist layer is applied to the entire surface, and the semiconductor layer is then coated by a known method. 15'i The entire batan with holes opening across it is formed,
Using this resist layer as a mask, the SiN film is etched by RIE using a fluorocarbon gas such as CF4, and then the resist is removed to form a SiN film 17 having openings across the semiconductor layer 14. Figure 1(b)
). Next, using this SiN film 17 as a mask, the exposed semiconductor layer is etched by high concentration n-type etching using an etching method with anisotropic etching characteristics, such as reactive ion beam etching (hereinafter abbreviated as RIBE) using a chlorine-based gas such as BCIs. The semiconductor layer 14 is removed, and the n-type semiconductor layer is further heated to a thickness (0,1 to -3V) that provides a predetermined threshold voltage, for example, about -IV to -3V.
0.15 pm) (see Figure 1 (C)).
)). Next, as the second insulating film, for example, a plasma CVD film is formed.
For example, a silicon oxide film 18 (hereinafter abbreviated as SiO film) is formed on the entire surface to a thickness of about 0.2 to 0.5 μm by a method (FIG. 1(d)), and then an etching method having anisotropic etching characteristics is performed. For example, this SiO film 18 is etched by RIE using CF4. At this time, the above 5
ill exchange 17, SiO attached to the side wall of the semiconductor layer 15
Since the thickness of the film 19 in the depth direction is thicker than other parts, only the SiO film 19 attached to this side wall remains. This S
The iO film has a thickness tl of 0.2 to 0.5 pm and a height hl.
is 6 to 1.65 μm (Fig. 1(e)). Next, a metal film 20 made of, for example, two layers of metal, for example, aluminum, which makes Schottky contact with the n-type semiconductor layer 13, is formed to have a sufficient thickness, for example, by sputtering to flatten the groove 21 on the entire surface. 0.5～
After a deposition of about 1.0 pm (FIG. 1(f))), an etching method having anisotropic etching characteristics, such as Ar ions, was used. For example, this metal film 20 is etched by an etching method such as ion milling. At this time, since the thickness of the metal film deposited in the trench 21 in the depth direction is thicker than in other parts, the metal film in this part remains and forms the gate electrode 22 (FIG. 1(g)). . At this time, the length lf of the gate electrode 22 is twice the length l of the opening in the SiN film 17 (FIG. 1(C)) and the thickness tL of the StO film 19 (FIG. 1(E)). For example, if 1 is set to 0.5 to 1.0 pm, which can be realized by ordinary exposure technology, then 12 becomes from 0.1 .mu.m or less to about 0.6 .mu.m.

Further, the thickness of the gate electrode is determined by the height hi (of the SiO film 19).
It is possible to achieve a thickness close to that shown in Figure 1(e), for example 0.
．． It is about 4 to 1.1 μm. Next, the SiN film 17'
It is removed by plasma etching using CF4F, for example, to expose the high concentration n-type semiconductor #14' (FIG. 1(h)). Next, a metal film 23 made of, for example, two layers of metal such as gold germanium alloy and nickel, which makes ohmic contact with this high concentration n-type semiconductor layer 14, is formed to a thickness of about 0.1 to 0.5 μm.

For example, υ is attached by vacuum evaporation method etc. (Fig. 1(i))
.

Next, a resist layer 24 is applied to a thickness such that the surface thereof is flattened, for example, about 1.0 to 3.0 μm, and dried by heating (FIG. 1 (J)). Next, this resist layer 24 is etched by an etching method having anisotropic etching characteristics, for example, RIE using oxygen gas, and the SiO film 1 is etched.
The metal film 25 attached on top of 9 is exposed (see FIG. 1(k)
)). Next, the metal film 25 is removed by, for example, ion milling using Ar ions, and the remaining resist layer 24 is removed using a solvent or the like to remove the source electrode 26. A drain electrode 27 is formed (FIG. 1(1)). At this time, a metal film 28 is placed on the gate electrode 22 with a thickness of 0.1 to 0.5 μm.
Since a certain amount remains, the thickness of the gate pole can be increased by this amount. Further, the region immediately below the source electrode 26 is formed of the heavily doped n-type semiconductor layer 14 and the n-type semiconductor layer 13 which is thicker than the region directly below the gate electrode 22 .

As explained above, according to the FET manufacturing method according to the present invention, the gate length 19 (FIG. 1 (9)) is 5102 films for the dimension 1 (FIG. 1 (C)) determined by exposure technology. 1
Since the thickness can be reduced by twice the thickness 1+ (FIG. 1(e)) of 9, an extremely short gate length can be realized without using fine wr source technology such as EBN light. Furthermore, the gate electrode n
In addition to the thickness hy (see FIG. 1(?)), the thickness of the gate electrode 22 is increased by the amount of the metal film 28 deposited on the gate electrode 22, thereby making it possible to lower the gate resistance. In addition, the source electrode 26
The region immediately below is formed by a highly doped n-type semiconductor layer and a thick n-type semiconductor layer, making it possible to lower the source resistance.

Moreover, the distance between the source electrode and the gate electrode, and between the high electron concentration n-type semiconductor on the source electrode side and the gate electrode is determined by the SiO2 film 19.
Film thickness 91. As shown in FIG. 1(e), the source resistance can be lowered because it can be made shorter regardless of the exposure technique.

Further, FIG. 2 shows a second embodiment of the FET manufacturing method according to the present invention. @Figure 2 (a), (the process in bl is the same process as in Figure 1 (a), (b),
The numbers in the figures also indicate the same thing. Next, SiN film 1
7. The semiconductor layer 15 is etched using the same method as in FIG. 1(C) as a mask (FIG. 2(c)).
At this time, the high concentration n-type semiconductor layer 14 is removed in FIG. 1
5 μm) 1), whereas Fig. 2 (e
), only the high concentration n-type semiconductor layer 14 is removed. Next, for example, the SiO film 2 is
The film 9 is formed on the entire surface to a thickness of, for example, 0.1 to 0.5 μm (FIG. 2(d)), and then the SiO film 2 is etched using the same etching method as in FIG. 1(e). Tsuching. At this time, the SiN film 17. Since the thickness of the SiO film J attached to the side wall of the semiconductor layer 15 in the depth direction is thicker than other parts, the SiO film J attached to the side wall remains as in FIG. 1(e). The thickness t2 of this SiO film is 11
~0.5pm r height h2 becomes sail 5~1.5μm (
Figure 2(e)).

Next, using this SiO film and the SiN film 17 as a mask, an etching method having anisotropic etching characteristics such as RIB is applied.
The semiconductor layer 15 is etched using Ei, and the n-type semiconductor layer 13 is etched to a thickness (approximately 0.1 to 0.15 μm) that provides a predetermined threshold voltage, for example, approximately -IV to -3V (see FIG. 2(f)). )). Next, for example, a SiO film 31, for example, is formed over the entire surface to a thickness of about 0.1 to 0.5 μm by, for example, the plasma CVD method (Fig. 2 (g)).
Next, this SiO film 31 is etched by an etching method having anisotropic etching characteristics, such as RIE. At this time, the SiO film 30. Since the thickness of the StO film 32 attached to the side wall of the semiconductor layer 15 in the depth direction is thicker than other parts, only the SiO film 32 attached to this side wall remains. The thickness t8 of this SiO film is 0.1 to 0.5 μm.
, the height h8 is 5 to 1.5 μm (Figure 2 (h))
.

The subsequent steps are the same as those in FIGS. 1(f) to (k) except that the 9i0 films 30 and 32 on the SiO film 1 shown in FIG. 1 are replaced to form the source electrode 26. drain electrode n,
A gate electrode 22 is formed (FIG. 2(i)). The FET manufacturing method of the second embodiment of the present invention described above is different from that of the first embodiment in FIGS.
) is different in that the process is repeated for two layers.
As shown in Figure (i), the n-type semiconductor layer 13 between the source electrode 26 and the gate electrode 22 and between the drain electrode 27 and the gate electrode 22 has a stepped shape.

In addition, the gate length lf (Fig. 2 (i)) is determined by υ depending on the exposure technology.
Add a SiO film to the determined dimension l (Fig. 2 (C)).

32 thickness t2. tg (Figure 2 (e), (h)
), it is possible to achieve an extremely short gate length, similar to the first embodiment, without using exposure technology such as EB II light. Furthermore, since the n-type semiconductor layer 13 between the source electrode 26 and the gate electrode 22 has a stepped shape, when the distance between the source electrode 26 and the gate electrode η is the same as in the first embodiment (tg ” ta = h), the resistance due to this interval is lower than in the first embodiment, and the source resistance is further reduced by this amount compared to the first embodiment.

Using this method, the gate length is 0.1 μm, the gate electrode thickness is 2.0 μm, and the n-type semiconductor layer concentration is 3×.
FET with short gate length, low gate resistance, and low source resistance, with IO"cm'-', thickness 0.3 pm, high concentration n-type semiconductor 11 x lυ" cm=, 0.2 l+m double layer. When manufactured, a cutoff frequency of about 80 GI (z), which is about 40 GHz higher than the conventional value, is obtained, and the noise figure NF is reduced by about 2 dB at 30 GHz, and about 1 dB is obtained, and the high frequency characteristics are improved. Extremely improved.

〔Effect of the invention〕

As explained above, according to the F'ET manufacturing method of the present invention, the gate length can be made smaller than the dimension determined by exposure technology, making it possible to make the gate length extremely short.

In addition, the gate resistance can be lowered by the gold M4 film deposited on the gate electrode, and the region directly under the source electrode is formed by a highly doped n-type semiconductor layer and a thick n-type semiconductor layer. Furthermore, the distance between the source electrode and the gate electrode, as well as the distance between the high electron concentration n-type semiconductor on the source electrode side and the gate electrode, is determined by the thickness of the SiOg film on the sidewall and can be shortened regardless of the exposure technique, making it possible to lower the source resistance. be. For these reasons, it is possible to realize an FET with low gate resistance, low source resistance, and extremely short gate length, and to improve its high frequency performance.

[Brief explanation of drawings]

FIGS. 1(a) to (1) are diagrams showing an example of the F'ET manufacturing method according to the present invention, and FIGS. 2(a) to (i) are diagrams showing an example of the F'ET manufacturing method according to the present invention. Figures 3(a) to 3(f) are diagrams showing the manufacturing process of a conventional example. 1... High resistance semiconductor substrate 2... N-type semiconductor layer 3... Gate electrode 4...Silicon oxide film 5...Silicon oxide film 6 on side wall portion...Ohmic metal 7...Resist 8...Source electrode 9...Drain electrode 10...Region 11 directly under the gate electrode ...Region 12 directly under the source electrode...High resistance semiconductor substrate 13...N-type semiconductor layer 14...High concentration n-type semiconductor layer 15...Semiconductor layer 16...Semiconductor layer surface 17... SiN film 18...SiO film 19...SiO film 20 on the side wall...Metal film 21 making Schottky contact...Drilled trench 22...Gate electrode...Metal film 24 making ohmic contact ...Resist layer 5...Metal film 26...Source electrode n...Drain electrode 28...Metal film 4...SiO film (9)...SiO film 31 on side wall...SiO Film 32...SiO film on side wall

Claims (2)

[Claims] (1) Forming a semiconductor layer consisting of at least two layers, with a semiconductor layer with high carrier concentration as the top layer and the next layer as a semiconductor active layer, in a partial region including the main surface of a high-resistance semiconductor substrate. a step of forming a first insulating film having an opening portion across the semiconductor layer, etching the semiconductor layer in the opening portion using the insulating film as a mask, and etching the semiconductor layer with at least the high carrier concentration. removing the layer to expose the semiconductor active layer; and forming a second insulating film on opposing sidewalls of the first insulating film and the semiconductor layer to reduce the exposed surface of the semiconductor active layer. a step of forming a metal that makes Schottky contact with the semiconductor active layer on the entire exposed surface of the semiconductor active layer to form a gate electrode; and a step of removing the first insulating film and forming the high carrier concentration semiconductor layer. a step of exposing, and a step of attaching a metal that makes ohmic contact with the high carrier concentration semiconductor over the entire surface;
Of the metals that adhere to the entire surface, the metal that adheres to the top of the second insulating film is removed, the metal that adheres to the high carrier concentration semiconductor layer and the metal that adheres to the gate electrode are separated, and the metal that adheres to the top of the gate electrode is removed. 1. A method for manufacturing a field effect transistor, comprising the step of forming an electrode and a drain electrode. (2) Forming a semiconductor layer consisting of at least two layers, with a high carrier concentration semiconductor layer as the top layer and the next layer as a semiconductor active layer, in a partial region including the main surface of the high-resistance semiconductor substrate. a step of forming a first insulating film having an opening portion across the semiconductor layer, etching the semiconductor layer in the opening portion using the insulating film as a mask, and etching the semiconductor layer with at least the high carrier concentration. removing the layer to expose the semiconductor active layer; and forming a second insulating film on opposing sidewalls of the first insulating film and the semiconductor layer to reduce the exposed surface of the semiconductor active layer. a step of etching the semiconductor active layer using the first insulating film and the second insulating film as masks; and a step of forming a third insulating film on opposing sidewalls of the second insulating film and the semiconductor active layer. A step of forming a metal that makes Schottky contact with the semiconductor active layer on the entire surface of the exposed semiconductor active layer and forming a gate electrode, and a step of removing the first insulating film and forming the high carrier concentration semiconductor layer. an exposing step, a step of attaching a metal that makes ohmic contact with the high carrier concentration semiconductor to the entire surface, and removing the metal attached to the upper part of the second and third insulating films from among the metals attached to the entire surface. A method for manufacturing a field effect transistor, comprising the step of: separating metal deposited on the high carrier concentration semiconductor layer from metal deposited on the gate electrode to form a source electrode and a drain electrode.