JPS6180870A - Semiconductor transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the parasitic resistance and the parasitic capacity, and moreover, to improve the reverse gate withstand voltage and to contrive the improvement of the microwave characteristics in a semiconductor transistor provided with the gate with the T-shaped section by a method wherein one end of the source electrode is made to planarly conform to the end edge on one side of the gate and one side of the gate and one end of the drain electrode is made to locate away from the end edge on the other side of the gate. CONSTITUTION:An active layer 12 is formed on a semiinsulative substrate 11; a gate electrode 15 in the structure, wherein the section is formed in a T shape, a source electrode 13 and a drain electrode 14 are provided on the surface of the active layer 12; and the relative positions among the gate, source and drain electrodes 15, 13 and 14 are respectively set so that the end on one side of the overhung part of the gate electrode 15 is made to planarly conform to one end of the source electrode 13 and the other end of the overhung part of the gate electrode 15 is made to locate away from one end of the drain electrode 14. By this method, a reduction in the gate resistance due to the T shaped structure of the gate, the improvement of the reverse gate withstand voltage due to the offset structure of the gate, wherein the interval between the gate and drain electrodes is widened, and the improve ment of the drain withstand voltage can be contrived without making the feedback capacity and fringing capacity on the side of the drain increase.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor transistor that aims to improve performance at extremely high frequencies and a method for manufacturing the same.

(Prior art) In recent years, semiconductor transistors have operating frequencies in the X band (8 to 8
i2 GHz) to ni band (18-26 GHz)
.

Research and development efforts are being actively conducted to improve performance and reliability in the Ka band (26 to 40 GHz) and higher frequency ranges. In order to improve performance, it is necessary to reduce the gate length of transistors, increase the cutoff frequency by using submicron gates, and reduce the parasitic resistances of the source and gate. Conventionally, the inventors reported at the 1985 National Conference of the Institute of Electronics and Communication Engineers a submicron or smaller gate transistor with reduced parasitic resistance, as shown in Figure 3 (
,), a gate metal AA 43 is deposited on a semi-insulating substrate 41 provided with an active layer 42, and by side etching using a resist pattern 44 as a mask, the gate metal AA 43 is etched as shown in FIG. 3(b). After shaping the gate length to 0.5 microns and depositing the ohmic metal 44, a lift-off method in which the mask is removed is used to form the bottom electrode 56 and the drain electrode 4.
7 to obtain a 0.5 micron gate superelectrode structure transistor as shown in FIG. 3(c). However, although the source resistance of such transistors can be reduced, since the side etching method is used, the cross-sectional shape of the date is not rectangular but trapezoidal or triangular, which increases the gate resistance and impairs microwave characteristics. It had the disadvantage of causing sexual deterioration. In particular, if the gate length is set to 0.2 micron class in order to further improve performance, the above-mentioned tendency will become even more pronounced.

In 1979, the Institute of Phys developed a transistor that solved these problems.
In ics ConfPr-ene, J.W.
'holey et al. reported.

As shown in FIG. 4(a), an active layer 42 is formed on a semi-insulating substrate 41, and is further shaped like the letter T? -) The electrode 48 is shaped to increase the gate cross-sectional area to reduce gate resistance, while the ohmic electrode 4
6.48 is a transistor formed in a self-alignment manner using the gate electrode 48 as a mask.

(Problems to be Solved by the Invention) However, in such a transistor, the source resistance and ? -) Although resistance can be reduced, the gate reverse breakdown voltage and drain breakdown voltage are low due to the short gap between the gate and drain electrodes as well as the gap between the source and gate electrodes. When applied to transistors, the input power cannot be increased or gate leakage current flows, which impedes improvement in microwave characteristics. As a modification a to this point, a transistor with a so-called offset structure, in which the upper end of the T-shaped gate 48 is shortened toward the source electrode 46 side and lengthened toward the drain electrode 47 side, is considered, as shown in FIG. 4(b). It will be done.

However, in such a transistor, the l'l capacity between the upper part of the drain side of the T-type gate and the active layer and the Flynnong capacitance between the upper part of the T-shaped gate and the drain ohmic electrode become large. Return';+('
Regarding the amount of u, normal e.g. 5102 or Si3N4
When the dielectric material S is provided as a surface passageway, the length becomes even larger, and the distance is 1 m, which is a large distance in terms of improving microwave characteristics.

The present invention eliminates such conventional drawbacks, and provides a semiconductor transistor and a semiconductor transistor which reduce parasitic resistance and parasitic resistance, increase reverse breakdown voltage, and improve microwave characteristics. The object of the present invention is to provide a manufacturing method thereof.

(Means for solving the problem) The present invention has a T-shaped cross section. -), in which the end of the source electrode is aligned in plan with one edge of the overturned c-t, and the end of the drain electrode is located away from the other edge of the date. A resin layer is coated on the active layer made of a semiconductor transistor of a conductive type and an active layer made of a semiconductor of a conductive type is coated and baked at a high temperature, an electrically insulating layer is provided by spin coating and baked, and a conductive film is further provided, and then the electrically conductive layer is formed. A process of etching openings in the conductive film and the electrically insulating layer using the charged particle gland formed on the electrically conductive film as a first mask, and then etching the anti-lipid layer to a wider area than the etching mask. and then removing the resin layer by etching until the active layer has the same dimensions as the etching mask;
A step of depositing a first metal scrap on the exposed active layer, and then, after removing the etching mask, depositing the second and third metal layers to a thickness of 1:1 at the gate opening. The process of thickly depositing the metal 13, the etching mask, the second mask provided on the metal 13, and the second mask. etching the third metal layer; after removing the second mask, forming a third mask on the gold that covers from one end of the layer to the resin layer; and using the mask, the resin layer reaches the conductive layer. The source, drain, ?
-) Semi-4 whose special feature is to perform the process of forming electrodes.
This is a method for manufacturing a physical transistor.

The present invention will be explained below using figures.

As shown in FIG. 1, an active layer 12 is formed on a semi-insulating substrate 11, and its surface has an IcT type cross-sectional structure. ”
-) Electrical G115, source electrode 13, drain electrode 1
It is equipped with 4. In the present invention, r-) one overhanging end of the electrode 15 is aligned with the tip of the source heavy cannon 13 in plan view, and the other overhanging end is located at a position further away from the end of the drain electrode 14. is set. By forming an electrode on the active layer 12 of the semi-insulating substrate 11, the conventional problem can be solved without increasing the return capacitance and Flynnong capacitance on the drain side, that is, the T-type gate structure. r-) Reverse breakdown voltage due to reduction in gate resistance and gate offset structure with widened gate/drain electrode spacing.

Drain breakdown voltage can be improved.

In addition, for the intermediate layer that will be a sweep, the width of the opening on the substrate is the date dimension, the length of the first thin film is determined by the metal, and the mask side has a wide opening with an overhang structure, and the mask After removing the second. To deposit the third metal layer, r-)gold IA is deposited on the sides of the mask, filling the openings and increasing the thickness beyond a certain thickness. '-) Without the problem of not getting height? −) Tall and short with reduced resistance? =)
You can get a long one. Also, after etching the metal layer using the second mask to define the upper part of the T-shape, ohmic electrodes are formed using a lift-off method using the third mask while sweeping the intermediate layer, and form gate electrodes and fins 7, 4. □8
．． Oh. Oyuaaa, oh7,2. □r-) can be easily obtained. On the other hand, by using a high-temperature shot-type transfer metal as the first metal layer, stable Schottky properties can be obtained in terms of adhesive strength. (As for i, by providing a thick metal layer with high electrical conductivity, r-) resistance can be lowered to 5, and the intermetallic reaction between Schottky gold: 4 and the upper metal layer is 1/4. The present invention can be effectively realized by using straw, which is a film that enhances adhesion.

(Implementation sequence) Hereinafter, as a specific example of the present invention, Gariu↑砒;+=
The case where the barrier gate 4 is an effect transistor (hereinafter referred to as GaAs MES FET) will be described in detail with reference to the drawings. FIGS. 2(a) to 2(+) are cross-sectional views showing an embodiment of the present invention in step fi. first,
In Fig. 2 (-), semi-Ij color edged GaAs 4 plate 2
1 dose of St'1. i: 3 x 10 an
% acceleration energy near 0 KeV,
Active by annealing in water at 800°C for 20 minutes)2
2, then Renost AZ-1350 (product name)
was applied at 300 Qrpm, and after irradiation with external light, it was baked at 250° C. for 1 hour in a nitrogen atmosphere to form a buffer E (II II layer) 23 with a thickness of 5000×. Then S
l A 5.910CD film (1 product name) (manufactured by Rinkyo Ohka Co., Ltd.) is applied at 500 rpm and baked at 190° C. for 30 minutes in nitrogen to form a 5IO2 film 24 with a total of 1000×. Next, a tungsten film 25 is formed on the semi-insulating substrate 21 for conduction during the formation of EB:4 light beams, and then E'hTMA, which is a charged particle beam-based renost, is formed.
(poly methyl
e) Coat and bake a resist 26, and provide a 0.2 micron opening 27 by electron beam exposure. Then, using the resist no-turn as a mask, tungsten h25.5
i02 membrane 24 respectively SF6. Etching is performed by parallel plate reactive ion beam etching using CF4 gas to transfer the opening 27. Next, buffer No. 2
3, by circular plasma etching using 02 gas! Etching is performed to a thickness of 3,500 mm under conditions of +200 (W) and 100 mTorr, and by overetching, an opening 28 that is wider than the mask is formed (FIG. 2(b)).

Next, the buffer chamber 23 was exposed to a parallel plate reactive ion beam using 02 gas, Chingyo 9100 Wl.
GaAs active FI under the condition of 80 mTorr
Etching is performed until reaching 22, and an opening 29 having the same dimensions as the mask is formed (FIG. 2(C)). Same, at this time,
The top 7 Hpm resist 26 is etched away.

Subsequently, a first metal layer of tungsten 30 (15001) is deposited by coating (FIG. 1(d)).

Next, 5in21id 24 was mixed with hydrofluoric acid + water (1: 1o
), then the second metal, titanium 31, and the third metal, gold 32, are removed by Snow Irvine vapor deposition.
+300X.

6000X (Fig. 2(, )), and then a resist groove 33, which is wider than the gate iJ opening 27 and formed by ordinary photolithography so as to cover the gold 32, is used as a mask. Gold 32 and titanium 31 are etched by ion milling until they reach the puffer layer 23 (see Figure 2).
f)). Next, after removing Rujistono and Turn 33, gold 32
A resist turf 34 is formed so as to extend over one end of the gold layer 32, one end surrounds the other end of the gold 32, and extends over the buffer layer 23 (FIG. 2, 0)). Subsequently, the buffer layer 23 is etched using the resist grooves and turns 34 as a mask until the buffer layer 23 reaches the active layer 22. Next, Au, which is ohmic gold scrap,
G5/Ni35 is broken from the top (Fig. 2 (h)).

Next, the buffer layer 23 is removed by plasma etching using 02 gas, and the source electrode 36, the drain electrode 37, and the gate electrode 38 are removed.
A GaAs 5PET having the structure shown in FIG. 1 is obtained (FIG. 2 (1)).

In the present invention, as the first gold F4D, highly heat-resistant Schottky transition metals W, Mo, T^ and compounds of these with St and N are used, and as the second metal layer,
TI serves as a stock 4 for metal-to-metal reactions and as an adhesive.

pt, and Au, which has high electrical conductivity, as the third metal layer.

λg is used.

(Effects of the Invention) Comparing the GaAs MESFET obtained by the above steps with that obtained by the conventional manufacturing method shown in Fig. 3(,) and Fig. 4(,), (b), First, in the present invention, a high temperature baked resin layer is used as the intermediate layer, and spin coating is applied as a gate mask, and the resin thickness is also low at 2°4.
−． 7i+ "," 2 / ej-□ゎ, 7yaae, □1 Since 11 layers of electrical insulation are used, date metal is attached to the side of the mask, resulting in a triangular cross-sectional shape, or there is a limit to the thickness. without causing
The gate film thickness is thick, and it is possible to form an r-) electrode with a T-shape and a large cross-sectional area.

Also, after etching the metal layer and determining the upper part of the T-shape,
By using the buffer layer as a spacer and using another resist mask to form an ohmic pole by a lift-off method, an offset gate with a distance between the gate electrode and the drain electrode can be obtained. Furthermore, by using a buffer layer, it can be easily etched by 0276 plasma, which is different from, for example, an oxide film spacer in which a metal layer may be immersed using a hydrofluoric acid-based chemical etching solution.

? −) Capable of lift-off. The method of the present invention includes a first metal that becomes the metal 51 and a second metal that is laminated thereon.
By breaking the third gold KA layer in a separate process step, it is possible to consider Schottky characteristics with reliability in mind and gate resistance reduction independently when selecting metal materials. . In other words, when a highly heat-resistant transition metal with excellent Schottky properties is used as the first layer metal, it has a higher resistance than conventional AAK, and a T-shaped gate can be formed using a single gold layer. However, it is not possible to reduce the f-gate resistance sufficiently, so after thinning the first raw metal,
By laminating a thick material with high electrical conductivity such as Au through the intermetallic reaction stopper 14 and an adhesive, it is possible to easily and effectively reduce the gate resistance with a T-shaped structure.

The GaAs MESFET obtained in this way has lower date resistance than conventional ones, and −
) - By widening the gap between the drain electrodes, the gate breakdown voltage increases, for example from 14 (B) to 22 (V), and when used as a power FET, the operating voltage can be increased, the output power is improved, Furthermore, by using an offset structure, it has been experimentally confirmed that the distortion characteristics are improved, and the characteristics can be improved in these respects without being accompanied by an increase in parasitic capacitance.

In the above embodiments, GaAm has been described, but Si
, InAs may be used, and the material does not limit the present invention in any way.

41 1+N-level explanation of the drawings The first decoy is a cross-sectional view showing the structure of a clear semiconductor transistor, and Figures 2 (-) to (i) explain the manufacturing method of the semiconductor transistor of the present invention in the order of steps. A cross-sectional view of the dam,
3(a) to 3(C) are cross-sectional views for explaining the conventional semiconductor transistor manufacturing method step by step, and FIG. 4(,)
, (b) is a cross-sectional view for explaining the structure of another conventional semiconductor transistor.

11.21...Semi/monochromatic d-substrate, 12.22...
Active layer, 13°36... Source 1 pole, 14.37...
・Drain electrode, 15.38...? -)'iHM, 2
3...Buffer E, 24...S tO2, 25, 3
0...Tungsten, 26...PiGIA, 27
...opening, 28...first buffer layer opening, 2
9...Second buffer IFi DFI port r:L31・
・Parl, 32...8u, 33.34...Renost pattern, 35-AuGe/Ni 0 Figure 2 (α) (b) Figure 2 (C) (d) Figure 2 (e ) (f) (h) Figure 2 Figure 3 (α) (C)

Claims (2)

[Claims] (1) In a semiconductor transistor having a gate with a T-shaped cross section, the end of the source electrode is positioned planarly to coincide with one edge of the overhanging gate, and the end of the drain electrode is positioned farther from the other edge of the gate. A semiconductor transistor characterized by: (2) After applying a resin layer on the active layer made of a conductive type semiconductor and baking at a high temperature, an electrically insulating layer formed by spin coating and baking was provided, and a conductive film was further provided, and then a resin layer was formed on the conductive film. A process of etching openings in the conductive film and the electrically insulating layer using the charged particle radiation resist pattern as a first mask, and further etching the resin layer to a dimension wider than the etching mask, and then etching the resin layer with the same etching mask. etching away the resin layer until dimensions reach the active layer; depositing a first metal layer on the exposed active layer; then, after removing the etching mask, etching away the resin layer;
A process of depositing a third metal layer thicker than the resin layer thickness at the gate opening, and etching the second and third metal layers using a second mask wider than the etching mask and provided on the metal layer. After removing the second mask, forming a third mask covering from one end of the metal layer to the resin layer; etching the resin layer using the mask until it reaches the conductive layer; and then etching the ohmic metal layer. a process of applying
A method of manufacturing a semiconductor transistor, characterized by performing a step of forming source, drain, and gate electrodes by etching and removing a resin layer.