JPS6169869U - - Google Patents
Info
- Publication number
- JPS6169869U JPS6169869U JP15318484U JP15318484U JPS6169869U JP S6169869 U JPS6169869 U JP S6169869U JP 15318484 U JP15318484 U JP 15318484U JP 15318484 U JP15318484 U JP 15318484U JP S6169869 U JPS6169869 U JP S6169869U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- film
- semiconductor chip
- mounting electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図および第２図はこの考案の一実施例を示
し、第１図はフイルムに電極配線パターンを形成
する工程を示す図、第２図はフイルムの電極配線
パターンに半導体を取り付ける工程を示す図、第
３図は本考案の他の実施例を示す断面図、第４図
は従来のフイルム回路基板の断面図である。
１０…透明フイルム、１４…電極配線パターン
、１７…半導体チツプ、１７ｃ…電極パツド、１
８…異方性導電膜。
Figures 1 and 2 show an embodiment of this invention, with Figure 1 showing the process of forming an electrode wiring pattern on a film, and Figure 2 showing the process of attaching a semiconductor to the electrode wiring pattern of the film. 3 is a sectional view showing another embodiment of the present invention, and FIG. 4 is a sectional view of a conventional film circuit board. DESCRIPTION OF SYMBOLS 10... Transparent film, 14... Electrode wiring pattern, 17... Semiconductor chip, 17c... Electrode pad, 1
8...Anisotropic conductive film.
Claims (1)
ルム基板に形成された半導体取付電極を有する配
線パターンと、この配線パターンの前記半導体取
付電極に電気的接続される半導体チツプと、この
半導体チツプと前記配線パターンとの間に介在さ
れる絶縁膜とを具備してなるフイルム回路基板。 A film substrate made of a polymeric material, a wiring pattern having a semiconductor mounting electrode formed on the film substrate, a semiconductor chip electrically connected to the semiconductor mounting electrode of the wiring pattern, and the semiconductor chip and the wiring pattern. and an insulating film interposed between the film circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15318484U JPS6169869U (en) | 1984-10-12 | 1984-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15318484U JPS6169869U (en) | 1984-10-12 | 1984-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6169869U true JPS6169869U (en) | 1986-05-13 |
Family
ID=30711219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15318484U Pending JPS6169869U (en) | 1984-10-12 | 1984-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6169869U (en) |
-
1984
- 1984-10-12 JP JP15318484U patent/JPS6169869U/ja active Pending
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