JPS6169166A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a latch-up by forming an impurity region in concentration higher than a first semiconductor region by an impurity diffused to the first semiconductor region from a semiconductor substrate on heat treatment at a time when shaping a second semiconductor region and lowering substrate resistance. CONSTITUTION:A P type region 43 is formed in partial surface region in an N type region 42 by using a selective diffusion technique in the main surface of an N<+> type semiconductor substrate 41. N<+> regions 44, 45 are shaped in a surface region in the P type region 43 while P<+> type regions 46, 47 are formed in a surface region in the N type region 42. Since the state of a high temperature continues for a prolonged time when the P type region 43 is diffused and shaped, an impurity in the substrate 41 is diffused into the N type region 42 in a section being in contact with the substrate 41, and a section being in contact with the P type region 43 of the N type region 42 is changed into N<+> and an N<+> type region 56 is formed. The values of equivalent resistors 28-32 in the N<+> type region 56 turned into N<+> are reduced extremely, thus hardly generating a latch-up phenomenon, then resulting in exceeding resistance against breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary broS semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can be strengthened against destruction due to latch-up.

[Technical background of the invention and its problems]

Complementary MO8 semiconductor device (hereinafter abbreviated as CMO8) has P-channel and N-channel transistors formed on the same substrate, and these two transistors are connected in series, which is used as the basic circuit element. It has various features such as the possibility of integration and low power consumption.

Therefore, in recent years, CMO8 has been applied to various circuits. However, as a disadvantage of CMO8, it cannot be denied that it is vulnerable to destruction, and a first-order destruction phenomenon occurs. One of the seven causes is damage caused by latch-up, damage caused by secondary breakdown of the withstand voltage of N-channel transistors, and electrostatic damage caused by the r-type oxide film.

Among these, destruction due to latch-up is an unavoidable failure mode due to the 0MO8 structure, and although extensive countermeasures have been taken to prevent destruction due to latch-up, there are no measures that can completely prevent it. is the current situation.

Next, the destruction phenomenon due to latch-up will be explained using an example of an inverter with 0MO8. FIG. 3 is a sectional view showing the configuration of a conventional inverter. In the figure 1
1 is an N-type semiconductor substrate, 12 is a P-type region provided on the main surface side of this semiconductor substrate 11, 13.14 is provided on the surface region of this P-type region 12 at a constant interval, N4 type regions, 1s, is, which will become the source and drain regions of the N-channel transistor, are provided at regular intervals on the surface region of the N-type semiconductor substrate, and the P4-type regions, which will become the drain and source regions of the P-channel transistor, are provided at regular intervals on the surface region of the N-type semiconductor substrate. 11 is the r-t oxide film of the N-channel transistor, 18 is the dirt oxide film of the P-channel transistor, and 19.20 is the source and drain/electrode f electrode of the N-channel transistor.
$A/)'j:y-)fi(D source and drain% &, 2s, 2s' is N channel and P channel/
The dirt electrodes 23 and 23' are commonly connected, and the connection point is connected to the input signal I.
The source electrode 19 of the N-channel transistor is connected to the supply voltage Vss, and the source electrode 19 of the N-channel transistor is connected to the supply terminal Vss,
The source electrode 21 of the channel transistor is connected to the other power supply voltage VDD supply terminal, and the drain electrode 2u of the N-channel transistor and the drain electrode 22 of the P-channel transistor are connected in common, and the common connection point is connected to the signal OUT output terminal. connected to.

In an inverter having such a configuration, due to its PN junction structure, bipolar transistors are generated isometrically as shown in the figure in addition to N-channel and P-channel transistors. That is, the PNP type region 15f is an emitter region, the substrate 11 is a space region, and the P-type region 12f is a collector region.
A PNP transistor 25 having an f emitter region, a substrate Il as a pace region, and a P-type region 12 as a collector region. N
NPN transistor 26 with type region 14t emitter region, P type region 12f base region and substrate 11 as collector region, N” type region tsft emitter region, P type region 12 as pace region and substrate 11 as collector region 27 occurs.

FIG. 4 is an equivalent circuit diagram showing the equivalently generated bipolar transistor as described above together with equivalent resistances.
.about.37 is the resistance in the P-type region 12. Now, in Fig. 4, when a voltage higher than VDD is applied to the output terminal or a current of an appropriate value is supplied, OUT~PN
P)U/Raster 25-Resistance 32~Resistance 28~Vl)D
Current flows through the path of PNP transistor 2.
5 becomes active. When the PNP transistor 25 becomes active, its collector current flows through the path from the 0UT-PNP transistor 25 to the resistor 36 to the resistor 37 to VSII. When the current flows, a voltage drop occurs across the resistor 37, and this voltage drop causes the NPN transistor 21 to become active. When the NPN transistor 27 becomes active and a collector current flows, a voltage drop occurs across the resistor 28, and this voltage drop across the resistor 28 causes the NPN transistor 24 to become active. In such a state, the collector currents of the PNP) transistor 24 and the N)'N transistor 27 supply pace current to each other, so even if the voltage at the output terminal or the supply current is removed, the V
The current continues to flow between DD I VB2 and finally the sources I11. Pole 19°21 was damaged.

[Purpose of the invention]

This invention was developed in consideration of the above-mentioned circumstances, and its purpose is to provide a method for manufacturing a semiconductor device that can prevent the occurrence of latte-up and is extremely resistant to breakage. Our goal is to provide the following.

[Summary of the Invention] That is, in this invention, in order to achieve the above-mentioned object, a first semicircular region having a low a and having the same conductivity type as that of the substrate is formed on a semiconductor substrate having a high temperature of 1 degree. A second semiconductor region (well region) of an opposite conductivity type is formed in this first semiconductor region. During the heat treatment during the formation of this second semiconductor region,
Due to the impurity diffused from the semiconductor substrate to the first semiconductor region, an impurity region [third
A semiconductor region] is formed, and this impurity region is used to form a substrate resistor to prevent latte-up.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 2, the main surface of an N4 type semiconductor substrate 41 with a specific resistance of about 0.05 Ωα is coated with a specific resistance of 0.1 by vapor phase growth or the like.
An N-type region (first semiconductor region) 42 of ~5Ωα is deposited. If such a substrate 41 is used to form N-channel and P-channel transistors in the same manner as in the prior art, a bridge as shown in FIG. 1 will be formed. That is, first, a P-type region (second
A half-fathom region) 43 is formed. After this, the P-type region 4
A pair of N4 type regions 44, 45, which serve as the source and drain regions of the N-channel transistor, are placed at a predetermined distance in the surface area of 420, while a pair of N4 type regions 44, 45 are placed at a predetermined distance in the surface area of the N-type region 420. A pair of P4 type regions 46 and 47 are formed to serve as the source and drain/regions.

After this, each dirt oxidation layer A48.49 of the N-channel and P-channel transistors is formed, and both the source and drain electrodes of the N-channel transistor and the source and drain electrodes of the 51% P-channel transistor are formed.
Both drain electrodes sz, ss, dirt electrodes 54*55f of both N-channel and P-channel transistors are formed, and the drain electrodes 51.53 and the dirt electrodes 54.55 are connected and wired to form 0MO3.
The inverter can be configured.

By the way, when forming the P-type region 43 by diffusion, for example, 1
Since the high temperature state is maintained for a long time, such as 200u and 15 to 20 hours, impurities in the substrate 41 are diffused into the N-type region 42 in the portion in contact with the substrate 41. As a result, the first
As shown in the figure, the portion of the N-type region 42 in contact with the P-type region 43 (the portion indicated by both the diagonal line downward to the right and the diagonal line downward to the left in the figure) is converted to N4 and becomes an N4-type region 56.

As a result, the equivalent resistance 2 in the equivalent circuit diagram shown in FIG.
The value of 8 is reduced to ρ〆/ρN- compared to the conventional case. where ρN" is the specific resistance of the N4 type region 56, ρN- is the specific resistance of the N type region 42, and ρN4 has a value equal to the specific resistance of the substrate 41, that is, 0.05Ωα. As a result, the above resistance The value of 28 is reduced to 1/2 to 1/100 of the conventional value. Therefore, in such a configuration, a voltage higher than VDD is applied to the output terminal as in the conventional case, or a current of an appropriate value is applied. Even if it is supplied, the value of the equivalent resistance 28 of J is small, so that a sufficient voltage drop does not occur to switch the PNP transistor 24 shown in FIG. The equivalent resistance 28 in the region 56
This is because the value of 32 is extremely small compared to the conventional value.

Latch-up phenomenon becomes less likely to occur. For example, when this invention is applied to an inverter, VDD= +20V,
Vss = OV O', output ta is 150m
It has been confirmed that the latch-up phenomenon does not occur even if the flow exceeds A.

Note that the present invention is not limited to the above-mentioned embodiment, and for example, although the above embodiment describes the case of an inverter as CMO8, it is not limited to this, and can also be applied to Nand Dart etc., and furthermore, using these gate circuits. Of course, it can also be applied to LSIs.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to prevent the latch-up phenomenon from occurring, thereby providing a method of manufacturing a semiconductor device that is extremely resistant to destruction.

[Brief explanation of drawings]

1 and 2 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a conventional CMO8 inverter, and FIG.
The figure is C in Figure 3 above? FIG. 2 is an equivalent circuit diagram of a vt OS inverter. 41...N'' type semiconductor substrate, 42...N type region (
il semiconductor region), 43...P type region (second semiconductor region), 44.45...N4 type region (source part, drain part), 46.47...P1 type region [source part, drain part] ], 56...N4 region (third semiconductor region). Applicant's agent: yP Physician Takehiko Suzue (Figure 1, Figure 2, Figure 3, Figure 41 V:):) Showa Year, Month, Day

Claims (1)

[Claims] forming a low concentration first semiconductor region of the same conductivity type on a high concentration semiconductor substrate of one conductivity type; forming a second semiconductor region of the opposite conductivity type in the surface region of the first semiconductor region; forming a source part and a drain part in respective surface regions of the first and second semiconductor regions, and during heat treatment for forming the second semiconductor regions, from the semiconductor substrate to the first semiconductor regions. A semiconductor device characterized in that a third semiconductor region of one conductivity type and having a higher concentration than the first semiconductor region is formed between the semiconductor substrate and the first and second semiconductor regions by impurities diffused into the semiconductor substrate. Production method.