JPH0743414B2 - Semiconductor integrated circuit with battery life detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a configuration of a semiconductor integrated circuit having a battery life detection circuit incorporated therein, and is particularly effective in improving the temperature characteristics of the battery life detection circuit. Technology.

[Conventional technology]

In many electronic devices such as an electronic timepiece that uses a battery as a power source, a circuit for monitoring the battery voltage of the battery to determine the degree of consumption of the battery, that is, a battery life detection circuit is built-in.

The battery life detection circuit is configured so that the detected power supply voltage is divided by a series connection of a resistor whose resistance value depends on the voltage and a resistor which does not depend on the voltage, and the voltage at the connection point between these resistors is input to a voltage comparator. It is known that voltage comparators output "high" or "low".

FIG. 2 is a circuit diagram illustrating a conventional battery life detection circuit.

The configuration of the conventional battery life detection circuit shown in FIG. 2 has an n-channel MOS resistor 12 as a resistor whose resistance value depends on the voltage.
And the resistance 11 whose resistance value does not depend on the voltage divides the detected power supply voltage, and the dividing point is connected to the gate of the inverter constituted by the p-channel MOS transistor 13 and the n-channel MOS transistor 14. The inverter composed of the p-channel MOS transistor 13 and the n-channel MOS transistor 14 serves as a voltage comparator. In the configuration shown in FIG. 2, the n-channel MOS resistor 12 is used as the voltage-dependent resistor, but a p-channel MOS resistor may be used without any problem. However, in that case, p
It goes without saying that the channel MOS resistance is set to the VDD side of the power supply and the voltage-independent resistor 11 is set to the Vss side of the power supply.

Since the battery life detection circuit shown in FIG. 2 is extremely simple, it is very excellent as a circuit to be mounted on a semiconductor integrated circuit. It has a fatal defect that the life detection voltage has temperature dependence. Such temperature dependence is caused by the difference in temperature characteristics between the n-channel MOS resistor 12 and the resistor 11, and cannot be avoided as long as the conventional semiconductor integrated circuit manufacturing method is used. This is because the voltage-independent resistance that can be formed by using the conventional semiconductor integrated circuit manufacturing method includes well diffusion resistance with a temperature coefficient of about 0.7% / deg and temperature coefficient of about 0.18% / deg.
deg source / drain diffusion resistance or temperature coefficient
It is limited to polycrystalline silicon resistors of 0.1% / deg or less, and there is a problem that there is nothing that matches the temperature coefficient of MOS resistors of 0.3% / deg.

Therefore, in order to solve such a problem, for example, JP-A-51-058378 or JP-A-57-019676 has been proposed.

Representative examples of the temperature compensation means in these reports are described below. FIG. 4 directly cites the drawing described in JP-A-57-019676.
In FIG. 4, a p-channel MOS resistor 32, a resistor 33, and a resistor R are connected in series to divide the power supply voltage so that the p-channel MO
Connect the point A, which is the connection point between the S resistor 32 and the resistor 33, to the p-channel M
It is connected to the point B of the gate of the inverter composed of the OS transistor and the n-channel MOS transistor, and the output of this inverter is connected to the gate of the latter-stage inverter. The latter-stage inverter is provided as a so-called waveform shaping circuit for clarifying whether the level of the output 0 point is “high” or “low”, and is combined with the former-stage inverter. Form a voltage comparator. The temperature compensating means of the battery life detecting circuit in FIG. 4 is characterized in that a temperature-dependent resistor 33 and a temperature-independent resistor R are connected in series to use the temperature of the p-channel MOS resistor 32 as a whole. A resistance having a temperature characteristic equal to that of the characteristic is formed to eliminate the temperature change of the voltage at the point A. That is, in order to obtain a resistance having the same temperature characteristic as the MOS resistance, a characteristic is that two types of resistance, that is, the resistance 33 having temperature dependence and the resistance R having no temperature dependence are combined. In order to match the temperature coefficient of the MOS resistor 32 as a whole by the series connection of the resistor R and the resistor 33, which do not depend on the temperature, the temperature coefficient of the resistor 33 is necessarily the same as that of the MOS resistor 3.
It must be greater than the temperature coefficient of 2. MOS resistor 32
Has a temperature coefficient of about 0.3% / deg, which is 0.3% / de of the resistance that can be built into a semiconductor integrated circuit by a normal manufacturing method.
Resistance with a temperature coefficient greater than g has a temperature coefficient of 0.7% / deg.
If the resistor 33 is constituted by a well diffused resistor, the temperature change of the voltage at the point A can be eliminated by adjusting the ratio of the resistance values of the resistor 33 and the resistor R. . In the prior art, it is impossible to eliminate the temperature change of the voltage at the point A unless such two types of resistors that do not depend on the voltage are combined. Such a restriction remains the combination of two types of resistors that do not depend on voltage, regardless of whether the resistor R that does not depend on temperature is external or built in a semiconductor integrated circuit.

[Problems to be solved by the invention]

In the battery life detection circuit shown in FIG. 4, the resistance configuration is complicated for temperature compensation, and the manufacturing process is performed to form a temperature-dependent resistance and a temperature-independent resistance. The addition is required, and the simplicity of the battery life detection circuit shown in FIG. 2 is lost. Therefore, there is a problem that designing becomes difficult when the battery life detection circuit is mounted on the semiconductor integrated circuit, resulting in a decrease in yield and an increase in cost.

An object of the present invention is to provide a semiconductor integrated circuit equipped with a battery life detection circuit capable of temperature compensation while completely maintaining circuit simplicity.

[Means for solving problems]

In order to achieve the above object, the semiconductor integrated circuit with a battery life detection circuit according to the present invention has the following configuration.

That is, all the circuit components that make up the battery life detection circuit are built into the semiconductor integrated circuit, and the battery life detection circuit connects a MOS resistance and a diffusion resistance in series between the detected power supply voltage. The voltage at the connection point with and is input to a voltage comparator composed of a p-channel transistor and an n-channel transistor, and this diffusion resistor has a surface impurity concentration of 1 × 10 ¹⁸ cm ^-3 or more The feature is that battery life detection without temperature dependence is performed because the MOS resistance to be connected and the temperature coefficient are almost the same.

Furthermore, in order to prevent an increase in the area occupied by the battery life detection circuit in the semiconductor integrated circuit, the semiconductor circuit with the battery life detection circuit according to the present invention has the following configuration.

That is, the diffusion resistor connected in series with the MOS resistor has a diffusion depth of 1 μm or less.

[Action]

In the so-called normal temperature range near room temperature, the temperature coefficient of diffusion resistance is determined by the impurity concentration, and the resistance per unit width and unit length of the diffusion resistance, that is, the sheet resistance is determined by the impurity concentration and the diffusion depth. Temperature coefficient of MOS resistance is about 0.3% / d
eg, and in order to make the temperature coefficient of diffusion resistance equal or close to this, the surface impurity concentration of diffusion resistance is 1 ×
Must be at least 10 ¹⁸ cm ^-3 .

Also, when the battery life detection circuit is operating, current flows through the MOS resistance and diffusion resistance.Therefore, in order to prevent the battery life detection circuit from applying an excessive load to the battery, these resistance values are usually several hundred kΩ. Or higher. If a diffusion resistance having such a value is to be formed with a sheet resistance of 1 to 2 kΩ / □ or less, the occupied area in the semiconductor integrated circuit increases, which is impractical. for that reason,
The sheet resistance of the diffusion resistor connected in series with the MOS resistor is set to 1 to 2 kΩ / □ or more. 1 to 2 kΩ / in diffusion resistance with surface impurity concentration of 1 × 10 ¹⁸ cm ^-3 or more
□ In order to realize the above sheet resistance, the diffusion depth must be 1 μm or less.

Therefore, the surface impurity concentration of the diffusion resistance should be 1 × 10 ¹⁸ cm ^-3.
By the above, the temperature coefficient of the diffusion resistance can be made almost equal to the temperature coefficient of the MOS resistance, and the temperature compensation of the battery life detection circuit can be performed with the simple circuit configuration of one MOS resistance and one diffusion resistance. Can be achieved. Further, by controlling the diffusion depth to 1 μm or less at the same time, a diffusion resistance having a temperature coefficient substantially equal to that of the MOS resistance can be mounted in a semiconductor integrated circuit in a practical size.

By the way, as described above, in the conventional method for manufacturing a semiconductor integrated circuit, the diffusion resistance having the temperature coefficient of 0.3% / deg as in the present invention cannot be formed. Therefore, in the present invention, a step of ion-implanting an impurity for forming a diffusion resistance having a temperature coefficient equal to that of a MOS resistance is added just before the final high temperature step in the manufacturing process of a semiconductor integrated circuit. × 10 ¹⁸ cm
A surface impurity concentration of ^-3 or more and a diffusion depth of 1 μm or less are simultaneously achieved.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a circuit diagram of a battery life detecting circuit for explaining an embodiment of the present invention.

The configuration of the battery life detection circuit of the present invention shown in FIG. 2 is an n-channel MOS resistor 12 as a resistor whose resistance value depends on voltage.
And a resistor 11 whose resistance value does not depend on the voltage are connected in series and are arranged between the detected power supply voltages. n-channel MOS resistor 1
The detected power supply voltage is divided by 2 and the resistance 11 whose resistance value does not depend on the voltage, and the division point is connected to the gate of the inverter formed by the p-channel MOS transistor 13 and the n-channel MOS transistor 14. The inverter composed of the p-channel MOS transistor 13 and the n-channel MOS transistor 14 serves as a voltage comparator. The resistance 11 whose resistance value does not depend on voltage is a diffusion resistance according to the present invention, and has a surface impurity concentration of about 3 × 10 ¹⁸ cm 2.
^-3 , the temperature coefficient is made substantially equal to the temperature coefficient of the n-channel MOS resistor 12. Also, its diffusion depth is about 0.
The sheet resistance is controlled to 25 μm and the sheet resistance is set to about 5 kΩ / □.

Next, a manufacturing method for realizing the configuration of the semiconductor integrated circuit with the battery life detection circuit according to the present invention will be described as a reference example. 5 to 14 show the steps of separating the semiconductor substrate surface into a first conductivity type region and a second conductivity type region in the method of manufacturing a semiconductor integrated circuit with a battery life detection circuit according to the present invention. The process up to the step of forming the diffusion resistance is shown, and steps before and after the step of forming the metal wiring are omitted.

As shown in FIG. 5, an n-type semiconductor substrate of the first conductivity type
A p-well 43 which is a second conductivity type region is selectively formed on the surface of 41.

Next, as shown in FIG. 6, in the respective regions of the n-type semiconductor substrate 41 and the p well 43, an element region 45 and an element isolation region are formed.
47 and are selectively formed.

Next, as shown in FIG. 7, a gate oxide film 49 is formed in the element region 45 by thermal oxidation.

Next, as shown in FIG. 8, a gate electrode film 51 is formed on the entire surface.

Next, as shown in FIG. 9, the gate electrode film 51 is selectively removed using the photoresist 44 as a mask to form the gate electrode 53 of the MOS transistor, and the n-type semiconductor substrate is formed.
The entire gate oxide film 49 in one element region 45 on the 41 side is exposed to form a diffusion resistance region 55.

Next, the photoresist 44 is removed, and as shown in FIG.
Using the photoresist 44 that opens the element region 45 of the MOS transistor in the p-well 43 as a mask, high-concentration phosphorus of about 3 × 10 ¹⁵ atoms / cm ² which is an n-type impurity is ion-implanted.

Next, the photoresist 44 is removed, and as shown in FIG.
Element region 45 of the MOS transistor on the n-type semiconductor substrate 41 side
And a high concentration of boron of about 3 × 10 ¹⁵ atoms / cm ^2, which is a p-type impurity, is ion-implanted using the photoresist 44 that opens at both ends of the diffusion resistance region 55 and the junction region.

Next, the photoresist 44 is removed, and as shown in FIG.
Boron with a low concentration of about 1 × 10 ¹³ atoms / cm ² is ion-implanted on the entire surface to introduce a p-type impurity into the diffusion resistance region 55.

Next, as shown in FIG. 13, a silicon oxide film 57 is deposited on the entire surface by chemical vapor deposition.

Next, as shown in FIG. 14, heat treatment is performed at 950 ° C. for about 30 minutes to diffuse and activate the ion-implanted impurities, and together with the source / drain of the MOS transistor,
The diffusion resistance region 59 and the junction regions at both ends of the diffusion resistance region 59 are formed. The subsequent formation of metal wiring and the like are exactly the same as in the method of manufacturing a semiconductor integrated circuit without the diffused resistor according to the present invention, and a description thereof will be omitted.

As is clear from the above description of the manufacturing method, the step of forming the diffusion resistance 59 according to the present invention is basically performed by ionizing boron of about 1 × 10 ¹³ atoms / cm ² shown in FIG. Only the implantation step is performed, and the increase in manufacturing cost is almost negligible as compared with the semiconductor integrated circuit in which the diffused resistor 59 is not mounted. The reason why the increase in manufacturing cost can be suppressed in this way is as follows.

That is, since the impurity concentration of the diffusion resistor 59 according to the present invention is lower than the impurity concentration of the source / drain of the MOS transistor by two digits or more, when the impurity of low concentration is introduced into the diffusion resistance region 55, the low concentration of impurity is introduced. Even if the impurities are ion-implanted into the source / drain regions of the MOS transistor, they have no influence on the electrical characteristics of the MOS transistor. Therefore, as shown in FIG. 12, when introducing a low-concentration impurity into the diffusion resistance region 55, ion implantation may be performed on the entire surface of the semiconductor substrate, and a high-cost process such as a photolithography process is not required. This is because. Also,
No special heat treatment step is required to diffuse and activate the impurities to be ion-implanted into the diffusion resistance region 55. For diffusion and activation of the impurities to be ion-implanted into the source / drain regions of the MOS transistor, The fact that it can be processed at the same time as the heat treatment also contributes to the suppression of an increase in manufacturing cost.

By the steps shown in FIG. 5 to FIG.
Has a surface impurity concentration of about 3 × 10 ¹⁸ cm ⁻³ and a diffusion depth of about 0.25 μm.

Although the present invention has been specifically described based on the embodiments as described above, the present invention is not limited to the above embodiments,
It goes without saying that various modifications can be made without departing from the spirit of the invention. For example, in FIG. 2, the n-channel MOS resistor 12 is used as the voltage-dependent resistor, but a p-channel MOS resistor may be used without any problem. However, in that case, set the p-channel MOS resistance to VDD of the power supply.
It goes without saying that the diffusion resistance 11 is connected to the Vss side of the power supply.

In the description of the manufacturing method shown in FIGS. 5 to 14, n
The p-type semiconductor substrate 41 is the first conductivity type region and the p-well 43 is the second conductivity type region.
The conductivity type region may be used and the n well may be used as the second conductivity type region. In that case, it goes without saying that the diffusion resistance 59 is an n-type diffusion resistance in which phosphorus is ion-implanted. Further, there is no problem in changing the semiconductor substrate side to the second conductivity type region and the well to the first conductivity type region.

Further, in the embodiment shown in FIGS. 5 to 14,
The process of ion-implanting impurities into the diffusion resistance region 55 is
Although it is performed after the step of ion-implanting the impurities into the source / drain of the transistor, the order may be changed without any problem. No matter which order ion implantation is performed, heat treatment for diffusion and activation of the impurities is performed.
By forming the diffused resistor with a temperature coefficient almost equal to that of the MOS resistor, without increasing the manufacturing cost, by simultaneously performing the heat treatment for diffusing and activating the impurities in the source / drain of the MOS transistor. You can

The diffusion resistance 59 represents one diffusion resistance forming the battery life detection circuit, and the diffusion resistance 59 can be used in a region other than the battery life detection circuit. In addition, since the ion implantation process added to form the diffusion resistance 59 does not prevent the formation of resistors such as well diffusion resistance that can be formed by conventional techniques, various types of resistors that can be used by the conventional technique are used in the present invention. Can also be used.

Next, the temperature change rate of the diffusion resistance according to the present invention will be described. FIG. 1 shows the temperature change rate 21 of the diffusion resistance and the temperature change rate 22 of the n-channel MOS resistance in one embodiment of the present invention.
FIG. 5 is a graph showing the change in resistance value at each temperature with respect to the resistance value at 20 ° C.
In this example, the surface impurity concentration of the diffusion resistance is about 3 × 10 ¹⁸ cm ⁻³ , the diffusion depth is about 0.25 μm, and the sheet resistance is about 5 kΩ / □. As is clear from FIG. 2, the temperature change rate 21 of the diffusion resistance is almost equal to the temperature change rate 22 of the n-channel MOS resistance, which is about 0.3% / deg.

Next, the temperature compensation characteristics of the battery life detection circuit according to the present invention will be described. FIG. 3 is a graph showing the temperature change of the life detection voltage of the battery life detection circuit according to the present invention. The circuit configuration of the battery life detection circuit is as shown in FIG.
The resistor 11 is a diffusion resistor having a surface impurity concentration of about 3 × 10 ¹⁸ cm ⁻³ and a diffusion depth of about 0.25 μm. As is clear from FIG. 3, the life detection voltage is almost constant in the temperature range of -20 ° C to + 80 ° C, plus or minus 6 m.
It is within V. It is clear that the present invention can achieve almost complete temperature compensation of the battery life detection circuit.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, it is possible to form a diffused resistor having a temperature coefficient substantially equal to that of the MOS resistor, and use only one diffused resistor and one MOS resistor in series. As a result, it is possible to provide a semiconductor integrated circuit equipped with a battery life detection circuit that does not depend on temperature while completely maintaining the simplicity of the circuit, and the effect is great.

[Brief description of drawings]

FIG. 1 is a graph of temperature change rates of diffusion resistance and MOS resistance used in the battery life detection circuit of the present invention. FIG. 2 is a circuit diagram of a battery life detecting circuit for explaining a conventional example and an embodiment of the present invention. FIG. 3 is a graph showing the temperature characteristic of the life detection voltage of the battery life detection circuit of the present invention.
FIG. 4 is a circuit diagram of a battery life detection circuit in a conventional example. 5 to 14 are sectional views showing a reference example of a manufacturing method for realizing the configuration of the semiconductor integrated circuit with the battery life detection circuit according to the present invention. 11 ... Resistor having no voltage dependence 12 ... n-channel MOS resistance, 13 ... p-channel MOS transistor, 14 ... n-channel MOS transistor, 21 ... temperature change rate of diffusion resistance according to the present invention, 22 ... n Channel MO
Rate of temperature change of S resistance.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/822 27/04

Claims (2)

[Claims] 1. A semiconductor integrated circuit in which all of the circuit components constituting the battery life detection circuit are built in, and the battery life detection circuit comprises a MOS resistance and a diffusion resistance connected in series between the detected power supply voltages. The voltage at the connection point between the diffusion resistor and the diffused resistor is input to a voltage comparator composed of a p-channel transistor and an n-channel transistor, and the diffused resistor has a surface impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more. , A semiconductor integrated circuit with a battery life detection circuit, which detects battery life without temperature dependence by making the temperature coefficient of the MOS resistance connected in series approximately match. 2. A semiconductor integrated circuit with a battery life detecting circuit according to claim 1, wherein the diffusion resistor connected in series with the MOS resistor has a diffusion depth of 1 μm or less.