JPH07111311A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent inversion of the surface layer adjacent to a diffusion resistance region, and also to prevent a leakage current from a diffusion resistor by a method wherein the part, excluding the part directly above the diffusion region of an insulating film, is covered by a low resistance layer, and the low resistance layer is fixed to the prescribed potential. CONSTITUTION:A thin oxide film 21 is formed on the part where the resistor of an N-type silicon substrate 1 is formed, a thick oxide film 22 is formed on the circumferential part of the oxide film 21, a polycrystalline silicon layer 7 is deposited thereon, and an aperture part 8 is provided on the polycrystalline silicon layer 7 of the part where a diffusion resistance region is formed. When boronic ions are implated from above the aperture part, a P<+> diffusion resistance region 3 is generated by heat treatment, and at the same time, the resistance of the polycrystalline silicon layer 7 becomes low. A contact hole 41 is provided on the oxide film 21 on the P<+> region, an Al wiring is brought into contact, a wiring 6 is brought into contact with the connection part 61 of the polycrystalline silicon layer 7 and fixed to power source potential which is the highest potential in this case. As a result, the surface layer of the substrate 1 is not inverted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a resistor formed as a circuit element of an integrated circuit by diffusing impurities in a semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As resistances of circuit elements of an integrated circuit, it is general to use regions of different conductivity type formed by diffusing impurities in a semiconductor substrate. To increase the resistance value,
The region of this diffusion resistance is bent and lengthened.
Figures 2 (a) and 2 (b) show such diffusion resistance.
FIG. 4B is a sectional view taken along line BB of FIG. That is, the U-shaped p ⁺ diffusion resistance region 3 is formed by ion implantation diffusion using the oxide film 2 on the surface of the n-type silicon substrate 1 as a mask, and the wiring 4 is brought into contact with the opening 41 of the oxide film 2. However, when the surface layer of the n-type substrate 1 is inverted to p-type by the electric field generated by the wiring on the surface of the substrate, it is transferred to another element integrated between the opposing portions of the diffusion resistance region 3 or outside the diffusion resistance region. Leakage current occurs, and the resistance value of the resistor as a circuit element fluctuates. Therefore, as shown in the figure, an n ⁺ region 5 that enters the middle of the p ⁺ region 3 or surrounds the periphery is formed by ion implantation and diffusion, and the same potential as that of the substrate ion implantation method is obtained by the wiring 6 contacting at the contact hole 61. in this case,
It is fixed to the power supply voltage to prevent the surface layer from inverting.

[0003]

However, in order to prevent the formation of the inversion layer by the method as shown in FIG. 2, the diffusion regions 5 having different conductivity types must be formed in the middle and the periphery of the diffusion resistance regions 3 facing each other. However, this region 5 is the diffusion resistance region 3 on both sides.
Since it is necessary to keep a distance approximately equal to the width of the region 5, the area required as a whole becomes very large.
It has been a big problem to increase the degree of integration of C.

An object of the present invention is to solve the above-mentioned problems, provide a semiconductor device in which the surface layer adjacent to the diffusion resistance region of the semiconductor substrate is prevented from being inverted, and a current does not leak from the diffusion resistance, and a manufacturing method thereof. Especially.

[0005]

To achieve the above object, the present invention has a diffusion resistance region of a second conductivity type selectively formed in a surface layer of a first conductivity type layer of a semiconductor substrate. In a semiconductor device, a surface of a region including a diffusion resistance region of a semiconductor substrate is covered with an insulating film, and a portion of the insulation film except a portion right above the diffusion resistance region is covered with a low resistance layer, and the low resistance layer is provided with a predetermined thickness. It can be fixed at the potential of.
It is effective that the low resistance layer is made of polycrystalline silicon containing impurities. Further, such a semiconductor device manufacturing method is such that a surface of a first conductivity type layer of a semiconductor substrate is covered with a polycrystalline silicon layer via an insulating film, and then a portion having a predetermined shape of the polycrystalline silicon layer is selected. Then, impurity ions are implanted into the entire surface, and a heat treatment is performed to form a second-conductivity-type diffusion resistance region in the surface layer of the first-conductivity-type layer exposed in the portion having the predetermined shape, and at the same time, to increase the amount of impurities on the surface. The resistance of the crystalline silicon layer shall be lowered.

[0006]

[Function] A low resistance layer is provided on the surface of the first conductivity type layer except right above the diffusion resistance region of the second conductivity type through an insulating film and fixed to a predetermined potential, for example, the same potential as the first conductivity type layer. As a result, the surface layer of the first conductivity type layer is not inverted, and it is possible to prevent current leakage between the opposing resistance regions or between the resistance region and the external element. The distance between conductive layers is normal MOSF
Since the minimum width with which ET can be turned off is sufficient, the distance between the opposing resistance regions can be narrowed. Moreover, if the conductive layer is made of polycrystalline silicon, it is possible to dope the polycrystalline silicon at the same time as the ion implantation for forming the diffusion resistance region to reduce the resistance, and thus the increase in manufacturing cost is minimized. Can be suppressed to. Further, such a semiconductor device manufacturing method is such that a surface of a first conductivity type layer of a semiconductor substrate is covered with a polycrystalline silicon layer via an insulating film, and then a portion having a predetermined shape of the polycrystalline silicon layer is selected. Then, impurity ions are implanted into the entire surface, and a heat treatment is performed to form a second-conductivity-type diffusion resistance region in the surface layer of the first-conductivity-type layer exposed in the portion having the predetermined shape, and at the same time, to increase the amount of impurities on the surface. The resistance of the crystalline silicon layer shall be lowered.

[0007]

1 (a) and 1 (b) show a part of an IC according to an embodiment of the present invention, the same parts as those in FIG. 2 are designated by the same reference numerals, and FIG. It is the sectional view on the AA line of FIG. This IC was manufactured as follows. A thin oxide film 21 is formed in a portion of the n-type silicon substrate 1 where a resistance is formed, and a thick oxide film 22 is formed in a peripheral portion thereof, and a polycrystalline silicon layer 7 is deposited thereon to form a diffusion resistance region with a width w. = 2 μm, an opening 8 is opened in the polycrystalline silicon layer 7. When boron is ion-implanted from above, boron ions are implanted into the n layer 1 through the thin oxide film 21 and, where the polycrystalline silicon layer 7 remains, that layer. Due to the boron introduced into the surface layer of the n-type substrate 1, the p ⁺ diffusion resistance region 3 is generated by the heat treatment, and at the same time, the polycrystalline silicon layer 7 has a low resistance. Oxide film 21 on p ⁺ region 7
A contact hole 41 is opened in and the AL wiring 4 is contacted. The wiring 6 is also brought into contact with the connection portion 61 of the polycrystalline silicon layer 7 and fixed to the power supply voltage which is the highest potential in this case. As a result, since the low-resistance polycrystalline silicon layer 7 exists between the diffusion resistance regions 3 and above the peripheral region and is fixed at the highest potential, the surface layer of the n-substrate 1 immediately below it is inverted. Never. Therefore, no current leakage occurs between the diffusion resistance regions or in the path from the diffusion resistance region to another element. Further, since the surface is covered with the oxide film 21 and insulated, no leakage occurs between the polycrystalline silicon layers 7.

[0008]

According to the present invention, the inversion of the surface layer between the diffusion resistance regions or between the surrounding other elements is suppressed by the insulating film between the resistance regions and immediately above the surrounding region. It was prevented by providing a resistance layer and fixing it to a predetermined potential such as a power supply voltage. Therefore, as compared with the conventional case where regions of different conductivity type are provided in the surface layer between the resistance regions or with other surrounding elements and fixed at a predetermined potential, the distance between the resistance regions bent and opposed to each other is increased. Can be about 1/3. As a result, the area occupied by the entire resistance becomes extremely small, which is suitable for increasing the degree of integration of the IC. In addition, if a polycrystalline silicon layer that is doped at the same time as the formation of the resistance region is used as the low resistance layer, the number of steps can be reduced, and the patterning shape of the polycrystalline silicon layer that can be used as an ion implantation mask can be reduced. A diffused resistor having an arbitrary resistance value can be easily formed only by changing

[Brief description of drawings]

FIG. 1 shows a diffusion resistance portion of an IC according to an embodiment of the present invention.
(a) is a plan view, (b) is a sectional view taken along the line AA of (a).

FIG. 2A is a plan view and FIG. 2B is a sectional view taken along line BB of FIG. 2A showing a diffusion resistance portion of a conventional IC.

[Explanation of symbols]

1 n Silicon Substrate 21 Oxide Film 3 p ⁺ Diffusion Resistance Region 4 Wiring 41 Contact Hole 6 Wiring 61 Connection 7 Polycrystalline Silicon Layer 8 Polycrystalline Silicon Layer Opening

Claims (3)

[Claims] 1. A semiconductor substrate having a diffusion resistance region of a second conductivity type selectively formed in a surface layer of a first conductivity type layer of a semiconductor substrate, wherein a surface of a region including the diffusion resistance region of the semiconductor substrate is insulated. A semiconductor device, which is covered with a film, and a portion of the insulating film other than just above a diffusion resistance region is covered with a low resistance layer, and the low resistance layer can be fixed to a predetermined potential. 2. The semiconductor device according to claim 1, wherein the low resistance layer is made of polycrystalline silicon containing impurities. 3. The surface of a first conductivity type layer of a semiconductor substrate is covered with a polycrystalline silicon layer with an insulating film interposed therebetween, and then a predetermined shaped portion of the polycrystalline silicon layer is selectively removed. Impurity ions are implanted into the surface of the first conductivity type layer by heat treatment to form a second conductivity type diffusion resistance region in the surface layer of the first conductivity type layer, and the resistance of the polycrystalline silicon layer on the surface is reduced. The method for manufacturing a semiconductor device according to claim 2, wherein