JPS6359210A - Rc active filter - Google Patents

Rc active filter

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Publication number
JPS6359210A
JPS6359210A JP20311086A JP20311086A JPS6359210A JP S6359210 A JPS6359210 A JP S6359210A JP 20311086 A JP20311086 A JP 20311086A JP 20311086 A JP20311086 A JP 20311086A JP S6359210 A JPS6359210 A JP S6359210A
Authority
JP
Japan
Prior art keywords
resistor
connection point
mos
channel mos
whose
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20311086A
Other languages
Japanese (ja)
Inventor
Tomoaki Masuda
増田 智章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20311086A priority Critical patent/JPS6359210A/en
Publication of JPS6359210A publication Critical patent/JPS6359210A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the efficiency of circuit integration by connecting a 1st MOS resistor and a 1st resistor in series and connecting the 2nd resistor in series with 2nd MOS resistor. CONSTITUTION:The resistors 16, 17 are connected and a series connection resistor comprising a MOS resistor and a diffusion resistor is used as the resistor being the component of the RC active filter. Let the resistance of the resistor 16 be R1, the resistance of the MOS resistor 12 be R2, then a voltage across the MOS resistor 12 is a multiple of R2/(R1+R2) in comparison with the constitution by the MOS resistor 12 only. That is, the distortion by the MOS resistor 12 is decreased. This is similar as to the MOS resistor 15.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、RCアクティブフィルタに関し、特に、半導
体集積回路におけるRCアクティブフィルタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an RC active filter, and particularly to an RC active filter in a semiconductor integrated circuit.

〔概要〕〔overview〕

本発明は、演算増幅器と正帰還ループを形成する抵抗と
コンデンサとを含むサレン・キー型のRCアクティブフ
ィルタにおいて、 上記抵抗として、PチャネルMOS)ランジスタとNチ
ャネルMOS)ランジスタの並列接続回路からなるMO
S抵抗と拡散抵抗との直列接続回路を用いることにより
、 歪みを小さくし、かつ面積を小さくでき集積化の効率を
上げるようにしたものである。
The present invention provides a Sallen-Key type RC active filter that includes an operational amplifier, a resistor, and a capacitor forming a positive feedback loop, in which the resistor is composed of a parallel connection circuit of a P-channel MOS transistor and an N-channel MOS transistor. M.O.
By using a series connection circuit of an S resistor and a diffused resistor, distortion can be reduced, the area can be reduced, and the efficiency of integration can be increased.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路において、帯域制限を行うRCア
クティブフィルタとしては、−例として第2図に示すサ
レン・キー(Sallen−Key)型の2次の低域通
過フィルタがある。本従来例は、一端を入力端子1に接
続し他端を接続点3に接続した抵抗2と、一端を接続点
3に接続し他端を接続点6に接続した抵抗4と、一端を
接続点6に接続し他端を接地電位に接続したコンデンサ
5と、正相人を接続点6に接続し逆相入力および出力を
出力端子9に接続した演算増幅器8と、一端を接続点3
に接続し他端を出力端子9に接続したコンデンサ7とを
含んでいる。そして抵抗2および4としては拡散抵抗を
用いている。
Conventionally, as an RC active filter for band limiting in a semiconductor integrated circuit, there is, for example, a Sallen-Key type second-order low-pass filter shown in FIG. In this conventional example, one end is connected to a resistor 2 with one end connected to the input terminal 1 and the other end connected to the connection point 3, and a resistor 4 whose one end is connected to the connection point 3 and the other end is connected to the connection point 6. a capacitor 5 connected to point 6 and the other end connected to ground potential, an operational amplifier 8 whose positive phase input is connected to connection point 6 and whose negative phase input and output are connected to output terminal 9, and one end connected to connection point 3.
and a capacitor 7 whose other end is connected to the output terminal 9. As the resistors 2 and 4, diffused resistors are used.

第3図は、従来のRCアクティブフィルタの他の一例を
示す回路図である。本従来例は第1図に示す回路で抵抗
2および4として拡散抵抗の代わりにMOS抵抗12お
よび15を用いたものである。
FIG. 3 is a circuit diagram showing another example of a conventional RC active filter. This conventional example uses MOS resistors 12 and 15 instead of diffused resistors as resistors 2 and 4 in the circuit shown in FIG.

ここで、MOS抵抗12はNチャネルMOSトランジス
タ10とPチャネルMOSトランジスタ11との並列接
続回路からなり、MOS抵抗15はNチャネルMOS)
ランジスタ13とPチャネルMOS)ランジスタ14と
の並列接続回路からなっている。
Here, the MOS resistor 12 consists of a parallel connection circuit of an N-channel MOS transistor 10 and a P-channel MOS transistor 11, and the MOS resistor 15 is an N-channel MOS).
It consists of a circuit connected in parallel with a transistor 13 and a P-channel MOS transistor 14.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の従来のRCアクティブフィルタでは、抵抗として
拡散抵抗やMOS抵抗を用いているが、抵抗として拡散
抵抗を用いる場合には、遮断周波数が低い周波数の場合
のように高抵抗が必要とされる場合、抵抗の占める面積
が抵抗値に比例して広がり、集積化の効率が低下する欠
点がある。
In the conventional RC active filter described above, a diffused resistor or MOS resistor is used as a resistor, but when a diffused resistor is used as a resistor, a high resistance is required, such as when the cut-off frequency is low. However, the area occupied by the resistor increases in proportion to the resistance value, resulting in a reduction in integration efficiency.

一方、MOS抵抗を用いた場合にはこの欠点を解消する
ことができるが、MOS抵抗は、その対抗値にソース・
ドレイン電圧依存性をもつため信号が歪む欠点がある。
On the other hand, this drawback can be overcome by using a MOS resistor;
There is a drawback that the signal is distorted because it has drain voltage dependence.

次にその理由を説明する。Next, the reason will be explained.

MOSトランジスタの電圧と電流の関係式が入力端子1
および接続点3の電圧を■、およびv2とし、Nチャネ
ルMOS)ランジスタ10のゲートに正電源電圧VDが
加えられ、PチャネルMOSトランジスタ11のゲート
電圧に負電源電圧−■。
The relational expression between the voltage and current of the MOS transistor is input terminal 1.
And the voltages at the connection point 3 are assumed to be ■ and v2, a positive power supply voltage VD is applied to the gate of the N-channel MOS transistor 10, and a negative power supply voltage -■ is applied to the gate voltage of the P-channel MOS transistor 11.

が印加された場合、入力端子1と接続点3間に流れる電
流Iは、 3  αい  Lp 〔γ7((ごV、+V、、−2φ、、、) 3/Z(V
2+V11.、2φFn) 3/2 )+r、((−V
、+VllF−2φ、p)3/2(V2+V、、  2
φrp)””) )     −+1)ただし、 μh  Cox でNチャネルMOSI−ランジスタ10のゲート幅w1
、ゲート長Lll、スレッショルド電圧v77と、Pチ
ャネルMOS)ランジスタ11のゲート幅Wp1ゲート
長り、スレッショルド電圧■TPをり、1    αP
   Lp v7.%=  Vtp = Vy となるように選んである。またCoxは半導体のゲート
酸化膜の容量で、μ7、■い、φ1、γ7はそれぞれN
チャネルMOS)ランジスタ1oのキャリアの移動度、
基板電圧、フェルミ準位、バイアス効果定数で、μp、
Vlp、φF2、γ2は、PチャネルMOS)ランジス
タ11のキャリアの移動度、基板電圧、フェルミ準位、
バイアス効果定数である。
is applied, the current I flowing between input terminal 1 and connection point 3 is 3 α Lp [γ7 ((V, +V, -2φ, ,) 3/Z(V
2+V11. , 2φFn) 3/2 )+r, ((-V
, +VllF-2φ,p)3/2(V2+V,, 2
φrp)””) ) −+1) However, μh Cox is the gate width w1 of the N-channel MOSI transistor 10.
, gate length Lll, threshold voltage v77, gate width Wp1 of P-channel MOS) transistor 11, gate length, threshold voltage ■TP, 1 αP
Lp v7. %=Vtp=Vy. Cox is the capacitance of the semiconductor gate oxide film, and μ7, ■, φ1, and γ7 are N, respectively.
channel MOS) carrier mobility of transistor 1o,
With substrate voltage, Fermi level, and bias effect constant, μp,
Vlp, φF2, γ2 are the carrier mobility of the P-channel MOS transistor 11, the substrate voltage, the Fermi level,
is the bias effect constant.

(1)式において第1項はV、−V2と電流が比例関係
にあるが、第2項が歪の要因として残る。この第2項は
lv+vzl依存性をもち、lv+−■21が大きいほ
ど第2項の絶対値が大きくなり歪も大きくなる。
In equation (1), the first term has a proportional relationship with V, -V2, and current, but the second term remains as a factor of distortion. This second term has lv+vzl dependence, and the larger lv+-21, the larger the absolute value of the second term and the larger the distortion.

本発明の目的は、上記の欠点を除去することにより、歪
が小さくてかつ面積を小さくでき集積化の効率を上げる
ことのできるRCアクティブフィルタを提供することに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an RC active filter that can reduce distortion, reduce area, and increase integration efficiency by eliminating the above-mentioned drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、ゲートを正電源に接続しドレインを入力端子
に接続しソースを第一の接続点に接続した第一のNチャ
ネルMOS)ランジスタおよびゲートを負電源に接続し
ソースを上記入力端子に接続しドレインを上記第一の接
続点に接続した第一のPチャネルMOS)ランジスタか
らなる第一のMOS抵抗と、ゲートを正電源に接続しド
レインを上記第一の接続点に接続しソースを第二の接続
点に接続した第二のNチャネルMOSトランジスタおよ
びゲートを負電源に接続しソースを上記第一の接続点に
接続しドレインを上記第二の接続点に接続した第二のP
チャネルMOSトランジスタからなる第二のMOS抵抗
と、正相入力を上記第二の接続点に接続し逆相入力およ
び出力を出力端子に接続した演算増幅器と、一端を上記
第二の接続点に接続し他端を接地電位に接続した第一の
コンデンサと、一端を上記第一の接続点に接続し他端を
上記出力端子に接続した第二のコンデンサとを含むRC
アクティブフィルタにおいて、上記第一のMOS抵抗と
直列に第一の抵抗を接続し、上記第二のMOS抵抗と直
列に第二の抵抗を接続したことを特徴とする。
The present invention provides a first N-channel MOS transistor whose gate is connected to a positive power supply, whose drain is connected to an input terminal, and whose source is connected to a first connection point, and whose gate is connected to a negative power supply and whose source is connected to the input terminal. A first MOS resistor consisting of a first P-channel MOS (first P-channel MOS) transistor whose gate is connected to the positive power supply and whose drain is connected to the first connection point and whose source is connected to the first connection point. a second N-channel MOS transistor connected to the second connection point, a second PMOS transistor having a gate connected to a negative power supply, a source connected to the first connection point, and a drain connected to the second connection point;
A second MOS resistor consisting of a channel MOS transistor, an operational amplifier whose positive phase input is connected to the second connection point, and whose negative phase input and output are connected to the output terminal, and one end of which is connected to the second connection point. and a second capacitor having one end connected to the first connection point and the other end connected to the output terminal.
The active filter is characterized in that a first resistor is connected in series with the first MOS resistor, and a second resistor is connected in series with the second MOS resistor.

また、本発明は、第一および第二の抵抗は拡散抵抗であ
ることが好ましい。
Further, in the present invention, it is preferable that the first and second resistors are diffused resistors.

〔作用〕[Effect]

抵抗が、抵抗とMOS抵抗との直列接続回路からなって
いるので、MOS抵抗の両端にかかる電圧はそれぞれの
抵抗値に従って分圧されるので、従来列のMOS抵抗単
独の場合に比べて小さくなり、それに従って歪みも小さ
くなる。
Since the resistor consists of a series-connected circuit of a resistor and a MOS resistor, the voltage applied across the MOS resistor is divided according to the respective resistance values, so it is smaller than when using only a conventional string of MOS resistors. , the distortion also decreases accordingly.

一方、抵抗として拡散抵抗を用いた場合の面積は、MO
S抵抗は拡散抵抗に比べて抵抗値が高いので拡散抵抗と
しては上記歪みの改善度に対応した値まで小さくするこ
とができ、従来例の拡散抵抗単独の場合に比べて抵抗と
しての面積を小さくできる。
On the other hand, when a diffused resistor is used as a resistor, the area is MO
Since the S resistor has a higher resistance value than the diffused resistor, the diffused resistor can be reduced to a value that corresponds to the degree of distortion improvement mentioned above, and the area as a resistor is smaller than the conventional diffused resistor alone. can.

従って、歪みを小さくしかつ面積を小さくして集積化の
効率を上げることが可能となる。
Therefore, it is possible to reduce distortion and area, thereby increasing integration efficiency.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

本実施例は、一端を入力端子に接続し他端を接続点18
に接続した第一の抵抗16と、ゲートを正電源■。に接
続しドレインを接続点18に接続しソースを第一の接続
点3に接続した第一のNチャネルMOSトランジスタ1
0と、ゲートを負電源■、に接続しソースを接続点18
に接続しドレインを接続点3に接続した第一のPチャネ
ルMOS)ランジスタ11と、ゲートを正電源■。に接
続しドレインを接続点3に接続しソースを接続点19に
接続した第二のNチャネルMOS)ランジスタ13と、
ゲートを負電源V3に接続しソースを接続点3に接続し
ドレインを接続点19に接続した第二のPチャネルMO
SI−ランジスタ14と、一端を接続点19に接続し他
端を接続点6に接続した第二の抵抗17と、正相入力を
接続点6に接続し逆相入力および出力を出力端子9に接
続した演算増幅器8と、一端を接続点6に接続し他端を
接地電位に接続した第一のコンデンサ5と、一端を接続
点3に接続し他端を出力端子9に接続した第二のコンデ
ンサ7とを含んでいる。
In this embodiment, one end is connected to the input terminal and the other end is connected to the connection point 18.
The first resistor 16 connected to and the gate connected to the positive power supply ■. a first N-channel MOS transistor 1 having a drain connected to a connection point 18 and a source connected to a first connection point 3;
0, the gate is connected to the negative power supply ■, and the source is connected to the connection point 18
A first P-channel MOS transistor 11 whose drain is connected to the connection point 3 and whose gate is connected to the positive power supply ■. a second N-channel MOS) transistor 13 connected to
A second P-channel MO whose gate is connected to the negative power supply V3, whose source is connected to connection point 3, and whose drain is connected to connection point 19.
SI-transistor 14, a second resistor 17 with one end connected to connection point 19 and the other end connected to connection point 6, a positive phase input connected to connection point 6, and a negative phase input and output connected to output terminal 9. A first capacitor 5 has one end connected to the connection point 6 and the other end connected to ground potential, and a second capacitor 5 has one end connected to the connection point 3 and the other end connected to the output terminal 9. It includes a capacitor 7.

ここで、NチャネルMOS)ランジスタ10と、Pチャ
ネルMOS)ランジスタ11とでMOS抵抗12を構成
し、NチャネルMOS)ランジスタ13とPチャネルM
OS)ランジスタ14とでMOS抵抗15を構成する。
Here, an N-channel MOS) transistor 10 and a P-channel MOS) transistor 11 constitute a MOS resistor 12, and an N-channel MOS) transistor 13 and a P-channel MOS transistor 13 constitute a MOS resistor 12.
(OS) transistor 14 constitutes a MOS resistor 15.

また抵抗16および17は拡散抵抗である。Further, resistors 16 and 17 are diffused resistors.

本発明の特徴は、第1図において抵抗16および17を
接続し、RCアクティブフィルタを構成する抵抗として
MOS抵抗と拡散抵抗との直列接続抵抗を用いるように
したことにある。
The feature of the present invention is that the resistors 16 and 17 are connected in FIG. 1, and a series-connected resistor of a MOS resistor and a diffused resistor is used as the resistor constituting the RC active filter.

次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

本実施例では、NチャネルMOSI−ランジスタ10の
ゲートが正電源■。に接続され、PチャネルMOS)ラ
ンジスタ11のゲートが負電源V、に接続されているの
で、NチャネルMoSトランジスタ10およびPチャネ
ルMOS)ランジスタ11の両方が常にオン状態でMO
S抵抗として使用している。入力端子1、接続点18お
よび接続点3の電圧をそれぞれv、 Sv、 、および
v2とし、抵抗16の抵抗値をR,、MOS抵抗12の
抵抗値をR2とすると R1+R2 −・−・−・−(2) となり、第3図の従来例のようにMOS抵抗12だけで
構成した場合に比べMOS抵抗12の両端の電圧が R。
In this embodiment, the gate of the N-channel MOSI transistor 10 is connected to the positive power supply (2). Since the gate of the P-channel MOS transistor 11 is connected to the negative power supply V, both the N-channel MoS transistor 10 and the P-channel MOS transistor 11 are always on.
It is used as an S resistor. Let the voltages of input terminal 1, connection point 18, and connection point 3 be v, Sv, and v2, respectively, and let the resistance value of resistor 16 be R, and the resistance value of MOS resistor 12 be R2, then R1+R2 −・−・−・-(2), and the voltage across the MOS resistor 12 is R compared to the case where the MOS resistor 12 is used as the conventional example shown in FIG.

R1+R。R1+R.

倍になる結果小さくなる。すなわち、MOS抵抗12に
よる歪が減少する。これはMOS抵抗15についても同
様である。また、面積もMOS抵抗は拡散抵抗に比べ小
さいので、第2図の従来例のように拡散抵抗だけで構成
した場合に比べ約I RI+R2 程度に小さくなる。
As a result of doubling, it becomes smaller. That is, the distortion caused by the MOS resistor 12 is reduced. This also applies to the MOS resistor 15. Furthermore, since the area of the MOS resistor is smaller than that of the diffused resistor, the area is about I RI + R2 smaller than that of the conventional example shown in FIG. 2, which is composed of only diffused resistors.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、拡散抵抗とMOS抵抗
を直列に接続した抵抗を用いることにより、歪を小さく
でき、かつ面積も小さくでき集積化の効率をあげる効果
がある。
As described above, the present invention has the effect of reducing distortion and reducing area by using a resistor in which a diffused resistor and a MOS resistor are connected in series, thereby increasing the efficiency of integration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図。 第2図および第3図は従来例を示す回路図。 1・・・入力端子、2.4.16.17・・・抵抗、3
.6.1B、19・・・接続点、5.7・・・コンデン
サ、8・・・演算増幅器、9・・・出力端子、10.1
3・・・NチャネルMOSトランジスタ、11.14・
・・PチャネルMOS)ランジスタ、12.15・・・
MOS抵抗、v8・・・正電源、■、・・・負電源。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIGS. 2 and 3 are circuit diagrams showing conventional examples. 1...Input terminal, 2.4.16.17...Resistor, 3
.. 6.1B, 19... Connection point, 5.7... Capacitor, 8... Operational amplifier, 9... Output terminal, 10.1
3...N channel MOS transistor, 11.14.
...P channel MOS) transistor, 12.15...
MOS resistance, v8...Positive power supply, ■,...Negative power supply.

Claims (2)

【特許請求の範囲】[Claims] (1)ゲートを正電源(V_D)に接続しドレインを入
力端子(1)に接続しソースを第一の接続点(3)に接
続した第一のNチャネルMOSトランジスタ(10)お
よびゲートを負電源(V_S)に接続しソースを上記入
力端子に接続しドレインを上記第一の接続点に接続した
第一のPチャネルMOSトランジスタ(11)からなる
第一のMOS抵抗(12)と、ゲートを正電源に接続し
ドレインを上記第一の接続点に接続しソースを第二の接
続点(6)に接続した第二のNチャネルMOSトランジ
スタ(13)およびゲートを負電源に接続しソースを上
記第一の接続点に接続しドレインを上記第二の接続点に
接続した第二のPチャネルMOSトランジスタ(14)
からなる第二のMOS抵抗(15)と、正相入力を上記
第二の接続点に接続し逆相入力および出力を出力端子(
9)に接続した演算増幅器(8)と、一端を上記第二の
接続点に接続し他端を接地電位に接続した第一のコンデ
ンサ(5)と、一端を上記第一の接続点に接続し他端を
上記出力端子に接続した第二のコンデンサ(7)とを含
むRCアクティブフィルタにおいて、 上記第一のMOS抵抗と直列に第一の抵抗(16)を接
続し、上記第二のMOS抵抗と直列に第二の抵抗(17
)を接続した ことを特徴とするRCアクティブフィルタ。
(1) A first N-channel MOS transistor (10) whose gate is connected to the positive power supply (V_D), whose drain is connected to the input terminal (1), and whose source is connected to the first connection point (3); A first MOS resistor (12) consisting of a first P-channel MOS transistor (11) connected to a power supply (V_S), a source connected to the input terminal, and a drain connected to the first connection point; A second N-channel MOS transistor (13) is connected to the positive power supply, its drain is connected to the first connection point, and its source is connected to the second connection point (6), and the gate is connected to the negative power supply, and the source is connected to the a second P-channel MOS transistor (14) connected to the first connection point and having its drain connected to the second connection point;
The positive phase input is connected to the second connection point, and the negative phase input and output are connected to the output terminal (
9), a first capacitor (5) with one end connected to the second connection point and the other end connected to ground potential, and one end connected to the first connection point. and a second capacitor (7) whose other end is connected to the output terminal, a first resistor (16) is connected in series with the first MOS resistor, and the second MOS resistor is connected in series with the second MOS resistor. A second resistor (17
) is connected to the RC active filter.
(2)第一および第二の抵抗は拡散抵抗である特許請求
の範囲第(1)項に記載のRCアクティブフィルタ。
(2) The RC active filter according to claim (1), wherein the first and second resistors are diffused resistors.
JP20311086A 1986-08-29 1986-08-29 Rc active filter Pending JPS6359210A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20311086A JPS6359210A (en) 1986-08-29 1986-08-29 Rc active filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20311086A JPS6359210A (en) 1986-08-29 1986-08-29 Rc active filter

Publications (1)

Publication Number Publication Date
JPS6359210A true JPS6359210A (en) 1988-03-15

Family

ID=16468562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20311086A Pending JPS6359210A (en) 1986-08-29 1986-08-29 Rc active filter

Country Status (1)

Country Link
JP (1) JPS6359210A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55116271A (en) * 1978-09-26 1980-09-06 Seiko Instr & Electronics Ltd Battery voltage detector
JPS59115610A (en) * 1982-12-22 1984-07-04 Hitachi Ltd Semiconductor filter circuit
JPS607218A (en) * 1983-06-24 1985-01-16 Toa Denpa Kogyo Kk Active filter
JPS6188549A (en) * 1984-10-05 1986-05-06 Citizen Watch Co Ltd Semiconductor integrated circuit with detecting circuit for life of battery

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55116271A (en) * 1978-09-26 1980-09-06 Seiko Instr & Electronics Ltd Battery voltage detector
JPS59115610A (en) * 1982-12-22 1984-07-04 Hitachi Ltd Semiconductor filter circuit
JPS607218A (en) * 1983-06-24 1985-01-16 Toa Denpa Kogyo Kk Active filter
JPS6188549A (en) * 1984-10-05 1986-05-06 Citizen Watch Co Ltd Semiconductor integrated circuit with detecting circuit for life of battery

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