JPH03133213A - Dynamic type frequency divider - Google Patents

Abstract

PURPOSE:To improve the allowable power voltage giving effect onto the DC bias of a transfer gate by setting the absolute value of a threshold voltage of the transfer gate to the value multiplied by 1.5 to 3 of the absolute value of the threshold voltage of other FET. CONSTITUTION:The absolute value of the threshold voltage of transfer gate FETs 7,9 is set to be nearly twice the absolute value of the threshold voltage of other FETs. When a clock signal IN is inputted to an input terminal 1, a DC component is eliminated from the clock signal IN by a coupling capacitor 2, the phase is inverted by an input inverter 4 and inputted to the gate of a transfer gate 7 via a coupling capacitor 5. Since the absolute value of the thresh old voltage of the transfer gate FETs 7,9 is set to be twice the absolute value of the threshold voltage of the other FETs, the allowable value when power voltages +VDD,-VSS are fluctuated is increased more than that of a conven tional divider.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to a field effect transistor (hereinafter referred to as FET) made of a compound semiconductor such as semi-interrupted GaAs.
This invention relates to a dynamic frequency divider that operates in a high frequency region and is configured by:

[Prior Art] Development of dynamic frequency dividers that operate in a high frequency region such as a microwave band has been progressing in order to achieve high-speed operation with a simple circuit configuration. FIG. 2 is a circuit diagram showing an example of a conventional dynamic frequency divider of this type.

That is, the clock signal inputted via the input terminal 40 is inverted by the input inverter 41 and inputted to the gate of the transfer 1 gate FET 42, and is also directly inputted to the gate of the transfer gate FET 43. The output terminal of transfer gate FET42 and the transfer gate
) An inverter circuit 44 is connected between the input terminal of the FET 43 and the input terminal of the FET 43.
is inserted. In addition, transfer gate FET4
A buffer 1 circuit 4 is connected between the output terminal of 3 and the output terminal 4θ.
5 is inserted. The output of the buffer circuit 45 is fed back to the input terminal of the transfer gate FET 42.

The inverter circuit 44 includes, for example, as shown in FIG. 3(a), N-channel FETs 49 and 48 connected in series between the +DD power supply terminal 50 and the ground, the +VDD power supply terminal 50 and the -VSS power supply terminal. 55, an N-channel FET 51, diodes 52, 53, and an N-channel FET 54 are connected in series. Input side FE
T48 has its gate connected to the input terminal 47 and drives an FET 49 as a load whose source and gate are connected. The output of FET48 is input to the gate of FET51 in the output stage. FET51 is a diode 52
．． 53 and a FET 54 whose gate and source are connected constitute a source follower, and output an amplified inverted output signal from an output terminal 56 between the diodes 52 and 53.

Further, the buffer circuit 45 has a +vDD power supply terminal 59 and a -VSS power supply terminal 60, as shown in FIG. 3(b), for example.
N-channel FETs 57 and 58 connected in series between
Consisting of The FET 57 inputs the input signal from the input terminal 61 to its gate, drives the FET 58 as a load whose gate and source are connected, and outputs a normal output signal from the output terminal 62.

In the conventional dynamic frequency divider configured in this way, the transfer gate FETs 42 and 43 are alternately turned on in accordance with the clock signal input from the input terminal 40, and the inverter circuit is connected at twice the period of the clock signal. 44
Since the signal transfer and holding to the buffer circuit 45 are repeated, the clock signal from the buffer circuit 45 is
A divided output signal whose frequency is divided by two is output.

[Problems to be Solved by the Invention] Incidentally, in the above-described conventional dynamic frequency divider, the gate of the transfer gate FET is biased with direct current. This gate bias voltage affects the electrical characteristics of the dynamic frequency divider, particularly the maximum operating frequency and input sensitivity characteristics.

On the other hand, this gate bias voltage is usually given by dividing the power supply voltage by resistance, and its value is set to approximately 1/2 of the threshold voltage of the FET. Therefore, when the power supply voltage fluctuates, the gate bias voltage also fluctuates, resulting in a problem that the power supply voltage tolerance is limited. Also, F
Transfer gate FE due to changes in ET manufacturing conditions, etc.
There is a problem that the maximum operating frequency and input sensitivity characteristics are not constant due to the influence of variations in the threshold voltage of T.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a dynamic frequency divider that can improve power supply voltage tolerance and stabilize maximum operating frequency and input sensitivity characteristics.

[Means for Solving the Problems] A dynamic frequency divider according to the present invention includes a first transfer gate which transfers a frequency-divided output signal according to a first gate input signal and whose gate is DC biased; an inverter circuit that inputs the output of the first transfer gate, inverts its phase, and outputs it; and a signal output from the inverter circuit that transfers the signal according to a second gate input signal that is an inversion of the first gate input signal. It also has a second transfer gate whose gate is DC biased, and a buffer circuit that inputs the output of the second transfer gate and outputs the frequency-divided output signal, and these are constituted by field effect transistors made of compound semiconductors. In the dynamic frequency divider, the absolute value of the threshold voltage of the field effect transistors forming the first and second transfer gates is equal to the threshold voltage of the field effect transistors forming the inverter circuit and the buffer circuit. It is characterized by being set to 1.5 to 3 times the absolute value.

[The gate bias voltage of the effect co-transfer gate is set to about 1/2 of the threshold voltage of the transfer 1 gate, but according to the present invention, the absolute value of the threshold voltage of the transfer gate Since the threshold voltage of the FET, that is, the absolute value of the threshold voltage of a conventional transfer gate is set to be larger than the absolute value, stability against fluctuations in gate bias voltage increases accordingly. Therefore, tolerance to fluctuations in the power supply voltage that generates the gate bias voltage also increases.

Further, according to the present invention, by increasing the absolute value of the threshold voltage, the on-resistance can be reduced, so the overall loop gain including the two transfer gates, the inverter circuit, and the buffer circuit is increased, and the maximum The operating frequency and input sensitivity characteristics can be improved and kept constant.

The inventors varied the threshold voltages of the first and second transfer gates to simulate the electrical characteristics of the circuit. As a result, it was confirmed that the effects of the present invention are significantly exhibited when the absolute value of the threshold voltage of the transfer gate exceeds 1.6 times the absolute value of the threshold voltages constituting other circuits. In addition, the gate breakdown voltage decreased as the threshold voltage increased, but until the absolute value of the transfer gate threshold voltage was three times the absolute value of other FETs,
A gate breakdown voltage that can withstand practical use was obtained.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a dynamic frequency divider according to an embodiment of the present invention.

A clock signal IN inputted from an input terminal 1 is inputted to the gate of a transformer FET 7 via a coupling capacitor 2, an input inverter 4, and a coupling capacitor 5. Further, the clock signal IN is directly input from the input terminal 1 to the gate of the transfer gate FET 9 via the coupling capacitor 3.

The output terminal of the inverter circuit 6 is connected to the input terminal of the transfer gate FET 7. A buffer circuit 8 is connected between the output end of the transfer gate FET 7 and the input end of the transfer gate FET 9. The output of the buffer circuit 8 is outputted from the output terminal 17 via the output buffer 15 as a frequency-divided output signal OUT.

Furthermore, the output of the transfer gate 9 is connected to the inverter circuit 6.
is input to the input terminal of.

On the other hand, resistors 13 and 14 are connected in series between the +VDD power terminal 16 and the -VSS power terminal 1θ. The gate of the transfer gate FET 7 is connected via a resistor 10 to the connection point of the resistors 13 and 14. Further, the gate of the transfer gate FET 9 is connected via a resistor 11 to the connection point of the resistors 13 and 14.

The connection point of the resistors 13 and 14 is connected to AC ground via the bypass capacitor 12.

The input inverter 4 includes a resistor 21 and an N-channel FET 2 connected in series between a power supply terminal 18 and a ground terminal 18.
0 and N-channel FETs 22 and 23 connected in series between the power supply terminals 18 and 19, and the input stage FET 20.
A signal is input to the gate of the output stage FE.
1. is connected to the gate of T22, and the gate and source of FET23 are connected. A phase-inverted signal is output from the connection point of FETs 22 and 23.

The inverter circuit 8 includes a resistor 25 and an N-channel FET 2 connected in series between a power supply terminal 16 and a ground terminal 18.
4 and the N-channel FET 27, diode 28, and N-channel FET connected in series between the power supply terminals 18 and 19.
2B, a signal is input to the gate of FET 24 in the input stage, its drain is connected to the gate of FET 27 in the output stage, and the gate and source of FET 2θ are connected.
A signal whose phase is inverted is output from the connection point between the diode 28 and the FET 213.

The buffer 1 circuit 8 consists of N-channel FETs 29 and 30 connected in series between power supply terminals 18 and 19, and the FET
A signal is input to the gate of FET 29, and a frequency-divided output signal having the same phase as the input signal is output from the connection point of FETs 29 and 30.

The output buffer 15 consists of N-channel FETs 31 and 32 connected in series between power supply terminals 18 and 19.
The frequency-divided output signal is input to the gate of FET 31, and
．． Divided output signal OU that is in phase with the input signal from the 32 connection points
It is designed to output T.

The transfer FETs 7 and 9 are, for example, normally-on type FETs, and the absolute value of the threshold value thereof is set to be approximately twice the absolute value of the threshold value of the other FETs. Further, the gates of transfer gate FETs 7 and 9 are connected to resistors 10, 11 .
13.14, the voltage is DC biased to, for example, a voltage of about 1/2 of the threshold voltage.

In the dynamic frequency divider configured in this way,
When a clock signal IN is input to the input terminal 1, the clock signal IN has its DC component removed by the coupling capacitor 2, is phase inverted by the input inverter 4, passes through the coupling capacitor 6, and then is transferred to the transfer gate 7. input into the gate.

Further, the clock signal IN is inputted to the gate of the transfer gate 9 after the DC component is removed by the coupling capacitor 3 . Therefore, the transfer FETs 7 and 9 are turned on alternately in accordance with the clock signal.

Now, when the transfer gate FET 9 is on, the output of the buffer 1 circuit 8 is input to the inverter circuit 6, where it is inverted. Next is the transfer gate FET
7 turns on, the output of the inverter circuit B is transmitted to the buffer circuit 8, so the frequency-divided output signal OUT outputted via the output buffer 15 is inverted. By repeating this, the clock signal 1 is output to the output terminal 17.
A signal obtained by dividing 7 into 1/2 is output.

According to the circuit of this embodiment, the transfer gate FET7
．． Since the absolute value of the threshold voltage of θ is set to twice the absolute value of the threshold voltage of other FETs, the power supply +V DD*
- The tolerance when Vss fluctuates can be increased more than before.

Incidentally, the present inventor has developed a transfer gate FET7.
The absolute value of the threshold voltage of 9 is 1. A computer simulation was conducted to determine how each electrical characteristic changes when the absolute value of the threshold voltage of the other FETs is set to 0.5 V, which is the same as before.

As a result, the power supply voltage tolerance was improved by 80%, and the allowable range of variation in the FET threshold voltage was improved by 20%. Furthermore, the on-resistance of the transfer 1 gate FETs 7 and 9 was reduced and the loop gain of the entire frequency divider was increased, so that the maximum operating frequency increased by 15%, while the minimum operating frequency did not change.

Note that the present invention is not limited to the embodiments described above. According to the simulation results obtained by the inventor,
The absolute value of the transfer gate threshold voltage is different from that of other FETs.
The effects of the present invention can be obtained if the absolute value of the threshold voltage is 1.5 times or more, preferably twice or more. However, if the threshold voltage of the transfer gate is increased too much, the gate breakdown voltage will be lowered, so it is desirable to set it to 3 times or less.

[Effects of the Invention] As explained above, according to the present invention, the absolute value of the threshold voltage of the transfer 1 gate is set to 1.5 to 3 times the absolute value of the threshold voltage of the other FETs. The power supply voltage tolerance that affects the DC bias point of the transfer gate can be improved, and the maximum operating frequency and input sensitivity characteristics can be stabilized.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a dynamic frequency divider according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional dynamic frequency divider, and Fig. 3(a) is a detail of the inverter circuit in Fig. 2. The circuit diagram, FIG. 3(b) is a detailed circuit diagram of the buffer circuit in FIG.

Claims (1)

[Claims] (1) Transfer the frequency-divided output signal according to the first gate input signal, input the first transfer gate whose gate is DC biased, input the output of this first transfer gate, invert the phase, and output it. an inverter circuit, and a signal output from the inverter circuit to the first
The second gate input signal is transferred according to the inverted second gate input signal, and the gate is DC biased.
A dynamic frequency divider comprising a transfer gate and a buffer circuit inputting the output of the second transfer gate and outputting the frequency-divided output signal, the dynamic frequency divider comprising compound semiconductor field effect transistors, The absolute value of the threshold voltage of the field effect transistors forming the first and second transfer gates is 1.5 to 3 times the absolute value of the threshold voltage of the field effect transistors forming the inverter circuit and the buffer circuit. A dynamic frequency divider characterized in that the frequency divider is set to .