JPS611046A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a C-MOSIC having excellent latch up withstand by forming the first conductive type island into the first conductive type high density substrate. CONSTITUTION:An n<--> type layer 105 is epitaxially grown on a high density n<+> type semiconductor substrate 111, and a p type island 106 and an n<-> type island 112 are formed on the layer 105. In this case, the island 112 is diffused into the substrate 105. In this configuration, when a positive surge voltage is applied to an output terminal OUT, a large current is flowed to the collector of a PNP type transistor (Tr) 2. In other words, if the amplification factor of the Tr 2 is large, the base current of the Tr 3 increases to rush to latch up state. However, when the island 112 is diffused into the substrate 111, the base density of the Trs 1, 2 increases. Thus, the recombination number of the carriers in the base increases, the current flowed corresponding to the increased number decreases, the current amplification factor decreases to increase the latch up withstand.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary type M
OS integrated circuit device (hereinafter abbreviated as ClllO5IC)
This is related to the improvement of.

[Traditional technique]

Generally, 0MO9IC has P-channel MO on the same substrate.
S transistor (hereinafter abbreviated as PMO5T) and N
Since a channel MOS transistor (hereinafter abbreviated as NHO3T) is formed, a parasitic bipolar transistor is formed between the P type and N expansion diffusion layers that constitute these transistors, and these transistors constitute a thyristor. So, this is what is called. This results in a phenomenon called latch-up, which is unique to 0MO3 ICs, and has the drawback of eventually leading to the destruction of the IC.

FIG. 1 is a circuit diagram showing the minimum unit of the 0M05 circuit.

In this Figure 1, (A) is PMO9T, (1
01) indicates its source, (102) indicates its drain, (B) indicates NMOST, (103) indicates its source, and (104) indicates its drain. And P.M.
O9T (A) (7)'/-S (101) is the power supply terminal V o D, the source (103) of NMOST (B)
are connected to the power supply terminals v and S, respectively, and both HO5T (
The gates of A) and (B) are commonly connected to the input terminal IN, and the drains (+02) and (+oa) of the same are commonly connected to the output terminal OUT, respectively.

Further, FIG. 2 is a structural sectional view of a conventional CMOS IC that actually constitutes the circuit shown in FIG. 1. In this FIG. 2, (105) is an n-type semiconductor substrate, (1
08), (112) are NMOST (B), PMOST
(A) are p-type and n-type islands formed respectively, (107) is the insulating layer, (108) is the metal electrode,
(1o9) is a double-shaped contact layer for the power supply terminal vS8, and (109) is an n+ type contact layer for the power supply terminal vDD.

And PMOST (A) is an n-type island (1
12) A D diffusion layer formed on the source (101) and a D diffusion layer forming the drain (102), and an insulating layer (107) formed between the source (101) and the drain (102). metal electrode (108
), and PMOST
(A) shows the n++ diffused layer formed on the p-type island (10B) to become the source (+03) and the drain (
104) and these sources (103
) and the drain (104) and an insulating layer (10?) between the drain (104) and the drain (104).
) and a gate electrode formed by a metal electrode (108).

In the CMOS fil: with the configuration shown in Figure 2, as mentioned earlier, the respective bipolar transistors and resistors related to latch-up are parasitic as shown by the broken lines in the figure. .

That is, (1) consists of the D-type source region (101) of PMOST (A), the n-type island (112),
It is formed between it and a thousand-shaped island (106).

PNP transistor, (2) connects p+ type train region (102) of PMOST (A) and n- type island (
112) and a p-type island (106) therein. Also, (3) is NHO3T (B) (Inn+n
n-type region (+03) and p-type island (10B)
and an n-type semiconductor substrate (105'), an NPI transistor (4) is an n+-type drain region 104 of NHO9T (B)).
, the p-type island (10G), and the n-type semiconductor substrate (105).

An NPN transistor is shown. Also, (5) is n-
power supply terminal V in the shaped semiconductor substrate (105). The resistance up to D, (6) is the resistance in the D-type source region (101) of PMOST (A), and (7) is the resistance in the p-type island (10
6) Tenohistor all the way to the power supply terminal Vss in
is NHO9T (B) (7) n+ type source region (10
3) is the internal resistance. Furthermore, in Figure 3, these second
The figure shows a parasitic circuit made up of parasitic elements indicated by broken lines.

Next, the operation during the latch-up phenomenon will be described with reference to FIGS. 2 and 3.

Now, when a negative surge voltage is applied to the output terminal OUT, the p-type island (10B) and NHO5T (B)
(7) A forward current flows between the n” type drain (+04), the NPN transistor (4) becomes conductive, and the NHO3T (B) is transferred from the n− type semiconductor substrate (105).
A current amplified by the amplification factor hFE1 of the NPN transistor (4) flows toward the n1 type drain (104) of the NPN transistor (4), and this current flows to the power supply terminal V. 0 through a resistor (5). Therefore, this current causes the base and emitter of the PNP transistor (1) to be forward biased and conductive, and the current flows to the power supply terminal V. resistor (8), PNP transistor (1), transistor (1), and resistor (
7) to the power supply terminal vDD. This further forward biases the NPN transistor (3) and draws the base current of the PNP transistor (1), so even if the previous surge input to the output terminal OUT disappears, the PNP transistor (1) and the NPN transistor (3) ) and for the thyristor configuration, the power supply terminal v
A large current will continue to flow between DD and vSS,
As a result, the element is destroyed.

Then, in the same way, when a positive surge voltage is applied to the output terminal OUT, the n-type island (+12) and PM
OST (A) A forward current flows between the P+ type drain (102) and the PNP transistor (2) becomes conductive, and the PNP transistor (2) is connected from the p- type island (10B) to the PMO drain (102).
Toward the p+ type drain 102) of ST (A),
A current amplified by the amplification factor hFE2 of the PNP transistor (2) flows to the power supply terminal VSS via the resistor (7).

Therefore, due to this current, the base-emitter of the NPN transistor (3) is forward biased and becomes conductive.
Current flows from the power supply terminal vDD to the power supply terminal vSS through the resistor (5), NPN transistor (3), and resistor (8).
flows to As a result, the PNP transistor (1) is further forward biased, and the NPN transistor (
3), so even if the surge input to the output terminal 0υT disappears, the PNP transistor (
1) and an NPN transistor (3) for the thyristor configuration, the power supply terminal V. A large current continues to flow between D'SS and produces the same result, and due to the structure of CMOS ICs, the formation of parasitic bipolar transistors cannot be avoided, and the latch-up phenomenon becomes a major problem. It was something.

Recently, as shown in FIG. 4, an n- type layer (105) is epitaxially grown on a highly doped n+ type semiconductor substrate (111), and a P- type island (108) is formed on this grown layer (105). Attempts have been made to prevent the latch-up phenomenon described above by forming n-type islands (112). This structure is achieved by increasing the concentration of the semiconductor substrate, resulting in a parasitic bipolar PNP transistor (1).
, (2) by increasing the base concentration, thereby recombining as many carriers as possible in the base, to increase the PN
P amplification factor hFEI of transistors (1) and (2),
This is intended to lower h□2 and increase latch-up resistance.

However, in the configuration shown in FIG. 4, in order to control the concentration of both island regions, it is necessary to form the n-type layer (to5) with a very low concentration. And for this purpose the power supply terminal vD
In addition to the resistance (5) from D, the resistance (8) in the n-type layer (105) will be superimposed, and the high concentration substrate (
111), the purpose of lowering the resistance value of the resistor (5) in the configuration shown in FIG. 3 could not be achieved, and the latch-up resistance would be poor.

[Summary of the Invention] The present invention aims to improve such drawbacks of the conventional technology, and by eliminating the formation of the resistor (8) in the configuration shown in FIG.
It provides IC.

[Embodiments of the invention]

Hereinafter, one embodiment of a complementary MO3 integrated circuit device as a semiconductor integrated circuit device according to the present invention will be described.

This will be explained in detail with reference to FIG.

In this FIG. 5 embodiment device, the above-mentioned FIGS.
The same reference numerals as in the conventional device in the figure represent the same or corresponding parts, and in this example device, the n-type islands are diffused into the high concentration substrate (105).

Now, as described in the conventional example above, when a positive surge voltage is applied to the output terminal OUT, the PN
The current flowing through the collector of P transistor (2) is large, that is, the amplification factor hF of PNP transistor (2)
When E2 is large, the base current of the NPN transistor (3) becomes large and enters a rough stub state.
When 112) is diffused into the highly concentrated substrate (111), the base concentration of the PNP transistors (1) and (2) increases, so the number of carrier recombinations in this base increases, and this increase Correspondingly, the current that flows decreases, the current amplification factor decreases, and the rough rise resistance increases. Also, due to this structure, the fourth
When the resistor (8) in the figure is removed, the PN in Figure 3 is
The parasitic resistance (5) between the base and emitter of the P-type transistor (1) is reduced compared to the conventional example shown in FIG.
) becomes difficult to operate, and the latch-up resistance is greatly improved.

〔Effect of the invention〕

As detailed above, according to the present invention, a low concentration layer of the first conductivity type is epitaxially grown on a high concentration substrate of the first conductivity type, and a low concentration layer of the first conductivity type is grown on the epitaxially grown layer so as not to be in contact with the high concentration substrate. A first region of a second conductivity type for forming a MOS transistor of a first conductivity type, and a second region of a first conductivity type for forming a MO9I-transistor of a second conductivity type in contact with a high concentration substrate. Since the regions are formed separately, the resistance value of the parasitic resistance between the base and emitter of the parasitic transistor, which is a cause of the latch-up phenomenon in this type of semiconductor integrated circuit device, can be reduced. It has features such as being able to improve latch-up resistance, and being simple in structure and easy to implement.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the minimum unit of a complementary NOS integrated circuit, and Fig. 2 is a cross section showing the structure of a conventional complementary HO5 integrated circuit device together with parasitic elements when the circuit shown in Fig. 1 is actually constructed. 3 is a circuit diagram showing a parasitic circuit using the same parasitic elements as above, FIG. 4 is a sectional view showing the structure of a conventional device improved to prevent latch-up together with parasitic elements, and FIG. 5 is a circuit diagram showing a parasitic circuit according to the present invention. FIG. 2 is a cross-sectional view showing the structure of an embodiment of such a complementary MOS integrated circuit device together with parasitic elements. (A)...PMOST (P-channel MO5 transistor), (tol)... Source of PMOST, (
102) Drain of PMOST, (B)...
・NMO3T (N-channel MO3 transistor),
(+03)...NMO8T source, (104)
...Drain of NMO3T, (105)...Low concentration semiconductor layer (low concentration epitaxial growth layer), (
10B) and (112)...island (first and second regions), (Ill)...high concentration semiconductor substrate.

Claims (1)

[Claims] A low concentration layer of a first conductivity type is epitaxially grown on a high concentration substrate of a first conductivity type, and a MOS transistor of a first conductivity type is formed on the epitaxially grown layer so as not to be in contact with the high concentration substrate. forming a first region of a second conductivity type for forming a MOS transistor of a second conductivity type, and a second region of a first conductivity type for forming a MOS transistor of a second conductivity type in contact with the high concentration substrate; A semiconductor integrated circuit device characterized by: