JPH06120745A - Bipolar integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a current push pull output circuit in which the problem of a subharmonic distortion can be prevented by biasing the N-type epitaxial layer of an output stage vertical PNP transistor to a potential between a power source potential and a collector potential by a low impedance. CONSTITUTION:The N-type epitaxial layer of an output stage vertical PNP transistor Tr 28 is biased by the low impedance through a terminal 36 by an NPN Tr 37 and a resistance 38. The potential is decided by resistances 39 and 40. Therefore, the potential of the N-type epitaxial layer of the PNP Tr 28 is made higher than the potential of the correcter area, so that the influence of a parasitic Tr can be prevented, and the problem of the subharmonic distortion can be improved even when a potential gradient is generated at the correcter area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar integrated circuit, and more particularly to improving a phenomenon of subharmonic distortion which is a problem in a current push-pull output circuit.

[0002]

2. Description of the Related Art In a current push-pull output circuit,
It is a commonly used method to use a PNP output transistor that discharges a current to the outside and an NPN output transistor that pulls a current from the outside in combination. Next, this general conventional example will be described with reference to FIG. That is, in the configuration of FIG. 2, 1 is a control circuit of a current push-pull output circuit, 2 and 3 are vertical PNP transistors that form a current mirror circuit of the output stage, 4 and 5 are resistors that determine the mirror ratio of the current mirror circuit, and 6 , 7 are NPN transistors forming the output stage current mirror circuit,
Reference numerals 8 and 9 are resistors that determine the mirror ratio of the current mirror circuit, 10 is a circuit power supply, and 11 is an output stage vertical PNP.
This is a terminal taken out from the N-type epitaxial layer of the transistor 3. The N-type epitaxial layer of the vertical PNP transistor 3 will be described with reference to FIG. FIG. 3 is a sectional view of a process configuration of a general vertical PNP transistor. That is, in the configuration of FIG. 3, 12 is a P-type silicon substrate, 13 is an N-type buried layer embedded in the P-type silicon substrate 12, and 14 is a P for element isolation.
Type regions, 15 and 16 are P type collector regions, 17 is an N type base region, 18 is an N type diffusion layer for extracting a base terminal, 19 is a P type emitter region, and 20 is a P type region 14 for element isolation. An N-type epitaxial layer separating the P-type collector regions 15 and 16, 21 is an insulating film, 22 is an emitter electrode, 23 is a base electrode, 24 is a collector electrode, and 25 is N.
The electrode is taken out from the mold epitaxial layer 20. In the vertical PNP transistor shown in FIG. 3, the N-type epitaxial layer 20 exists due to its process configuration.
Conventionally, the N-type epitaxial layer 20 is used in a floating state without being biased, or the collector electrode 24 is used.
And the electrode 25 taken out from the N-type epitaxial layer 20 are connected and the potential of the N-type epitaxial layer 20 is used in common with the collector potential, or the N-type epitaxial layer 20 is biased to the power supply potential and used. It is common to have However, when the output current is large, the phenomenon of subharmonic distortion occurs in the above conventional general usage,
It is known that a transistor breakdown voltage problem occurs due to a process configuration. For example, in the conventional current push-pull output circuit shown in FIG. 2, the breakdown voltage between the collector regions 15 and 16 and the N-type epitaxial layer 20 shown in FIG. 3 is generally low, and therefore, depending on the potential of the power supply 10 shown in FIG. In many cases, the terminal 11 taken out from the N-type epitaxial layer 20 of the vertical PNP transistor cannot be biased to the power supply potential. Further, when the N-type epitaxial layer 20 is used in a potential floating state without biasing the terminal 11, a potential gradient occurs in the collector regions 15 and 16 shown in FIG. 17 and collector regions 15, 16 and N
Type epitaxial layer 20, or collector region 15,
16, a parasitic transistor is generated in the N-type epitaxial layer 20, the P-type region 14 for element isolation, and the P-type substrate 12, and a phenomenon of subharmonic distortion occurs in the output. Even if the collector electrode 24 and the electrode 25 taken out from the N-type epitaxial layer 20 are connected in order to prevent the influence of the parasitic transistor, a parasitic transistor is generated because a potential gradient is generated in the collector regions 15 and 16, and the subharmonic distortion occurs. The problem of does not improve.

[0003]

The current push-pull output circuit according to the conventional example has a problem that the phenomenon of subharmonic distortion occurs as described above. The present invention has been made in view of the above points, and an object thereof is to provide an output circuit that does not cause the problem of subharmonic distortion.

[0004]

To achieve this object, the present invention provides a current push-pull output circuit in which an N-type epitaxial layer forming an output stage vertical PNP transistor is connected to a potential between a power source and a collector potential. In addition, it is biased with low impedance.

[0005]

Therefore, in the present invention, the problem that the phenomenon of subharmonic distortion of the current push-pull output circuit occurs can be solved, and the reliability of the output circuit can be remarkably improved.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. That is, in the configuration of FIG. 1, reference numeral 26 is a control circuit of the current push-pull output circuit, 27 and 28 are vertical PNP transistors forming the current mirror circuit of the output stage, and 29 and 30 are resistors that determine the mirror ratio of the current mirror circuit. , 31 and 32
Is an NPN transistor that constitutes the output stage current mirror circuit, 33 and 34 are resistors that determine the mirror ratio of the current mirror circuit, 35 is the power supply for this circuit, and 36 is an N-type transistor that constitutes the output stage vertical PNP transistor 28 A terminal taken out from the epitaxial layer, 37 is an NPN transistor for biasing the terminal 36 with a low impedance, 38 is a resistor that determines the idling current of the NPN transistor 37, and 39 and 40 are resistors that determine the bias potential of the terminal 36. . In the present embodiment, the N-type epitaxial layer of the output stage vertical PNP transistor 28 is biased to a low impedance by the NPN transistor 37 and the resistor 38 via the terminal 36, and its potential is determined by the resistors 39 and 40. To be done. Therefore, by making the potential of the N-type epitaxial layer of the output stage vertical PNP transistor 28 higher than the potential of its collector region, the influence of the parasitic transistor is prevented even if a potential gradient occurs in the collector region, and the problem of subharmonic distortion occurs. Be improved. Also, the output stage vertical PN
Since the potential of the N-type epitaxial layer of the P-transistor 28 is determined by the values of the resistors 39 and 40, the N-type epitaxial layer of the output stage vertical PNP transistor 28 is biased with a low impedance so that the breakdown voltage problem does not occur. It is possible.

[0007]

As described above, according to the present invention, in the current push-pull output circuit, the N-type epitaxial layer of the output stage vertical PNP transistor is biased to a potential between the power supply and the collector potential with a low impedance. It is possible to realize an output circuit that solves the problem of subharmonic distortion and the breakdown voltage problem.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a current push-pull output circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a current push-pull output circuit according to a conventional example.

FIG. 3 is a sectional view of a process structure of a vertical PNP transistor according to an embodiment of the present invention and a conventional embodiment.

[Explanation of symbols]

1 Control Circuit 2 Vertical PNP Transistor 3 Output Stage Vertical PNP Transistor 4, 5 Resistor that Determines Current Mirror Ratio 6 NPN Transistor 7 Output Stage NPN Transistor 8, 9 Resistor that Determines Current Mirror Ratio 10 Power Supply 11 Output Stage Vertical PNP Transistor Terminal 12 taken out from N type epitaxial layer 12 P type substrate 13 N type buried layer 14 Element isolation P type region 15, 16 P type collector region 17, 18 N type base region 19 Emitter region 20 N type epitaxial layer 21 Insulating film 22 emitter electrode 23 base electrode 24 collector electrode 25 electrode taken out from the N-type epitaxial layer 20 control circuit 27 vertical PNP transistor 28 output stage vertical PNP transistor 29, 30 current mirror ratio is determined Resistor 31 NPN transistor 32 output stage NPN transistor 33, 34 resistor that determines the current mirror ratio 35 power supply 36 output stage vertical PNP terminal of the PNP transistor taken out from the N type epitaxial layer 37 terminal 36 biasing NPN transistor 38 NPN transistor 37 Idling current setting resistor 39, 40 Bias potential setting resistor

Claims (1)

[Claims] 1. A bipolar integrated circuit in a current push-pull output circuit, wherein an N-type epitaxial layer of an output stage vertical PNP transistor is biased with a low impedance to a potential between a power supply and a collector potential.