JPS626658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential transistor circuit device such as an ECL.

Conventionally, ECL has been common as a high-speed logic circuit. ECL uses bipolar transistors, usually based on a differential transistor pair, and creates a "1" or "0" state in the load by activating one transistor.
In ECL, the current flowing through the differential transistor pair is usually set to a constant value by a current source, so the transistors can be operated in a non-saturated state, allowing very fast logic operations.

OR (NOR) gate and AND using ECL
The basic configuration of a (NAND) gate is shown in Figures 1a and 1b. In both cases, transistors Q ₁₁ to Q ₁₄ and resistors
It consists of R ₁ , R ₂ , and constant current source I. Constant current source I is usually composed of a transistor and a resistor.

By the way, unlike MOS logic circuits, ECL requires element isolation when integrated into a circuit, and the number of elements in the gate circuit is relatively large, so when integrated into an integrated circuit, it occupies a large area and requires constant current flow. There were problems such as the high power consumption required for the flow.

For example, the structure of a transistor constituting a gate circuit as shown in FIG. 1 is normally as shown in FIGS. 2a and 2b. 1 is a p-type Si substrate, 2 is an n-type epitaxial layer serving as a collector, and a p-type base layer 3 and an n ⁺ type emitter layer 4 are provided on this. 5 is an n ⁺ type buried layer, 6 is an n ⁺ type collector terminal extraction layer, and 7
is a p ⁺ type device isolation layer. When the transistors having such a structure are separated into elements and integrally integrated to form, for example, the NAND gate shown in FIG. 1B, the pattern becomes as shown in FIG. 3. Transistor Q ₁₅ and resistor R ₃ of FIG. 3 are used as constant current source I. It can be seen that the shaded area in FIG. 3 is the element isolation region, which occupies a considerable area in the entire integrated circuit.

^I2L was invented and is attracting a lot of attention as a solution to these difficulties with ECL.
I ² L has a slow operating speed and is useless in the ECL operating region.

This invention was made in view of the above points,
The present invention provides a differential transistor circuit device that can significantly reduce the area occupied when integrated into an integrated circuit, and improve reliability and reduce costs.

This invention provides a differential transistor pair used for ECL etc., which has a plurality of base layers and a plurality of emitter layers in the collector layer of one island region of a semiconductor substrate separated from each other, and a plurality of emitter layers from the collector layer. The main idea is to have a composite transistor structure with a lead-out collector terminal.

A composite transistor structure according to an embodiment of the present invention is shown in FIGS. 4a and 4b. In the figure, 11 is p-type Si
The substrate 12 is an n-type epitaxial layer, p ⁺
An n-type epitaxial layer 12 in one island region separated by a type element isolation layer 13 is used as a collector layer, and two independent p-type base layers 14 are formed within the collector layer.
₁ , 14 ₂ are provided, and respective base layers 14 ₁ ,
N ⁺ type emitter layers 15 ₁ and 15 ₂ are provided within 14 ₂ . Between the substrate 11 and the n-type epitaxial layer 12, facing each base layer 14 ₁ , 14 ₂
N ⁺ type buried layers 16 ₁ and 16 ₂ are provided, and the n ⁺ type buried layers 16 ₁ and 1 are respectively provided from the surface.
N ⁺ -type collector terminal extraction layers 17 ₁ and 17 ₂ are formed by diffusion to a depth reaching 6 ₂ to lead out two collector terminals C ₁ and C ₂ . 2 base layers 1
Base terminals B ₁ and B ₂ are led out independently from the base terminals 4 ₁ and 14 ₂ , and an emitter terminal E is led out in common from the two emitter layers 15 ₁ and 15 ₂ .

An equivalent circuit of this composite transistor is shown in FIG. Rs and Cs are the parasitic resistance and parasitic capacitance between the two collectors, respectively. The parasitic resistance Rs is caused by the two n ⁺ type buried layers 16, which are introduced because the two collector terminals C ₁ and C ₂ are taken out from one collector layer.
This is the resistance of the n-type epitaxial layer 12 between ₁ and ₁₆₂ . For example, the parasitic resistance Rs is such that the specific resistance of the n-type epitaxial layer 12 is 2 Ω-cm, the distance between the n ⁺ buried layers 16 ₁ and 16 ₂ is L = 20 μm, and the distance from the p-type substrate 11 to the n ⁺ buried layer 16 ₁ , Assuming that the thickness of the upwardly protruding portion of the layer ₁₆₂ is t=3.5 μm, and the width of the opposing n ⁺ type buried layers 16 ₁ and ₁₆₂ is w=50 μm, Rs=2.2 KΩ in a first-order approximation. This is due to the load resistances R ₁ and R ₂ (usually several tens to
(several hundred Ω). Also, the parasitic capacitance Cs
is composed of a capacitance component inserted between the n ⁺ type buried layers 16 ₁ and 16 ₂ , and its value is about 1 pF. This composite transistor is used as a differential transistor pair in ECL with its commonly connected emitter terminal E.
If it is connected to a constant current source and operated, it will perform non-saturated operation, so there is no need to worry about lateral PNP transistor operation even though two independent base layers are provided in the same epitaxial layer. Furthermore, by separating the two base layers to an extent that punch-through does not occur, the transistors can be operated as two independent transistors.

Equivalent circuits when OR (NOR) gates and AND (NAND) gates are constructed by ECL using such composite transistors are shown in FIGS. 6a and 6b, corresponding to FIGS. 1a and 1b, respectively. The parasitic resistance and parasitic capacitance components mentioned above are ignored. The differential transistor pair Q ₁₁ and Q ₁₂ in Figure 1 is a composite transistor.
Replaces Q ₁₀₁ and similarly uses a differential transistor pair
Q ₁₃ and Q ₁₄ are replaced with a composite transistor Q ₁₀₂ .

A schematic planar pattern when the gate of FIG. 6b is integrated on a semiconductor substrate is shown in FIG.
As shown in the figure. As is clear from a comparison with FIG. 3, by configuring the differential transistor pair as an integrated composite transistor, the occupied area is reduced. The area reduction rate by replacing a differential transistor pair with a single composite transistor is approximately 36%.
The area reduction rate for the entire gate is approximately 23%.
becomes.

Normally, gates using ECL are integrated into a circuit in the form of cascading a number of stages, so this embodiment can significantly reduce the area of an integrated circuit chip. As is clear from FIG. 4, the collector terminals C ₁ and C ₂ of the composite transistor are not completely separated, but are connected by a parasitic resistance Rs. Therefore, the current from the constant current source does not completely flow through the load resistor on the one collector terminal side, but also flows through the load resistor on the collector terminal side in the off state, resulting in a decrease in the off level. However, by differentially extracting the gate output and differentially inputting it to the next stage gate, the output signal can be reliably transmitted.

Incidentally, as a structure similar to the composite transistor shown in FIG. 4, a structure shown in FIG. 8 has been proposed (Japanese Patent Application Laid-Open No. 49-37580). This is applied to the p-type substrate 21.
A p type epitaxial layer 22 is formed, and a p type base layer 24 is formed in an island region surrounded by a p ⁺ type element isolation layer 23.
An n-type emitter layer 25 is provided. Then, two n ⁺ type buried layers 26 ₁ and 26 are provided under the base layer 24.
₂ , and two collector terminals are connected through the n ⁺ type collector terminal extraction layers 27 ₁ and 27 ₂ from each.
C ₁ , C ₂ and one base layer 24
Two base terminals from both sides of the emitter layer 25 of
B ₁ and B ₂ are derived. By making the base width under the emitter layer 25 very narrow, one of the base terminals B ₁ and B ₂ is set to "1" and the other is set to "0", and the collector terminals C 1 and B 2 are set to " ₁ " and the other to "0". It performs switching to put one side of _C2 into an operating state. However, narrowing the base width required to ensure switching operation equivalently leads to an increase in base resistance, which in turn leads to a decrease in operating speed.
In addition, in order to perform the switching operation reliably, it is necessary to make the resistance between the collector terminals C ₁ and C ₂ sufficiently large, and for this purpose, the n ⁺ type buried layer 26 ₁ ,
Although it is necessary to increase the distance between 26 _{and 2} , it is also necessary to increase the width of the emitter layer 25, and as a result, the base resistance becomes even higher. Furthermore, although the base layer 24 is substantially separated into two by the emitter layer 25, the separation is not perfect, so it is difficult to guide electrons injected from the emitter layer 25 only to one collector terminal side. It is.

Furthermore, the base layer 24 and the buried layers 26 ₁ and 26 ₂
are in contact and both impurity layers are highly concentrated, so
Its use is limited because its withstand voltage is much lower than that of normal base and collector voltages.

In contrast, in the embodiment of _the invention shown _{in FIG} . ,15 ₂ are each
Since they are arranged separately on the n ⁺ type buried layers 16 ₁ and 16 ₂ , they have the advantage that a more complete switching operation is possible.

9a and 9b show a composite transistor structure of another embodiment of the invention. In this case, p-type Si
forming an n-type epitaxial layer 32 on a substrate 31;
Two p ^- type base layers 34 ₁ , 34 ₂ are provided in the island region separated by the p + -type element isolation layer 33 , and two n ⁺ -type emitter layers 35 ₁₁ , 2 are provided in each base layer 34 ₁ , 34 ₂ . 35 ₁₂ , 35 ₂₁ , and 35 ₂₂ are provided. 36 ₁ and 36 ₂ are n ⁺ type buried layers, and n ⁺ type collector terminal extraction layers 37 ₁ and 37 ₂ are respectively provided.
Two collector terminals C ₁ and C ₂ are led out through the terminal. Also, as is clear from the figure, the two base layers 34 ₁ and 34 ₂ each have two buried layers 36 .
₁ and 36 ₂ , two emitter layers 35 ₁₁ and 35 ₂₁ are placed on the buried layer 36 ₁ , and another two emitter layers 35 ₁₂ and 35 ₂₂ are placed on another buried layer 36 _2. are placed above each. Then, base terminals B ₁ and B ₂ are led out from the base layers 34 ₁ and 34 ₂ , respectively, and the two emitter layers 35 ₁₁ and 35 ₂₂ are commonly connected to lead out one emitter terminal E ₁ and another two. emitter layer 35 ₂₁ ,
Connect 35 ₁₂ in common and connect another emitter terminal E ₂
is derived.

In this composite transistor, when base terminal B ₁ is set to "1" (high level) and base terminal B ₂ is set to "0" (low level), current flows from collector terminal C 1 to emitter terminal E 1, and at the same time, current flows from collector terminal C ₁ to emitter terminal E ₁ . terminal
Flows from C ₂ to emitter terminal E ₂ . base terminal
When the potentials applied to B ₁ and B ₂ are reversed, current flows from the collector terminal C ₁ to the emitter terminal E ₂ and at the same time flows from the collector terminal C ₂ to the emitter terminal E ₁ .
An equivalent circuit of this composite transistor is shown in FIG. 10, and the manner in which the above-mentioned current flows is shown by solid lines and broken arrows. As is clear from the figure, in this composite transistor, signals to the two base terminals B ₁ and B ₂ cause a connection between the two collector terminals C ₁ and C ₂ and the two emitter terminals E ₁ and E ₂ . Current switching operation is possible.

By combining this composite transistor with the composite transistor of the previous embodiment, an exclusive OR
(NOR) gate can be constructed very easily as shown in FIG. Exclusive OR using traditional ECL
_The (NOR) gate is configured as shown in _{FIG .}
Q ₂₃ , Q ₂₄ and the transistor pair Q ₂₅ , Q ₂₆ are replaced with the composite transistor Q ₂₀₂ of this embodiment.
In Figure 12, the set of transistors Q ₂₃ and Q ₂₅ and the set of transistors Q ₂₄ and Q ₂₆ each have a common collector, so they are made in a common island area, and if the load resistance and constant current source are removed, the island area is There will be 4 pieces. In contrast, in FIG. 11, only two island regions are required, and it can be seen that the area can be significantly reduced.

By variously modifying the way in which the emitter terminals are taken out from the four emitter layers in the embodiment shown in FIG. 9, current switching, etc. can be achieved in various ways as shown in FIGS. 13 a to c compared to FIG. A composite transistor as a function element that performs the following operations is obtained.
FIG. 13a shows the case where the emitter terminal E ₁ is taken out in common from the emitter layers 35 ₁₁ and 35 ₂₁ , and the emitter terminal E ₂ is taken out in common from the emitter layers 35 ₁₂ and 35 ₂₂ , and the same figure b shows the emitter layer 35 ₁₁ , 35 ₁₂ , 35
₂₁ , 35 _{and 22} independently from the emitter terminal E ₁ ~
This is the case when E ₄ is taken out. In these, by selecting base terminals B ₁ and B ₂ , current switching operations as shown by solid lines and broken lines are possible. Also, Fig. 13c shows the case where all four emitter layers are commonly connected and one emitter terminal E is taken out, and no matter which base terminal is selected, two collector terminals are connected.
Both C ₁ and C ₂ become active.

FIGS. 14a and 14b show the structure of a composite transistor according to yet another embodiment of the invention. In this embodiment, three p-type base layers 44 1 to ₄ are formed in island regions separated by a p ⁺ type element isolation layer 43 of an n-type epitaxial layer 42 formed on a p-type Si substrate 41.
4 ₃ is provided, two n ⁺ type emitter layers 45 ₁ , 45 ₂ are provided on the base layer 44 ₁ , and the base layer 44 ₂ ,
44 ₃ and one emitter layer 45 ₃ ,
₄₅₄ is provided. 46 ₁ and 46 ₂ are n ⁺ type buried layers, and collector terminals C ₁ and C ₂ are connected to them through n ⁺ type collector terminal extraction layers 47 ₁ and 47 ₂ , respectively.
is derived. The base layer 44 ₁ at the center is provided so as to span over the two buried layers 46 ₁ and 46 ₂ , and the base layers 44 ₂ and 44 ₃ on both sides thereof are arranged so as to face only the buried layers 46 ₁ and 46 ₂ , respectively. Base terminals B ₁ , B ₂ , and B ₃ are independently led out from each base layer. All the emitter layers are commonly connected to lead out one emitter terminal E.

The equivalent circuit of this composite transistor is shown in FIG. Two buried layers 46 ₁ , 46
The base terminal B ₁ taken out from the central base layer 44 ₁ facing both of ₂ is the main, and by setting this main base terminal B ₁ to "1",
Both collector terminals C ₁ and C ₂ become operational. The remaining base terminals B ₂ and B ₃ are for control, and when B ₂ is set to "1", only one collector terminal C ₁ becomes operational, and when B ₃ is set to "1", the other collector terminal becomes active. Only C ₂ becomes operational.

FIG. 16 is a modification of the pattern of the embodiment shown in FIG. 14, and the basic configuration is the same as that in FIG. 14.
Therefore, portions corresponding to those in FIG. 14 are given the same reference numerals as in FIG. 14, and explanation thereof will be omitted, but the area can be reduced by this pattern modification.

FIG. 17 shows an equivalent circuit of an embodiment in which a master-slave type D flip-flop with a set-reset terminal is integrated into an integrated circuit by combining the composite transistors of the respective embodiments described above. For comparison, an equivalent circuit of a flip-flop with the same function using conventional ECL is shown in FIG. 18, and corresponding parts are given the same reference numerals. Conventional transistor Q ₃₇ ,
Q ₃₈ , Q ₄₃ , and Q ₄₆ are integrated as a composite transistor Q ₃₀₁ of the embodiment shown in FIG. 14 or FIG. 16 shown in the equivalent circuit of FIG. 15, and the transistors Q ₃₅ ,
Q ₃₆ , Q ₄₄ and Q ₄₇ are integrated as a similar composite transistor Q ₃₀₂ , transistors Q ₃₃ and Q ₄₈ are integrated as a composite transistor Q ₃₀₃ of the embodiment shown in FIG. 4, and transistors Q ₃₄ and Q ₄₅ are similarly integrated. It is integrated as a composite transistor Q ₃₀₄ . Further, transistors Q ₃₂ and Q ₄₂ and Q ₃₁ and Q ₄₁ are each combined into one transistor. Thus, the 18th
Compared to the diagram, the configuration shown in FIG. 17 allows a significant reduction in chip area. Furthermore, the structure shown in FIG. 17 has the advantage that the mask pattern has good symmetry and Al wiring is easier to perform than in the conventional structure.

FIG. 19 shows an equivalent circuit when the present invention is applied to a 1/3 prescaler. Using the configuration shown in FIG. 18 as the flip-flops FF ₁ and FF ₂ in the diagram, AND
The configuration described in the equivalent circuit of FIG. 6B is used as the gate, and the larger the circuit scale, the greater the area reduction effect of the present invention becomes.

Figure 20 shows a conventional latch circuit with set-reset, and this configuration is also based on the same principle.
It is possible to form transistors Q ₅₁ to Q ₅₆ in one island region, and a large effect in area reduction can be obtained.

In the above embodiments, an epitaxial layer is used, but the present invention can also be implemented by forming the collector layer by impurity diffusion without using an epitaxial wafer. Furthermore, all the composite transistors in the above embodiments had two collector terminals, but
If necessary, three or more collector terminals may be derived, and the composite transistor may have a PNP structure.

As described in detail above, according to the present invention, the differential transistor pair has a plurality of base layers and a plurality of emitter layers in the collector layer of one island region of a semiconductor substrate, and the collector layer By creating a composite transistor structure with multiple collector terminals derived from the ECL, when various gates, flip-flops, latches, and other circuits based on ECL are integrated into an integrated circuit, the area occupied can be significantly reduced compared to conventional circuits. Moreover, there is no need to add any special process to the conventional bipolar integrated circuit process, and the number of elements and contact holes are reduced, thereby improving the reliability of the integrated circuit and reducing costs.

[Brief explanation of the drawing]

Figures 1a and b are each using conventional ECL.
Diagrams showing OR (NOR) gates and AND (NAND) gates; Figures 2a and b are schematic plan views showing the conventional transistor structure and their E-A cross-sectional views; Figure 3 is a diagram showing the conventional transistor structure. FIG. 4a and b are a schematic plan view showing a composite transistor structure according to an embodiment of the present invention, and a cross-sectional view thereof, and FIG. are equivalent circuit diagrams of the composite transistor, Fig. 6a, b
is also an OR using that composite transistor
An equivalent circuit diagram showing a (NOR) gate and an AND (NAND) gate corresponding to Figures 1a and b, Figure 7 is a plane pattern when the gate in Figure 6b is integrated into an integrated circuit, and Figure 8 is A diagram showing a conventional switching transistor structure similar to the above embodiment, FIG. 9a,
b is a schematic plan view showing a composite transistor structure according to another embodiment of the present invention and its cross-sectional view, FIG. 10 is an equivalent circuit diagram of the composite transistor, and FIG. Equivalent circuit diagram of the constructed exclusive OR (NOR) gate, 12th
Figure shows traditional exclusive OR (NOR) for comparison
13a to 13c are equivalent circuit diagrams of the gate, and FIGS. 13a to 13c are equivalent circuit diagrams of composite transistors as various function elements obtained by modifying the emitter wiring in the above embodiment. FIGS. A schematic plan view and a knee' cross-sectional view showing the composite transistor structure of the example, FIG. 15 is an equivalent circuit diagram of the composite transistor, and FIG. 16 is a diagram of FIG. 14a.
17 is an equivalent circuit diagram of a master-slave type D-type flip-flop with a set-reset terminal constructed by combining the composite transistors shown in the equivalent circuits of FIGS. 5 and 15. Figure 18 is an equivalent circuit diagram of a conventional flip-flop with the same function for comparison, and Figure 19 is an OR of the flip-flop in Figure 17 and Figure 6a.
FIG. 20 is an equivalent circuit diagram of a 1/3 prescaler combining (NOR) gates, and FIG. 20 is an equivalent circuit diagram of a conventional latch circuit to which the present invention is applied to a large effect. 11, 31, 41...p-type Si substrate, 12, 32,
42...n-type epitaxial layer, 13, 33, 43
...p ⁺ type element isolation layer, 14 ₁ , 14 ₂ , 34 ₁ ,
34 ₂ , 44 ₁ , 44 ₂ , 44 ₃ ... p-type base layer, 15 ₁ , 15 ₂ , 35 ₁₁ , 35 ₁₂ , 35 ₂₁ ,
35 ₂₂ , 45 ₁ , 45 ₂ , 45 ₃ ... n ⁺ type emitter layer, 16 ₁ , 16 ₂ , 36 ₁ , 36 ₂ , 46 ₁ ,
46 ₂ ... n ⁺ type buried layer, 17 ₁ , 17 ₂ , 37
₁ , 37 ₂ , 47 ₁ , 47 ₂ ... n ⁺ type collector terminal extraction layer, C ₁ , C ₂ ... collector terminal, B ₁ , B ₂ ,
B ₃ ... Base terminal, E, E ₁ , E ₂ , E ₃ , E ₄ ... Emitter terminal, Q ₁₀₁ , Q ₁₀₂ , Q ₂₀₁ , Q ₂₀₂ , Q ₃₀₁ , Q ₃₀₂ ,
Q ₃₀₃ , Q ₃₀₄ ...Composite transistor.

Claims (1)

[Claims] 1. In a differential transistor circuit device having a differential transistor pair as a constituent element, the differential transistor pair includes a plurality of bases in a collector layer of one island region separated from elements of a semiconductor substrate. and a plurality of emitter layers, a plurality of collector terminals are derived from the collector layer, base terminals are derived from each of the base layers, and an emitter terminal is commonly derived from each of the emitter layers. A differential transistor circuit device characterized by: 2 The composite transistor structure has 2 layers in the collector layer.
A collector terminal is led out from each buried layer via a high concentration collector terminal extraction layer, and a base layer is provided on each of the buried layers, and a base terminal is led out from each base layer. 2. The differential transistor circuit device according to claim 1, wherein an emitter layer is provided in each of said base layers, and an emitter terminal is commonly led out from each emitter layer. 3 The composite transistor structure has two
A collector terminal is led out from each buried layer through a high concentration collector terminal extraction layer, and two base layers are provided so as to span over the two buried layers, and each base A base terminal is led out from each layer, an emitter layer is provided at a position facing each of the buried layers in each base layer, and an emitter terminal is led out from each emitter layer by common connection by an appropriate combination. A differential transistor circuit device according to claim 1. 4 The composite transistor structure has two
A number of high-concentration buried layers are provided, and a collector terminal is led out from each buried layer via a high-concentration collector terminal extraction layer, and one base layer disposed so as to straddle the two buried layers and each of the above-mentioned Two base layers are provided so as to face each of the buried layers, a base terminal is led out from each base layer, and an emitter layer is provided at a position facing each of the buried layers in each of the base layers. 2. The differential transistor circuit device according to claim 1, wherein an emitter terminal is commonly derived from each emitter layer.