JPH09307000A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent generation of latch-up without making large the size of a complementary field-effect transistor semiconductor device, even when a high voltage or noise is applied to the transistor semiconductor device from the exterior. SOLUTION: Guard band regions 53 and 54 connected to a source region of a field-effect transistor are provided in parallel to each other and apart from each other in a region where field-effect transistors 13 and 14 of different channel polarities are opposed to each other. Therefore, a latch-up preventing function can sufficiently exhibit without increasing its chip size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, and more particularly to a complementary field effect transistor semiconductor device which is provided with a measure for preventing latch-up.

[0002]

2. Description of the Related Art In a complementary field effect transistor semiconductor device having N-channel and P-channel field effect transistors, bipolar transistors are parasitically present due to its structure, and these bipolar transistors form a thyristor structure circuit. I am configuring.

Therefore, when the circuit of the thyristor structure is turned on for some reason such as a high voltage or noise from the outside, an excessive power supply current flows. Once this excessive power supply current flows, the current continues to flow even if the cause of turning on the circuit of the thyristor structure is removed.

In addition, since many parasitic bipolar transistors are turned on and flow, the current value becomes several ten times as large as the power supply current during normal operation, which may cause fusing of metal wiring or destruction of junction. And eventually the complementary field effect transistor semiconductor device is damaged. This phenomenon is called latch-up, and measures to prevent this latch-up are essential for the complementary field effect transistor semiconductor device.

In general, latch-up is often triggered by a high voltage or noise externally applied to an input / output terminal or a power supply terminal of a complementary field effect transistor semiconductor device.

Next, a latch-up generating mechanism will be described with reference to the drawings. FIG. 3 is a sectional view schematically showing a complementary field effect transistor semiconductor device for explaining latch-up, and FIG. 4 shows a bipolar transistor parasitically present in the complementary field effect transistor semiconductor device shown in FIG. It is an equivalent circuit diagram showing a thyristor structure.

The structure of the complementary field effect transistor semiconductor device will be described with reference to the sectional view shown in FIG. As shown in FIG. 3, a P-channel field effect transistor 13 is formed on an N-type semiconductor substrate 20, and an N-channel field effect transistor 14 is formed on a P-type well region 21 formed on the N-type semiconductor substrate 20. Then, a complementary field effect transistor circuit is configured.

Since these complementary field effect transistor circuits form P-type and N-type impurity diffusion regions on the same semiconductor substrate, they are parasitically connected to the PNP-type bipolar transistor Q1 and the PNP-type bipolar transistor Q2.
There are a PN type bipolar transistor Q3 and an NPN type bipolar transistor Q4. Further, a resistance r1 and a resistance r2 are parasitically present in the N-type semiconductor substrate 20 and the P-type well region 21, respectively.

Further, a PNP type bipolar transistor Q1
And the collectors of the PNP type bipolar transistor Q2 and the bases of the NPN type bipolar transistor Q3 and the NPN type bipolar transistor Q4 form the P type well region 12, and similarly the PNP type bipolar transistor Q is formed.
The base of 1 and the PNP type bipolar transistor Q2 and the collectors of the NPN type bipolar transistor Q3 and the NPN type bipolar transistor Q4 serve as an N type semiconductor substrate 20 to form a thyristor structure circuit.

The operation of the circuit having the thyristor structure will be described below with reference to the sectional view of FIG. 3 and the equivalent circuit diagram of the thyristor structure of FIG. First, the case where a high voltage or noise from the outside is applied to the OUT terminal will be described.

When a voltage higher than the power supply VDD is applied to the OUT terminal shown in FIG. 4, the drain region of the P-channel field effect transistor 13 shown in FIG.
A current flows through the emitter and base of the NP-type bipolar transistor Q2, and the emitter and collector are electrically connected. As a result, a current flows through the resistor r2 and a voltage is generated across the resistor r2.

The voltage generated across the resistor r2 becomes the base potential of the NPN bipolar transistor Q3, and this base potential rises in the positive direction to turn on the NPN bipolar transistor Q3.

When a current flows through the NPN type bipolar transistor Q3, a voltage is generated across the resistor r1, that is, the base potential of the PNP type bipolar transistor Q1 drops and the PNP type bipolar transistor Q1 is turned on.

Therefore, a current flows through the emitter and base of the PNP bipolar transistor Q1 and the resistor r2, a voltage is again generated across the resistor r2, and the NPN is generated.
Type bipolar transistor Q3 is maintained in the ON state,
Even if the voltage applied to the UT terminal is removed, an excessive current continues to flow between the power supply VDD and the power supply VSS.

When a voltage lower than the power supply VSS is applied to the OUT terminal, the drain region of the N-channel field effect transistor 14 is forward biased, and a current flows through the base and emitter of the NPN bipolar transistor Q4.
Conduction occurs between the emitter and the collector. This makes the resistance r
1, a current flows, a voltage is generated across the resistor r1, and P
The NP type bipolar transistor Q1 is turned on.

As a result, a voltage is generated across the resistor r2 and the NPN bipolar transistor Q3 is turned on.
For this reason, a voltage is again generated across the resistor r1, and the PNP bipolar transistor Q1 is maintained in the ON state.
Even if the voltage applied to the T terminal is removed, an excessive current continues to flow between the power supply VDD and the power supply VSS.

That is, in this state, the power supply V is supplied to the OUT terminal.
Similar to the case of applying a voltage equal to or higher than DD, the collector currents of the NPN bipolar transistor Q3 and the PNP bipolar transistor Q1 supply the base currents to each other, and the currents continue to flow until the power is turned off.

The mechanism of latch-up generation is not limited to the above description, but many factors can be considered. Next, a case where a high voltage or noise from the outside is applied to the power supply will be described.

When a high positive voltage or noise is applied to the power supply VDD, the source region of the P-channel field effect transistor 13 and the N-type semiconductor substrate 20 are forward biased, and the emitter and base of the PNP-type bipolar transistor Q1 are connected. , A current flows between the emitter and the collector, a current flows through the resistor r2, and a voltage is generated across the resistor r2. Latch-up occurs through the same process as in the case of applying a voltage higher than the power supply VDD to the OUT terminal described above.

Furthermore, when a high negative voltage, noise, or the like is applied to the power supply VSS, the source region of the N-channel field effect transistor 14 and the P-type well region 21 are forward biased, and the NPN-type bipolar transistor Q.
A current flows through the base and the emitter of 3, the collector and the emitter conduct, and the current flows through the resistor r1 and the resistor r
A voltage is generated across 1. Latch-up occurs through the same process as in the case of applying a voltage equal to or lower than the power supply VSS to the OUT terminal described above.

In either case, current flows in the N-type semiconductor substrate 20 or P-type well region 21 of the complementary field effect transistor semiconductor device, and the internal resistance r
When the voltage drop between 1 and the resistor r2 exceeds a certain limit value, latch-up occurs.

According to the equivalent circuit diagram of FIG. 4, the voltage value at which the voltage across the resistors r1 and r2 becomes equal to the base-emitter voltage VBE between the PNP type bipolar transistor Q1 and the NPN type bipolar transistor Q3 is constant. It becomes the limit value. This is one of the conditions for the occurrence of latch-up.

Many means have been proposed to prevent this latch-up. Two latch-up prevention means will be described below.

The first latch-up prevention means prevents latch-up by making it difficult to turn on the bipolar transistor itself which constitutes the thyristor structure circuit.

Specifically, the region in which the P-channel field effect transistor is installed and the region in which the N-channel field effect transistor is installed, which constitutes each circuit in the complementary field effect transistor semiconductor device, are separated from each other.

Explaining with reference to FIG. 3, the P-channel field effect transistor 13 and the N-channel field effect transistor 14 are separated from each other.

As a result, the PNP-type bipolar transistors Q1 and PN which exist parasitically in FIGS.
The width of the base region with the P-type bipolar transistor Q2,
In other words, the distance between the drain region of the P-channel field effect transistor 13 and the P-type well region 21 is increased, and the resistance component of the collectors of the NPN bipolar transistor Q3 and the NPN bipolar transistor Q4 is increased. This makes it difficult to turn on the bipolar transistor in the process in which the complementary field effect transistor semiconductor device shifts to latch-up.

However, since the latch-up prevention means separates the region in which the P-channel field effect transistor is installed from the region in which the N-channel field effect transistor is installed, the area occupied by the complementary field effect transistor circuit is increased. Grows. Therefore, there is a problem that the area of the entire complementary field effect transistor semiconductor device increases.

Next, the second means for preventing latch-up is
Latch-up is prevented by absorbing carriers that are injected into the semiconductor substrate or the well region of the complementary field effect transistor semiconductor device. This will be described with reference to the drawings.

FIG. 5 is a plan view schematically showing a complementary field effect transistor semiconductor device for explaining a conventional latch-up prevention means, and FIG. 6 is a cutting line B shown in FIG.
It is sectional drawing which shows a mode that it cut | disconnected by -B. Figure 7
FIG. 7 is an equivalent circuit diagram showing a thyristor structure using bipolar transistors parasitically present in the complementary field effect transistor semiconductor device shown in FIG. 6.

As shown in FIGS. 5 and 6, the P-channel field-effect transistor 13 and the N-channel field-effect transistor 14 have an N-type guard ring region 3 and a P-type field effect transistor 14, respectively.
It is surrounded by the guard ring region 4 of the mold.

The source region 25 of the P-channel field effect transistor 13 and the N-type guard ring region 3 are connected to a power supply VDD (not shown) by a metal wiring 8, and the source region 28 of the N-channel field effect transistor 14 is connected. The P-type guard ring region 4 is connected to a power supply VSS (not shown) by a metal wiring 9.

The gate electrode 24 of the P-channel field effect transistor 13 and the N-channel field effect transistor 1
4 is connected to the gate electrode 29 by the metal wiring 6 and is connected to the drain region 23 of the P-channel field effect transistor 13 and N
The drain region 30 of the field effect transistor of the channel is connected by the metal wiring 11.

As shown in FIG. 6, PNP type bipolar transistor Q1 and PNP type bipolar transistor Q2.
The connection between the NPN type bipolar transistor Q3, the NPN type bipolar transistor Q4, and the resistors r1 and r2 is parasitically present in the complementary field effect transistor semiconductor device as shown in FIG.

The resistor r11 is parasitically present between the N type guard ring region 3 and the N type semiconductor substrate 20, and the resistor r22 is the P type guard ring region 4 and the P type second well region. It exists parasitically between 21 and 21.

As shown in FIG. 7, the resistors r1 and r11 are
Are connected in parallel, and the resistors r2 and r22 are connected in parallel.

For example, when a high voltage or noise from the outside is applied to the metal wiring 11, the drain region 23 of the P-channel field effect transistor 13 or the N-channel field effect is selected depending on the polarity of the applied high voltage or noise. Either of the drain regions 30 of the transistor 14 is forward biased.

That is, either the PNP type bipolar transistor Q2 or the NPN type bipolar transistor Q4 is turned on and a current is passed through the N type semiconductor substrate 20 or the P type well region 21.

Normally, the current flowing through the N-type semiconductor substrate 20 or the P-type well region 21 reaches the resistor r1 or the resistor r2, and a voltage is generated across both ends of the resistor to cause the conventional latch-up. By following the current transmission path as described in the state, a current is caused to flow in the thyristor structure circuit constituted by the PNP type bipolar transistor Q1 and the NPN type bipolar transistor Q3 to shift to the latch-up state.

However, the P-channel field effect transistor 13 and the N-channel field effect transistor 14 shown in FIGS. 5 and 6 are surrounded by the N-type guard ring region 3 and the P-type guard ring region 4, respectively. It is surrounded.

Therefore, as shown in FIG. 7, the resistors r1 and r11 are parallel resistors, and the resistors r2 and r2 are also connected.
Both are parallel resistors.

Therefore, the resistance r1 is generated by the current flowing in the N type semiconductor substrate 20 or the P type well region 21.
Alternatively, the voltage generated across the resistor r2 does not exceed the base-emitter voltage VBE of the PNP type bipolar transistor Q1 or the NPN type bipolar transistor Q3 and does not cause latch-up.

That is, the carriers to be injected are connected to the N-type guard ring region 3 connected to the power supply VDD and the power supply VSS before reaching the N-type semiconductor substrate 20 or the P-type well region 21 facing each other. It is absorbed by the P-type guard ring region 4.

Furthermore, when a high voltage or noise from the outside is applied to either the source region 25 of the P-channel field effect transistor 13 or the source region 28 of the N-channel field effect transistor 14, latch-up is similarly performed. Will never occur.

[0045]

However, the latch-up prevention means includes a P-channel field-effect transistor 13 and an N-channel field-effect transistor 14, which are the N-type guard ring region 3 and the P-type guard ring, respectively. The area 4 surrounds the periphery.

Therefore, the guard ring region itself needs to be installed around the field effect transistor, and the chip size of the complementary field effect transistor semiconductor device becomes large. This is against the method of reducing the cost by miniaturizing the element such as the field effect transistor and is not preferable.

In order to solve these problems, an object of the present invention is to reduce the chip size of the complementary field effect transistor semiconductor device even when a high voltage or noise from the outside is applied to the complementary field effect transistor semiconductor device. A semiconductor device that prevents the occurrence of latch-up without increasing the size.

[0048]

In order to achieve the above object, the semiconductor device of the present invention employs the semiconductor device as described below.

The semiconductor device of the present invention is a semiconductor device having a field effect transistor circuit composed of a first field effect transistor and a second field effect transistor, the semiconductor device being opposite to the source region of the first field effect transistor. A first guard band region of conductivity type and a source region of the second field effect transistor and a second guard band region of opposite conductivity type are provided to extend the source region of the first field effect transistor. The first field effect transistor and the second field effect transistor face each other by connecting to the first guard band region, extending the source region of the second field effect transistor and connecting to the second guard band region. It is characterized in that a first guard band region and a second guard band region are installed in parallel in the region.

The semiconductor device of the present invention is a semiconductor device having a field effect transistor circuit composed of a first field effect transistor and a second field effect transistor, the semiconductor device being opposite to the source region of the first field effect transistor. A first guard band region of conductivity type and a source region of the second field effect transistor and a second guard band region of opposite conductivity type are provided, and a first guard band region is provided as compared with the source region of the first field effect transistor. The band area is deep,
Compared to the source region of the second field effect transistor, the second
Of the second field effect transistor is extended by extending the source region of the first field effect transistor and connecting to the first guard band region of the second field effect transistor. Connected to the guard band area of
It is characterized in that the first guard band region and the second guard band region are arranged in parallel and at a distance from each other in a region where the first field effect transistor and the second field effect transistor face each other.

In the semiconductor device of the present invention, a guard band region having a conductivity type opposite to that of the source region of the field effect transistor is provided, and the source region of the field effect transistor is extended and connected to this guard band region.

Further, in the semiconductor device of the present invention, the guard band regions are provided respectively for the P-channel field effect transistor and the N-channel field effect transistor, and the P-channel field effect transistor and the N-channel field effect transistor are mutually provided. These two guard band areas are installed in parallel with each other and in the area facing each other.

Thus, in the present invention, the P-channel field effect transistor and the N-channel field effect transistor are separated by the N-type guard band region and the P-type guard band region.

Even when a high voltage or noise from the outside is applied to the complementary field effect transistor semiconductor device, P
By disposing two guard band regions in regions where the channel field effect transistor and the N channel field effect transistor face each other, carriers injected into the semiconductor substrate or the well region are absorbed by these two guard band regions. Has become. As a result, in the semiconductor device of the present invention, the latch-up generation condition is not satisfied, and the latch-up generation can be suppressed.

Further, in the present invention, the guard band region is provided between the complementary field effect transistor circuit and the field effect transistors having different polarities, without surrounding the entire periphery thereof. Therefore, the area used for the means for preventing latch-up is small. Therefore, the increase in the area of the complementary field effect transistor circuit can be minimized, and the latch-up can be prevented without increasing the chip size of the semiconductor device.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a plan view schematically showing a complementary field effect transistor semiconductor device according to an embodiment of the present invention.

First, the structure of the complementary field effect transistor semiconductor device of the present invention will be described with reference to FIG. A P-channel first field effect transistor 13 is provided on the N-type semiconductor substrate 20, and an N-channel second field effect transistor 14 is provided on the P-type well region 21 provided on the N-type semiconductor substrate 20.

The N-type first guard band region 53 is provided on the semiconductor substrate 20 having the N-type conductivity, and the P-type second guard band region 54 is provided on the P-type first well region 21.

First guard band region 53 having N type
And the second guard band region 54 having P type are parallel to and spaced from each other in the region where the P-channel first field effect transistor 13 and the N-channel second field effect transistor 14 face each other. Set up.

First guard band region 53 having N type
The second guard band region 54 having the P-type and the P-type is provided in a region other than the region where the P-type first field effect transistor 13 and the N-type second field effect transistor 14 face each other, and each is provided with the metal wiring 8 And below the metal wiring 9.

The N-type first guard band region 5 provided in the region where the P-type first field effect transistor 13 and the N-type second field effect transistor 14 face each other.
3 and the P-type second guard band region 54, P
A boundary between the well region 21 of the type and the semiconductor substrate 20 of the N type is provided. That is, the N-type first guard band region 53 and the P-type second guard band region 54 are provided so as to face each other with the boundary between the P-type well region 21 and the N-type semiconductor substrate 20 sandwiched therebetween.

The N type first guard band region 53 has the same impurity concentration as that of the N type source region 28 constituting the N type second field effect transistor 14, and the P type second region.
The guard band region 54 is formed with the same impurity concentration as that of the P type source region 25 forming the P type first field effect transistor 13.

Next, the structure of the semiconductor device according to the embodiment of the present invention will be further described while explaining the connection state of each component. The P-channel first field effect transistor 13 includes a P-type drain region 23, a gate electrode 24, and a P-type drain region 23.
And a P-type source region 25.
Extends from the P-channel first field effect transistor 13 and is connected to the N-type first guard band region 53.

In the field effect transistor, in addition to the source region, the drain region and the gate electrode, a bulk region which is a region of the same conductivity type as the semiconductor substrate or the well is provided in order to determine the potential of the semiconductor substrate or the well forming the channel. . For example, in the case of an N type field effect transistor, a P type bulk region is provided.

The N-type first guard band region 53 is provided for the same purpose as the bulk region of the field effect transistor, and the N-type first guard band region 53 and the P-type source region 25 are made of metal. Connected by wiring 8, zero V
It is connected to a power supply VDD (not shown) that supplies the potential of.

The P type source region 25 is the first of the P channel.
Since it is extended from the field effect transistor 13 and connected to the N-type first guard band region 53, a PN junction can be formed at these connection portions, but since it is connected to each other by the metal wiring 8, the P-type source region 25 is formed. And the N-type first guard band region 53 are kept at the same potential.

The N-channel second field effect transistor 14 includes an N-type drain region 30, a gate electrode 29 and an N-type drain region 30.
And the N-type source region 28.
Extends from the N-channel second field effect transistor 14 and is connected to the P-type second guard band region 54.

The P-type second guard band region 54 is provided for the same purpose as the bulk region of the field effect transistor, and the P-type second guard band region 54 and the N-type source region 28 are made of metal. It is connected by a wiring 9 and is connected to a power source VSS (not shown) which supplies a potential of −3V.

The N-type source region 28 is the second N-channel region.
Since it is extended from the field effect transistor 14 and is connected to the P-type second guard band region 54, a PN junction can be formed at these connection portions, but since it is connected to each other by the metal wiring 9, the N-type source region 28 is formed. And the P-type second guard band region 54 are kept at the same potential.

The gate electrode 24 of the P-channel first field effect transistor 13 and the gate electrode 29 of the N-channel second field effect transistor 14 are connected by the metal wiring 6, and the P-channel first field effect transistor is formed. 13 P
The drain region 23 of the N type and the N type drain region 30 of the second field effect transistor 14 of the N channel are connected by the metal wiring 11.

With this structure, the power supply VDD and the power supply VSS
Comprising a P-channel first field-effect transistor 13 and an N-channel second field-effect transistor 14 which operate at a potential between and, and a complementary field-effect transistor.

Next, the operation of the complementary field effect transistor semiconductor device of the present invention will be described. In the complementary field effect transistor semiconductor device of the present invention, a bipolar transistor and a resistor are parasitically present in the structure, and a thyristor structure circuit is formed. Since the connection state of the circuit of this thyristor structure is the same as that in FIG. 7, the operation will be described with reference to FIGS. 1 and 7.

The P-type source region 25 of the P-channel first field effect transistor 13 is used as an emitter, the N-type semiconductor substrate 20 is used as a base, and the P-type first well region 2 is used.
PNP type bipolar transistor Q having 1 as a collector
1 and an NPN-type bipolar transistor having the N-type source region 28 of the N-channel second field effect transistor 14 as an emitter, the P-type first well region 21 as a base, and the N-type semiconductor substrate 20 as a collector. There is a transistor Q3.

Further, a PNP having the P type drain region 23 of the P channel first field effect transistor 13 as an emitter, the N type semiconductor substrate 20 as a base, and the P type first well region 21 as a collector. Type bipolar transistor Q2 and the N-type drain region 30 of the N-channel second field effect transistor 14 are used as emitters,
There is an NPN-type bipolar transistor Q4 having the P-type first well region 21 as a base and the N-type semiconductor substrate 20 as a collector.

The resistor r1 is provided on the N-type semiconductor substrate 20,
In the P-type first well region 21, the resistance r2 and the N-type first well region 21 are provided.
A resistance r11 between the guard band region 3 and the N-type semiconductor substrate 20 and a resistance r22 between the P-type second guard band region 4 and the P-type first well region 21, respectively. .

When a high voltage, noise, or the like from the outside is applied to the metal wiring 11 shown in FIG. 1, the P-type drain of the P-channel first field effect transistor 13 depends on the polarity of the high voltage, the noise, or the like to be applied. Either the region 23 or the N-type drain region 30 of the N-channel second field effect transistor 14 is forward biased.

That is, either the PNP type bipolar transistor Q2 or the NPN type bipolar transistor Q4 is turned on to turn on the N type semiconductor substrate 20 or the P type first substrate.
An electric current is applied to the well region 21 of.

However, in the regions where the P-channel first field effect transistor 13 and the N-channel second field effect transistor 14 shown in FIG. Since the second guard band region 54 of the mold is installed in parallel and at a distance from each other, the resistors r1 and r11 shown in FIG. 7 are parallel resistors, and the resistors r2 and r22 are also parallel resistors. Become.

Therefore, the voltage generated across the resistor r1 or the resistor r2 by the current flowing in the N-type semiconductor substrate 20 or the P-type first well region 21 is PN.
Base-emitter voltage VBE of the P-type bipolar transistor Q1 or the NPN-type bipolar transistor Q3
Latch-up does not occur without exceeding.

That is, the carrier to be injected is N
-Type semiconductor substrate 20 or P-type first well region 2
Before reaching 1, it is absorbed by the N-type first guard band region 53 connected to the power supply VDD and the P-type second guard band region 54 connected to the power supply VSS.

Furthermore, an external high voltage is applied to either the P-type source region 25 of the P-channel first field effect transistor 13 or the N-type source region 28 of the N-channel second field effect transistor 14. Similarly, even when noise or the like is applied, latch-up does not occur.

The complementary field effect transistor circuit that constitutes the complementary field effect transistor semiconductor device of the present invention is
A P-type guard band region and an N-type guard band region, which are connected to regions where the P-channel field effect transistor and the N-channel field effect transistor face each other so as to extend from the source region of each channel polarity field effect transistor. Is provided.

Further, since this guard band region is provided under the metal wiring for power supply as shown in FIG. 1, in comparison with the latch-up prevention measure of providing the guard ring region around the field effect transistor in the prior art, Even if the latch-up prevention measures are taken, the increase in size of the field effect transistor can be minimized.

Although the configurations of the embodiments of the present invention have been described above, the present invention is not limited to these configurations. Different embodiments of the present invention will be described below with reference to FIG.

FIG. 2 is a sectional view schematically showing a state of cutting along the cutting line AA shown in FIG. In FIG. 2, illustration of the metal wiring 8 and the metal wiring 9 is omitted.

As shown in FIG. 2, the N-type first guard band region 53 and the P-type source region 25 forming the P-channel first field effect transistor 13 have different depths.

The depth L2 of the N-type first guard band region 53 may be larger than the depth L1 of the P-type source region 25.

Similarly, the P-type second guard band region 54
And the N-type source region 28 forming the N-channel second field-effect transistor 14 has a different depth, and is different from the depth L3 of the N-type source region 28 in comparison with the P-type second guard 28. The structure may be such that the depth L4 of the band region 54 is larger.

That is, the depth dimension of the guard band region does not have to be the same as the depth dimension of the source region forming the field effect transistor.

In order to absorb the injected carriers efficiently, the N-type first guard band region 53 and the P-type second guard band region 53 are formed.
It is desirable that the depth L2 and the depth L4 of the region forming the guard band region 54 of 4 are large. That is, it is better to form deep in the semiconductor substrate, and this structure can well absorb the semiconductor substrate and carriers injected into the well.

The method of manufacturing the complementary field effect transistor semiconductor device in this case will be briefly described. In general, a semiconductor substrate is covered with a resist mask, impurities are selectively introduced, and then a diffusion region is formed by a thermal diffusion process. It can be easily manufactured using a conventional method.

By the way, the selective introduction of impurities into the semiconductor substrate to form the source region, the drain region, the bulk region, or the guard band region of the field effect transistor can be easily performed by a general manufacturing method. it can.

As an example, the semiconductor substrate is covered with a resist mask, impurities are selectively introduced into desired positions on the semiconductor substrate, and an impurity diffusion region is formed in the semiconductor substrate by a heat diffusion step of applying heat to the semiconductor substrate. make.

There are some means for increasing the depth dimension, that is, the depth dimension from the surface of the semiconductor substrate, in the process of forming the guard band region, the source region forming the field effect transistor, and the like.

For example, in the step of introducing impurities,
In order to implant the impurity ions, the acceleration energy applied to the impurity ions is increased to implant the impurity ions deeper from the front surface to the back surface of the semiconductor substrate, or heat is applied to the impurity-doped semiconductor substrate to diffuse the impurities into the semiconductor substrate. In the thermal diffusion step, there is a method of lengthening the thermal diffusion time of impurities, a method of increasing the temperature applied to the semiconductor substrate in this thermal diffusion step, and the like.

These methods are known general manufacturing methods and are not special. By using these methods, the depth dimension of the guard band region and the source region forming the field effect transistor can be arbitrarily created.

Also, the width dimension of the guard band region can be freely changed according to the installation state of the circuit when laying out the field effect transistor circuit.

That is, if there is a margin in the region where the field effect transistor circuit is provided, the width of the guard band region can be increased to more absorb the carriers flowing in the semiconductor substrate or the well.

Furthermore, in the embodiment of the present invention, the semiconductor substrate has been described as an N type semiconductor substrate. However, even if a P type semiconductor substrate is used, a complementary field effect transistor semiconductor device having the features of the present invention is provided. Can be configured. In any case, various modifications can be made without departing from the spirit of the present invention.

[0100]

As described above based on the embodiments, the present invention takes into consideration the paths of entry and transmission of high voltage and noise from the outside in the complementary field effect transistor semiconductor device, and the different channel polarities. A guard band region is provided between the field effect transistor and the field effect transistor to prevent latch-up from occurring.

A guard band region of the opposite conductivity type to the source region of the field effect transistor is provided, and the source region of the field effect transistor is extended and connected to this guard band region.

The P-channel field effect transistor and the N-channel field effect transistor are each provided with this guard band region, and the two guard band regions are arranged in parallel in a region where field effect transistors having different channel polarities face each other, and Install separately.

As a result, the P-channel field effect transistor and the N-channel field effect transistor are separated by the N-type guard band region and the P-type guard band region.

Complementary Field Effect Transistor Even when a high voltage or noise from the outside is applied to the semiconductor device, by providing two guard band regions in regions where field effect transistors of different channel polarities face each other, the semiconductor substrate Alternatively, carriers injected into the well region are absorbed by these two guard band regions, and the occurrence of latch-up can be suppressed.

Furthermore, the guard band region is provided between the field effect transistors having different channel polarities or under the power supply wiring without surrounding the entire periphery of the complementary field effect transistor circuit.

That is, it is not necessary to surround the entire periphery of the field effect transistor like the guard ring region provided around the field effect transistor in the prior art and spaced apart from the field effect transistor.

For this reason, since the source region of the field effect transistor is extended and connected to the guard band region, the area used for the means for preventing latch-up is extremely small as compared with the guard ring region in the prior art, and the complementary field effect is obtained. It is possible to minimize the increase in the area of the field effect transistor, even though the transistor circuit is provided with a latch-up prevention measure.

In other words, as a method of preventing latch-up, it is possible to exert a sufficient function without increasing the chip size, to provide high reliability and high latch-up resistance, and its effect is extremely high. Is very large.

[Brief description of drawings]

FIG. 1 is a plan view showing a planar pattern shape of a complementary field effect transistor semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a partial region of a complementary field effect transistor semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a complementary field effect transistor semiconductor device according to a conventional technique.

FIG. 4 is a circuit diagram showing an equivalent circuit of a thyristor structure including bipolar transistors parasitically present in a complementary field effect transistor semiconductor device according to a conventional technique.

FIG. 5 is a plan view showing a complementary field effect transistor semiconductor device according to a conventional technique.

FIG. 6 is a cross-sectional view showing a complementary field effect transistor semiconductor device according to a conventional technique.

FIG. 7 is a circuit diagram showing an equivalent circuit of a thyristor structure using bipolar transistors parasitically present in the field effect transistor circuit of the complementary field effect transistor semiconductor device of the present invention and the prior art.

[Explanation of symbols]

 8 metal wiring 9 metal wiring 13 first field effect transistor 14 second field effect transistor 20 semiconductor substrate 21 first well region 53 first guard band region 54 second guard band region

Claims (2)

[Claims] 1. A semiconductor device having a field-effect transistor circuit comprising a first field-effect transistor and a second field-effect transistor, the first device having a conductivity type opposite to that of a source region of the first field-effect transistor. A guard band region and a second guard band region having a conductivity type opposite to that of the source region of the second field effect transistor are provided, and the source region of the first field effect transistor is extended to extend to the first guard band region. And extending the source region of the second field effect transistor and connecting to the second guard band region, the first guard in a region where the first field effect transistor and the second field effect transistor face each other. In parallel with the band region and the second guard band region,
A semiconductor device characterized by being installed separately. 2. A semiconductor device having a field-effect transistor circuit including a first field-effect transistor and a second field-effect transistor, the first device having a conductivity type opposite to a source region of the first field-effect transistor. A guard band region and a second guard band region having a conductivity type opposite to that of the source region of the second field effect transistor are provided, and the depth of the first guard band region is larger than that of the source region of the first field effect transistor. The depth of the second guard band region is deeper than that of the source region of the second field effect transistor. The source region of the first field effect transistor is extended and connected to the first guard band region. , The source region of the second field effect transistor is extended and connected to the second guard band region, and the first field effect transistor and the second field effect transistor are connected. A semiconductor device in which a first guard band region and a second guard band region are arranged in parallel and at a distance from each other in a region where the transistors face each other.