KR19980023935A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit which is not destroyed is obtained even when the direct current power source is connected by reversing the polarity.

In a semiconductor integrated circuit comprising a bipolar IC, a DC power supplied from the outside is supplied to each element of the bipolar IC through a pnp transistor, and a base current of the same magnitude as that of the pnp transistor operates in a saturation region And at the same time, prevents the breakdown of each element when the direct current power source is connected by reversing the polarity.

Description

Semiconductor integrated circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a protection circuit against reverse connection in a semiconductor integrated circuit comprising a bipolar IC.

10 is a circuit diagram showing a part of a conventional semiconductor integrated circuit.

10, the collector of the npn transistor 81 is connected to the power supply terminal Vcc to which DC power is supplied from the outside, and the emitter of the transistor 81 is connected to the collector of the npn transistor 81 and is grounded through the p-type diffusion resistor 82.

The base of the transistor 81 is connected to the base of the pnp transistors 83 and 84 respectively and the emitters of the pnp transistors 83 and 84 are connected to the power supply terminal Vcc, And the collector are connected.

Here, a case in which the DC power source is connected with the polarity reversed in the circuit shown in Fig. 10 will be described.

FIG. 11 is a cross-sectional view of the npn transistor 81, showing the state in which the DC power supply is connected with the polarity reversed.

In Figure 11, npn transistor 81 is formed on the p-type silicon substrate (90), n ⁺ buried layer (91), n ^_ epitaxial layer (92), p-type diffusion layer 93 forming the base, forming the emitter n ⁺ diffusion layer 94, and made of an n ⁺ diffusion layer 95 forming the contact part of the collector, the n ^_ epitaxial layer 92 and the n ⁺ diffusion layer 95 forms the collector.

and a p-type silicon substrate (90), n-type region formed in the n ⁺ buried layer 91 and the n ^_ epitaxial layer 92 and the n ⁺ diffusion layer 95 is to form the diodes according to the pn junction.

In this diode, a p-type silicon substrate 90 constitutes the anode, the n-type region constitutes the cathode, and the diode is a diode which is forward biased from the p-type silicon substrate 90 to the n ⁺ diffusion layer 95 do.

In this state, the p-type silicon substrate 90 is connected to the power supply terminal Vcc and the n < ^{+ &} gt ^; diffusion layer 95 is grounded when the direct current power source is connected with reversed polarity.

As a result, there is a problem that the power supply terminal Vcc is grounded in the semiconductor integrated circuit 80 and the semiconductor integrated circuit 80 is destroyed.

Next, Fig. 12 is a sectional view of the p-type diffusion resistor 82, showing the state in which the direct current power source is connected with the polarity reversed.

In Figure 12, p-type diffused resistor 82 is formed on the p-type silicon substrate (90), n ⁺ buried layer (96), n ^_ epitaxial layer (97), p-type diffusion layer 98 forming the resistor, and n ⁺ Diffusion layer (99).

and a p-type silicon substrate (90), n-type region formed in the n ⁺ buried layer 96 and the n ^_ epitaxial layer 97 and n ⁺ diffusion layer 99 is to form the diodes according to the pn junction.

In the diode, p-type silicon substrate 90. This forms the anode, n ⁺ buried layer 96 and the n ^_ epitaxial layer 97 and n ⁺ a n type region formed of a diffusion layer (99) itmyeo forms a cathode, The diode is a diode that is forward-biased from the p-type silicon substrate 90 to the n ⁺ diffusion layer 99.

In this state, the p-type silicon substrate 90 is connected to the power supply terminal Vcc and the n ⁺ diffusion layer 99 is grounded when the direct current power source is connected reversely with the polarity reversed.

As a result, there is a problem that the power supply terminal Vcc is grounded in the semiconductor integrated circuit 80 and the semiconductor integrated circuit 80 is destroyed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor integrated circuit which is not broken even when DC power is connected by reversing the polarity do.

The present invention relates to a semiconductor integrated circuit comprising a bipolar IC, in which a DC power supplied from the outside is supplied to each element of a bipolar IC through a pnp transistor, and the pnp transistor is connected to a base And to prevent the breakdown of each element when the direct current power source is connected by reversing the polarity while the current is flowing.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an example of a semiconductor integrated circuit according to a first embodiment of the present invention. Fig.

Fig. 2 is a sectional view of the pnp transistor 2 shown in Fig. 1 when the DC power supply is normally connected. Fig.

Fig. 3 is a sectional view of the npn transistor 11 shown in Fig. 1 when the DC power supply is normally connected. Fig.

Fig. 4 is a sectional view of the p-type diffusion resistor 12 shown in Fig. 1 when the dc power supply is normally connected. Fig.

5 is a sectional view of the p-type diffusion resistor 6 shown in Fig. 1 when the direct current power supply is normally connected.

6 is a sectional view of the pnp transistor 2 shown in Fig. 1 when a DC power supply is connected with the polarity reversed. Fig.

Fig. 7 is a sectional view of the npn transistor 11 shown in Fig. 1 when a DC power supply is connected with reversed polarity. Fig.

8 is a sectional view of the p-type diffusion resistor 12 shown in Fig. 1 when the direct current power source is connected with the polarity reversed. Fig.

9 is a sectional view of the p-type diffusion resistor 6 shown in Fig. 1 when the direct current power source is connected with the polarity reversed.

10 is a diagram showing an example of a conventional semiconductor integrated circuit.

11 is a sectional view of the npn transistor 81 shown in Fig. 10 when the direct current power source is connected with the polarity reversed.

12 is a sectional view of the p-type diffusion resistor 82 shown in Fig. 10 when a DC power supply is connected with reversed polarity. Fig.

DESCRIPTION OF REFERENCE NUMERALS

1: semiconductor integrated circuit 2: pnp transistor

3: constant current source 4,5,11: npn transistor

6,12: p-type diffusion resistor 10: electronic circuit

Next, the present invention will be described in detail with reference to the embodiments shown in the drawings.

Embodiment Mode 1.

1 is a diagram showing an example of a semiconductor integrated circuit according to a first embodiment of the present invention.

1, the semiconductor integrated circuit 1 includes a pnp transistor 2 having a collector wall ring, a constant current source 3, npn transistors 4 and 5, a p-type diffusion resistor 6, and an electronic circuit 10 formed of a semiconductor integrated circuit.

The semiconductor integrated circuit 1 is formed of a bipolar IC, and the collector wall ring is a collector wall.

The electronic circuit 10 is composed of an npn transistor 11, a p-type diffusion resistor 12 and pnp transistors 13 and 14. The emitter of the npn transistor 11 is connected to the ground via a p- do.

The base of the npn transistor 11 is connected to the base of the pnp transistors 13 and 14 respectively and the emitters of the pnp transistors 13 and 14 are respectively connected to the collector of the npn transistor 11, 14 are also connected to a collector.

In the electronic circuit 10, only a part of the circuit is shown for easy understanding.

10 and 12, and the npn transistor 11 is connected to the npn transistor 81 of FIG. 10, and the p (npn) Type diffusion resistor 12 is connected to the p-type diffusion resistor 82 in FIG. 10, the pnp transistor 13 is connected to the pnp transistor 83 in FIG. 10, the pnp transistor 14 is connected to the pnp transistor 84 in FIG. 10 ).

The emitter of the pnp transistor 2 is connected to a power supply terminal Vcc supplied from the outside with DC power and the collector of the pnp transistor 2 is connected to the collector of the npn transducer 11 of the electronic circuit 10 And the connecting portion a is a power source terminal to which the DC power of the electronic circuit 10 is supplied.

A constant current source 3 is connected between the base of the pnp transistor 2 and the ground so that the pnp transistor 2 is connected to the base of the pnp transistor 2 by the constant current source 3 with a sufficient current Flows.

The collector of the npn transistor 4 is connected to the base of the pnp transistor 2, and the emitter of the npn transistor 4 is grounded.

The base of the npn transistor 4 is connected to the base of the npn transacter 5, and the corresponding connection is connected to the collector of the npn transacter 5.

In the npn transceiver 5, the emitter is grounded, and the collector is connected to the power supply terminal Vcc via the p-type diffusion resistor 6. [

In addition, n-type regions formed by various n-type layers in the p-type diffusion resistors 6 and 12 are connected to the connection portion (a), respectively, and details will be described later.

The npn transducers 4 and 5 and the p-type diffusion resistor 6 form a start-up circuit and the current set in the constant current source 3 is supplied to the pnp transistor (2).

Here, when the pnp transistor 2 is turned on, it is necessary to operate the pnp transistor 2 in the saturation region in order to reduce the voltage drop across the emitter collector. Therefore, at the base of the pnp transistor 2 it is necessary to pass a current large enough to operate the pnp transistor 2 in the saturation region.

Thus, the constant current source 3 is set so as to flow a sufficiently large current as described above to the base of the pnp transistor 2.

FIG. 2 is a sectional view of the pnp transistor 2 of FIG. 1 showing a case where the DC power supply is normally connected.

2, the pnp transistor 2 includes a collector wall ring 21 formed of an n ⁺ layer formed on a p-type silicon substrate 20, ^n_ epitaxial layers 22 and 23, a p- 24 and 25, made of a p-type diffusion layer 26 forming the emitter, the collector, the ring 21 and the n ^_ epitaxial layer (22, 23) forms the base.

The collector wall ring 21 has a function of lowering the series resistance of the collector and reducing the effect of the parasitic pnp transistor formed between the collector wall ring 21 and the silicon substrate.

Therefore, the saturation voltage of the pnp transistor 2 can be reduced, and the voltage drop due to the pnp transistor 2 when the pnp transistor 2 is turned on can be reduced.

The p-type diffusion layers 24 and 25 are connected to form a collector, and the collector is connected to the connection part (a) of the electronic circuit 10. [

When the DC power is normally connected, the p-type silicon substrate 20 is grounded and the p-type diffusion layer 26 forming the emitter is connected to the power supply terminal Vcc.

Fig. 3 is a sectional view of the npn transceiver 11 of Fig. 1 showing a case where the DC power supply is normally connected.

2 are denoted by the same reference numerals.

In Figure 3, npn transfected sitter 11 has n ⁺ buried layer (31), n ^_ epitaxial layer (32), p-type diffusion layer 33 forming the base formed on the p-type silicon substrate 20, an emitter forming n ⁺ diffusion layer 34, and made of an n ⁺ diffusion layer 35 forming the contact part of the collector, the n ^_ epitaxial layer 32 and the n ⁺ diffusion layer 35 forms the collector.

The n ⁺ diffusion layer 35 is connected to the collector of the pnp transistor 2 and the p type diffusion layer 33 forming the base is connected to the base of the pnp transistors 13 and 14 to form an n ⁺ diffusion layer 34 are connected to the p-type diffusion resistor 12.

When the DC power is normally connected, the p-type silicon substrate 20 is grounded.

Next, Fig. 4 is a sectional view of the p-type diffusion resistor 12 of Fig. 1 showing a case where the dc power source is normally connected.

2 are denoted by the same reference numerals.

4, the p-type diffusion resistor 12 includes an n ⁺ buried layer 41, an n ^- epitaxial layer 42, a p-type diffusion layer 43 forming a resistor, and n ⁺ Diffusion layer 44 as shown in FIG.

The n ⁺ diffusion layer 44 is connected to the collector of the pnp transistor 2, and the p-type silicon substrate 20 is grounded.

Two terminals are set in the p-type diffusion layer 43, and the resistance value between the two terminals becomes the resistance value of the p-type diffusion resistor 12. [

one of the two terminals set in the p-type diffusion layer 43 is connected to the emitter of the npn transistor 11, and the other terminal is grounded.

Next, Fig. 5 is a sectional view of the p-type diffusion resistor 6 of Fig. 1 showing a case where the dc power supply is normally connected.

2 are denoted by the same reference numerals.

5, the p-type diffusion resistor 6 is n ⁺ buried layer (51), n ^_ epitaxial layer (52), p-type diffusion layer 53 forming the resistor formed on the p-type silicon substrate 20 and the n ⁺ Diffusion layer 54 as shown in FIG.

The n ⁺ diffusion layer 54 is connected to the collector of the pnp transistor 2, and the p-type silicon substrate 20 is grounded.

Two terminals are set in the p-type diffusion layer 53, and the resistance value between the two terminals becomes the resistance value of the p-type diffusion resistor 6. [

one of the two terminals set in the p-type diffusion layer 53 is connected to the power supply terminal Vcc and the other terminal is connected to the collector and base of the npn transducer 5 and the collector of the npn transistor 5 Respectively.

Here, p-type diffusion layer 53 and, n ⁺ buried layer 51 and n ^_ epitaxial layer 52 and n ⁺ parasitic to the diffusion layer (54) n-type regions and, p-type silicon substrate 20 is composed of a pnp transistor .

However, the n ⁺ diffusion layer 54 constituting the base terminal of the parasitic pnp transistor is connected to the power supply terminal Vcc through the pnp transistor 2, and the pnp transistor 2 is connected to the emitter collector Is smaller than the voltage between the emitter bases of the parasitic pnp transistors.

As a result, in the parasitic pnp transistor, the emitter voltage becomes lower than the base voltage, the parasitic pnp transistor does not turn on, and the leakage current from the power source by the parasitic pnp transistor can be reduced.

Next, a case where the direct current power source is connected to the semiconductor integrated circuit 1 with the polarities reversed will be described.

6 is a sectional view of the pnp transistor 2 when the DC power supply is connected with the polarity reversed.

In Fig. 6, the same components as those in Fig. 2 are denoted by the same reference numerals, and a description thereof will be omitted.

6, the p-type silicon substrate 20 is connected to the power supply terminal Vcc and the grounded portion of the electronic circuit 10 is connected to the power supply terminal Vcc, And is connected to the power supply terminal Vcc.

Further, the emitter of the pnp transistor 2 is grounded.

In this state, a diode is formed by the pn junction between the p-type silicon substrate 20 and the n-type region comprising the collector wall ring 21 and the ^n_ epitaxial layers 22 and 23, gap between the p-type diffusion layer (24-26) and, n-type region formed in the ring collector 21 and the n ^_ epitaxial layers 22 and 23 are formed in the diode according to the respective pn junctions.

However, the grounded p-type diffusion layer 26 constitutes the anode of the diode, and the n-type region comprising the collector wall ring 21 and the epitaxial layers 22 and 23 forms the cathode of the diode.

As a result, the p-type silicon substrate 20 and the p-type diffusion layer 26 are not short-circuited and the p-type silicon substrate 20 and the p-type diffusion layer 24, the p- ) Are not short-circuited.

Therefore, in the case where the direct current power source is connected with the opposite polarity, the npn transistor 81 and the p-type diffusion resistor 82 shown in Figs. 11 and 12, The power supply terminal Vcc connected to the collector of the pnp transistor 2 is grounded through the emitter of the pnp transistor 2 by each diode formed in the transistor 11 and the p type diffusion resistor 12, ≪ / RTI >

As described above, when the direct current power source is connected with the polarity reversed, each diode formed in the npn transducer 11 and the p-type diffusion resistor 12 in the electronic circuit 10 causes the electronic circuit 10 The connection portion a can be prevented from being grounded by the pnp transistor 2 even if the connection portion a of the connection portion a is connected to the power supply terminal Vcc.

7 is a sectional view of the npn transistor 11 when the DC power supply is connected with the polarity reversed.

In Fig. 7, the same components as those in Fig. 3 are denoted by the same reference numerals, and a description thereof will be omitted.

7, the p-type silicon substrate 20 is connected to the power supply terminal Vcc and the emitter of the pnp transistor 2 is grounded as the DC power supply is connected with the polarity reversed.

Here, the power supply terminal (Vcc) is formed between the n-type region and formed of a p-type silicon substrate 20 and, n ⁺ buried layer 31 and n ^_ epitaxial layer 32 and the n ⁺ diffusion layer 35 And is connected to the n < ^{+ &} gt ^; diffusion layer 35 by a forward-biased diode.

However, n ⁺ diffusion layer 35, and the collector of the pnp transistor 2 is connected, by a pnp transistor (2), n ⁺ diffusion layer 35 is not ground.

Next, Fig. 8 is a chip cross-sectional view of the p-type diffusion resistor 12 when the direct current power source is connected with reversed polarity.

In Fig. 8, the same components as those in Fig. 4 are denoted by the same reference numerals, and a description thereof will be omitted.

8, the p-type silicon substrate 20 is connected to the power supply terminal Vcc in accordance with the connection of the dc power supply with the polarity reversed, and of the two terminals set in the p- Is connected to the power supply terminal (Vcc), and the emitter of the pnp transistor (2) is grounded.

Here, the power supply terminal (Vcc) is formed between the p-type silicon substrate 20 and, n ⁺ buried layer 41 and n ^_ epitaxial n-type region consisting of a 42 and the n ⁺ diffusion layer 44 the forward is formed between the forward-biased diode, and the p-type diffusion layer 43 and, n ⁺ buried layer 41 and n ^_ formed of the epitaxial layer 42 and the n ⁺ diffusion layer (44), n type regions biased And is connected to the n < ^{+ &} gt ^; diffusion layer 44 by a diode.

However, n ⁺ diffusion layer 44 had a collector of the pnp transistor 2 is connected, by a pnp transistor (2), n ⁺ diffusion layer 44 is not ground.

9 is a sectional view of the p-type diffusion resistor 6 when the direct current power source is connected with reversed polarity.

In Fig. 9, the same parts as those in Fig. 5 are denoted by the same reference numerals, and a description thereof will be omitted.

9, the p-type silicon substrate 20 is connected to the power supply terminal Vcc and the p-type diffusion layer 53 is connected to the power supply terminal Vcc and the emitter of the pnp transistor 2 are grounded.

Here, the power supply terminal (Vcc) is a p-type silicon substrate 20 and, n ⁺ buried layer 51 and n ^_ epitaxial layer 52 and the n ⁺ diffusion layer 54 which is formed between the n-type region formed but connected to the n ⁺ diffusion layer 54 by a forward-biased diode, n ⁺ diffusion layer 54 had a collector of the pnp transistor 2 is connected, by a pnp transistor (2), n ⁺ diffusion layer 54 is It is not grounded.

In addition, p-type diffusion layer 53 and, n ⁺ buried layer 51 and n ^_ epitaxial layer 52 and n ⁺ by the diode formed between the n-type region and formed of a diffusion layer 54, the grounded p-type One terminal of the diffusion layer 53 is not connected to the power supply terminal Vcc.

As described above, the semiconductor integrated circuit 1 according to the first embodiment of the present invention has the connection portion (a), which is the power supply terminal to which the DC power is supplied in the electronic circuit 10 formed by the semiconductor integrated circuit, A pnp transistor 2 having a collector wall ring is disposed between the pnp transistor 2 and the gate of the pnp transistor 2 and a DC power source is supplied to the connection portion a through the pnp transistor 2, The constant current source 3 is connected so that the base current of the same magnitude as the transistor 2 operates in the saturation region.

Therefore, in the semiconductor integrated circuit 1, when the direct-current power supply is normally connected, the voltage drop by the pnp transistor 2 can be minimized, and at the same time, the parasitic pnp The leakage current from the power source by the transistor can be reduced.

Even if the power supply terminal Vcc and the connection portion a are short-circuited in the electronic circuit 10 when the DC power supply is reversed with the polarities reversed, the connection portion (a) It can be prevented from being grounded.

As a result, even when the direct current power source is connected by reversing the polarity, it is possible to prevent the power source terminal (Vcc) from being grounded in the semiconductor integrated circuit, thereby preventing breakage of the semiconductor integrated circuit.

As is apparent from the above description, according to the semiconductor integrated circuit of the present invention, the DC power supplied from the outside is supplied to each element of the bipolar IC through the pnp transistor through which the base current of the same magnitude as that in the saturation region operates. And the pnp transistor has the opposite polarity to prevent the breakdown of each element when the direct current power source is connected.

Therefore, when the DC power supply is connected with the opposite polarity, it is possible to prevent the power supply terminal Vcc from being externally supplied with the DC power from being grounded in the semiconductor integrated circuit, thereby preventing destruction of the semiconductor integrated circuit.

As a result, it is possible to improve the reliability in the semiconductor integrated circuit.

Claims (1)

In a semiconductor integrated circuit comprising a bipolar IC, A direct current power supplied from the outside is supplied to each element of the bipolar type IC through a pnp transistor and a base current of the same magnitude as that of the pnp transistor operates in a saturation region flows and the polarity is reversed, And prevents breakdown of each of the elements when the semiconductor integrated circuit is connected.