JP2558201Y2 - Overvoltage protection circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overvoltage protection circuit for protecting an element when an abnormal voltage is generated at an output terminal of an operational amplifier.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional overvoltage protection circuit applied to a power operational amplifier. In this circuit, at the output stage of the power operational amplifier, two diodes D1 and D2 are connected to a newly provided constant current transistor Q1 (a fixed voltage is applied to the base) to fix the voltage at the connection point A and The transistors Q2 and Q3 are connected between the resistor R1 functioning as a current source of the bias circuit and the output terminal 1 via the resistor R2 for current reduction. The emitter follower transistors Q4 and Q5 form a SEPP circuit in which both emitters are commonly connected to the output terminal 1, and the transistor Q7
Drives the SEPP circuit by inputting a signal to the base,
A transistor Q6 having a fixed voltage applied to the resistor R1 and the base supplies a collector current to the transistor Q7,
The diodes D3 and D4 perform temperature compensation by maintaining the base between the transistors Q4 and Q5 at 2V _BE .

In this circuit, a positive voltage +
When a negative voltage −V is applied to the negative power supply terminal 3 and a load is connected between the output terminal 1 and the ground 4, the load is applied to the load in accordance with a signal applied to the input terminal (not shown). The applied output voltage Vo changes.

However, when a motor or a solenoid is connected as the load, the voltage Vo at the output terminal 1 becomes significantly lower than the voltage -V at the negative voltage terminal 3 due to the back electromotive force generated in the motor or the solenoid. Transistor Q
4 causes an overvoltage between the emitter and the collector, which may cause destruction.

However, at this time, if the breakdown voltage between the base and the collector of the transistor Q3 is set to the voltage Vs corresponding to the potential difference between the power supply voltages + V and -V, the voltage Vo of the output terminal 1 and the positive power supply terminal 2 When the potential difference from the voltage + V reaches the sum of the voltage Vs, the V _{BE of} the transistor Q2, and the V _CE of the transistor Q1, the transistor Q3 breaks down, and the voltage of the output terminal 1 becomes negative. 0.7 V (total 2 Vf of the forward voltage drops of the diodes D1 and D2 = 1.4 V).
From the base-emitter voltage V _{BE of the} transistor Q2 =
It is clamped to a voltage higher by 0.7 V (a voltage value reduced by 0.7 V). The breakdown current at this time is represented by resistors R1, R2,
It flows through the transistors Q2 and Q3, and the transistors Q6 and Q
7 are turned off, and transistors Q4 and Q5 are also turned off to protect them.

[0006]

[Problem to be solved by the invention] However, in this circuit,
Transistors Q1-Q3, resistor R2, diode D1,
This requires a large number of elements, that is, a total of six D2s, and occupies a large layout area, which is disadvantageous in integration.

Accordingly, the present invention is to provide an overvoltage protection circuit which greatly reduces the required number of elements and improves the layout area.

[0008]

The overvoltage protection circuit of the present invention has a first NPN transistor (Q4) having a collector connected to a positive power supply terminal (2) and a collector connected to a negative power supply terminal (3). First PNP transistor (Q5)
SE connected in common to both output terminals (1)
A PP circuit, a second NPN transistor (Q7) that inputs a signal to drive the SEPP circuit, and a second NPN transistor (Q7).
A second PNP transistor (Q6) for supplying a collector current to the transistor (Q7); the second PNP transistor (Q6); and the second NPN transistor (Q
7) two diodes (D
3, D4) and the second PNP transistor (Q6)
And an output stage having a first resistor (R1) connected between the first PNP terminal and the positive power supply terminal (2), wherein the collector is connected to the second PNP through a second resistor (R3). A third NPN transistor (Q8) having an emitter connected to the output terminal (1) and a base connected to the negative power supply terminal (3) is provided to the emitter of the transistor (Q6). Transistor (Q
8) The emitter and the collector are constituted by an N-type epitaxial layer surrounded by a P-type substrate and a P-type region reaching the P-type substrate, and the base is formed between the emitter and the collector. And the P-type region connected to the P-type substrate.

In the present invention, the emitter and the collector of the third NPN transistor have a pocket structure for emitter diffusion formed on the surface of the epitaxial layer, and the base has an isolation structure formed between the emitter and the collector. Can be.

[0010] By NPN transistor (Q8) is turned on, the potential difference is clamped to _{V BE} of the transistor (Q8) between the output terminal (1) and the negative power supply terminal (3), the excess voltage output transistor ( Q4, Q5) is prevented. In particular, the current flowing through the output terminal (1) is supplied from the collector of the NPN transistor (Q8), so that current flowing between the base and the emitter of the transistor (Q8) is slightly, V _BE is the current flowing through the output terminal Its overvoltage protection is provided without significant influence. The element required for protection is NP
With only the N transistor (Q8) and the resistor (R3), the layout area is greatly reduced.

[0011]

Embodiments of the present invention will be described below. FIG. 1 is a diagram showing an overvoltage protection circuit according to one embodiment. Here, the same components as those in FIG. 4 described above are denoted by the same reference numerals. In the present embodiment, a protection N is provided between the current source resistance R1 and the output terminal 1 via a current reduction resistor R3.
The PN transistor Q8 is connected. The base of the transistor Q8 is connected to the power supply terminal 3.

[0012] Consequently, in this circuit, than the voltage -V voltage Vo at the output terminal 1 is the negative power supply terminal 3 becomes lower by _{V BE} of the transistor Q8, the transistor Q8
Conducts to shut off the transistors Q6 and Q7 and shut off and protect the transistors Q4 and Q5. At this time, the voltage of the output terminal 4 is clamped at a lower voltage by V _BE of the transistor Q8 than the voltage -V of the negative power supply terminal 3. Further, the current flowing through the output terminal is supplied from the collector of the transistor Q8, and the current flowing between the base and the emitter of the transistor Q8 is very small. , Does not greatly change its clamp voltage _VBE .

The above-described transistor Q8 is a conventional NP
N transistor (breakdown voltage is about 6.5V)
2 and 3, a high-concentration N-type emitter 33 and a collector 34 are formed in an N-type epitaxial layer 32 on a P-type substrate 31 with a pocket structure for emitter diffusion. The base 35 has an isolation structure. As a result, the breakdown voltage becomes sufficiently high. Moreover, the layout is extremely simple and the layout area is greatly reduced.

As described above, according to the present invention, effective overvoltage protection can be performed only by adding two elements, a resistor (R3) and a transistor (Q8), to an operational amplifier.
The base current flowing through the transistor (Q8) is only when an overvoltage is applied, and does not normally flow, so that the current is not wasted. Further, in the present invention, the current flowing to the output terminal when an overvoltage is applied is supplied from the collector of the transistor (Q8), and the current flowing between the base and the emitter of the transistor is very small. Therefore, the clamp voltage does not greatly change. The overvoltage protection function is not impaired. In the present invention, the layout of the third NPN transistor (Q8) is formed on a P-type substrate and an N-type epitaxial layer formed thereon. In other words, N surrounded by a P-type region called a so-called isolation structure reaching the P-type substrate
The type epitaxial layer is used as an emitter and a collector region, and an isolation region between the emitter region and the collector region is used as a base region. This structure
Even without forming a special region for forming the transistor, the transistor can be formed by an isolation region and an epitaxial layer formed on a normal semiconductor device. That is, a semiconductor device can be configured without increasing the element area. Therefore, it is very advantageous in forming a semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an overvoltage protection circuit according to an embodiment of the present invention applied to an output stage of a power operational amplifier.

FIG. 2 is a plan view of a layout of elements constituting an overvoltage protection circuit.

FIG. 3 is a cross-sectional view of a layout of elements constituting an overvoltage protection circuit.

FIG. 4 is a circuit diagram of a conventional overvoltage protection circuit applied to an output stage of a power operational amplifier.

[Explanation of symbols]

 1: output terminal, 2: positive power supply terminal, 3: negative power supply terminal

Claims (1)

(57) [Scope of request for utility model registration] An emitter of a first NPN transistor (Q4) having a collector connected to a positive power supply terminal (2) and an emitter of a first PNP transistor (Q5) having a collector connected to a negative power supply terminal (3). An SEPP circuit commonly connected to the output terminal (1); a second NPN transistor (Q7) for inputting a signal to drive the SEPP circuit;
A second PNP transistor (Q6) for supplying a collector current to the NPN transistor (Q7) of the second
Two diodes (D3, D4) connected between the P transistor (Q6) and the collector of the second NPN transistor (Q7), and the second PNP transistor (Q
6) and an operational amplifier having an output stage having a first resistor (R1) connected between the positive power supply terminal (2) and a collector connected to the second resistor via a second resistor (R3). PN
A third NPN transistor (Q8) having an emitter connected to the output terminal (1) and a base connected to the negative power supply terminal (3) is provided to the emitter of the P transistor (Q6). In the NPN transistor (Q8), the emitter and the collector are formed of an N-type epitaxial layer surrounded by a P-type substrate and a P-type region reaching the P-type substrate, and the base is formed of the emitter and the collector. An overvoltage protection circuit formed between the P-type regions and connected to the P-type substrate.