JP2803887B2 - Semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A semiconductor integrated device operated by a plurality of power supplies is provided. In a semiconductor integrated device operated by a plurality of power supplies, each of the power supplies has a plurality of diodes each having an anode connected thereto, and each of the isolation regions having a plurality of diodes each having a common cathode.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated device operated by a plurality of power supplies.

As a semiconductor integrated device operated by a plurality of power supplies, for example, there is one having a circuit configuration as shown in FIG. In the figure, PNP transistors Q ₁ and Q ₂ form a current mirror circuit, the collector of Q ₁ is connected to the collector of NPN transistor Q ₃ and the collector of Q ₂ is a level shift diode D ₁ to D ₃ It is connected to the emitter of the PNP transistor Q ₄ through.

The collector of the transistor Q ₂ is via a resistor Ra NP
N transistor Q is connected to the base _5, also NPN transistor base via a resistor Rb of the transistor Q ₅ Q
Connected to ₆ collectors.

Further, the collector of the emitter and the transistor Q ₅ of the transistors Q ₁ and Q ₂ are each first power supply is applied, while each second power supply is applied to the bases of the transistor Q ₅ of the transistor Q ₃ Configuration.
The power supply is applied to the base of transistor Q ₅ through the diode D _4. Here, the power supply is set to a higher potential than the power supply.

In such a circuit, the resistors Ra and Rb are manufactured as diffusion resistors, and a power supply, which is usually the highest potential, is applied to the electrodes of the isolation region (not shown), and the pn junction of the isolation region is reverse-biased and functions as a resistance. Let me. Therefore, even when power is not applied to the electrodes of the isolation region for some reason, it is necessary to apply power and make Ra and Rb function as resistors.

[Conventional technology]

FIG. 4 shows a structural diagram of an example of a conventional semiconductor integrated device. In the figure, an n-type isolation region 42 is formed on a p-type semiconductor substrate 41, and a p-type diffusion layer 43 is formed in the isolation region 42. Thereafter, after a silicon dioxide (SiO ₂ ) film 44 is formed on the semiconductor substrate 41, predetermined portions are removed by a normal lithography technique, and then electrodes 45, 46 and 47 made of aluminum (Al) are formed. .

The p-type diffusion layer 43 functions as the resistance Ra or Rb, and the electrodes 45 and 46 formed at both ends of the p-type diffusion layer 43.
Functions as a resistor electrode. On the other hand, the electrode 47 formed on the separation region functions as an electrode of the separation region. Conventionally, even in a semiconductor integrated device using a plurality of power supplies, only the highest potential power supply is applied to the electrode 47 of the isolation region, and thus the p-type diffusion layer 43 and the isolation region 42 are formed. The pn junction is reverse-biased to keep parasitic elements from operating.

[Problems to be solved by the invention]

However, in the above-described conventional device, power is not applied to the electrode 47 of the isolation region for some reason, or the pn junction formed by the p-type diffusion layer 43 and the isolation region 42 is forward-biased depending on the power-on sequence of a plurality of power sources. As a result, there is a problem that the p-type diffusion layer 43 does not function as a resistor, and a parasitic element operates to destroy the semiconductor integrated device.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor integrated device that can reverse bias an isolation region even when there is a power supply that is not turned on.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. As shown in the figure, the present invention has an isolation region including resistance diffusion layers 12 and 13 and a plurality of power supply V
In the semiconductor integrated device that operates by ₁ ~V _n, each anode connected to the each power supply V ₁ ~V _n,
The is characterized in that each cathode in the separation region has a common-connected plurality of diodes 15 ₁ to 15 _n.

[Action]

When the power V ₁ ~V _n is assumed to be in a relationship that potential V _1> ... becomes> V _n, typically all of the power is normally turned on, and is connected to a power source V ₁ of the highest potential diode 15 ₁
Only it is turned on, and all the rest of the diode 15 ₂ to 15 _n are turned off. Therefore, at this time the voltage from the potential of the power supply V ₁ minus the forward curing voltage V _D of the diode 15 ₁ to the electrode 14 of the isolation region is applied to the resistor diffusion bonding (pn junction) is reverse biased normally .

On the other hand, when the power source V ₁ is was 0V without being charged for some reason, only the diode 15 ₂ which is connected to a power source V ₂ of the highest potential of the remaining power V ₂ ~V _n are turned on, thereby the Similarly, the resistance diffusion junction (pn junction) is normally reverse-biased. The same applies to other cases. Therefore,
In the present invention, even if one of the plurality of power supplies is not turned on, the remaining power supply can reverse bias the resistance diffusion junction (pn junction).

〔Example〕

FIG. 2 shows a structural diagram of one embodiment of the present invention. In the figure,
The same components as those in FIG. 1 are denoted by the same reference numerals. Second
In the figure, an n-type isolation region 22 is formed in a p-type semiconductor substrate 21, and a p-type resistance diffusion layer 12
(Or 13) is formed.

Furthermore, after the SiO ₂ film 23 is formed on the semiconductor substrate 21, separated from the resistive diffusion layer 12 (13) upper part of the SiO ₂ film 23 region 22
Windows were opened in the upper part of the electrodes, and Al electrodes 24, 2
5 and 14 are formed.

The electrodes 24 and 25 are provided on both ends of the resistance diffusion layer 12 (13), and are electrodes for resistance. On the other hand, the electrode 14 is
It is connected to only 22 and is an electrode in the isolation region. In the present embodiment, it is characterized both cathode of integrated diode 15 ₁ and 15 ₂ to the electrodes 14 of the isolation region to a point which is respectively connected. In this embodiment, the electrodes other than the ground potential are V ₁
And V ₂ (where V ₁ > V ₂ ).

Thus, according to this embodiment, the power source V ₁ and the power source V ₁ is the electrode 1 via the diode 15 ₁ when V ₂ is normally turned
4 is applied to, and only the power supply V ₂ is also power V ₂ via the diode 15 ₂ is applied to the power supply 14 as V ₁ is turned is not turned on by some cause, in any case, the isolation region 22 The pn junction with the resistance diffusion layer 12 (13) can be reverse-biased.

Therefore, according to the present embodiment, it is possible to always reverse bias the resistance diffusion junction by using the power supply originally used as the power supply for operation of the semiconductor integrated device without newly providing a power supply for reverse bias compensation. Thus, the resistor can be operated normally, and device destruction due to the operation of a parasitic element can be prevented.

〔The invention's effect〕

As described above, according to the present invention, even if one of the plurality of power supplies is not turned on, the resistance diffusion junction can be reverse-biased by the remaining power supplies. It has features that it can function normally as a resistor, and does not operate a parasitic element, thereby preventing damage to the semiconductor integrated device due to the operation of the parasitic element.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a circuit diagram of an example of a semiconductor integrated device, and FIG. FIG. In the figure, 11 is a semiconductor integrated device, 12, 13 resistance diffusion layer, 14 an electrode of the isolation region, 15 ₁ to 15 _n denotes a diode.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/04

Claims (1)

(57) [Claims] 1. A semiconductor integrated device having an isolation region including a resistance diffusion layer and operated by a plurality of power supplies, wherein each anode is connected to each power supply, and each cathode is connected to the isolation region in common. A semiconductor integrated device comprising a plurality of diodes.