JPH01305560A - Complementary mos transistor - Google Patents

Abstract

PURPOSE:To prevent latch-up phenomena by forming a recessed cut-in part at the other face of a semiconductor substrate right below a guard ring, and providing a first conductivity type diffusion layer in contact with the guard ring inside the cut-in part. CONSTITUTION:A cut-in part 31 is formed below a complementary MOS transistor formed on a P-type silicon substrate 1, and a guard ring 16 is so formed between a PMOS transistor and an NMOS transistor in contact with an N<+> diffusion region 41 at the cut-in part 31. By this constitution, since the PMOS transistor and the NMOS transistor are formed as to be surrounded by a dielectric isolation layer, the P-type silicon substrate 1 and the N-type well 2 are electrically isolated at the guard ring part and at the N<+> diffusion area 41 part, accordingly even if carriers are injected into inside of the P-type silicon substrate 1due to noise, etc., positive feedback becomes hard to work and no latch-up phenomenon occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to complementary MO5 transistors.

[Conventional technology]

FIG. 2 is a sectional view showing an example of the structure of a conventional complementary MO5I transistor. In the figure, 1 is a P-type silicon substrate, 2 is an N-type well formed in a part of the P-type silicon substrate 1, and 3 and 4 are the sources of PMOS transistors formed on the surface of the P-type silicon substrate. and I~rain, 5 and 6 are NM formed on the surface of the N-type well 2.
Source and drain of the O5+- transistor, 7 is a Bi region for contact 1 to the P-type silicon substrate, 8 is an N+ region 9 for contact to the N-type well, is a gate I to oxide film,
1o is the gate electrode of the PMO5l helangistor, 11 is N
Gate electrode of MO5+- transistor, 12 is input wiring,
13 is an output wiring, and 14 and 15 are power supply wirings.

The latch-up phenomenon of complementary MOS+ transistors will be explained using FIG.

+IOV is applied to the power supply wiring 14, and O is applied to the power supply wiring 15.
When V is applied, if a negative excessive voltage is momentarily applied to the power supply wiring 14 due to external noise, the drain 6 is forward biased with respect to the substrate 1, and electrons are injected into the substrate 1. Ru. When some of these electrons reach the N-type well 2, they are conducted through the N-type well 2 and a current flows through the N+ region 8 and the power supply wiring 14.

Therefore, a voltage drop occurs in the N-type well 2, and the gap between the source 3 and the N-type well 2 is biased in the forward direction. As a result, the relationship between the substrate 1 and the source 5 is forward biased,
Electrons are injected into the substrate 1.

Since these electrons act in the same way as electrons injected from the train due to external noise, positive feedback is applied as a whole.

When positive feedback is applied in this way, the power supply wiring 14 and 1
5, the current continues to flow, resulting in element destruction.

In order to prevent such latch-up phenomenon, conventionally, as shown in FIG.
5) - A method of increasing the distance from the transistor, or a method of surrounding the MOS transistor with a guard ring 16 made of a diffusion layer to fix the potential of the substrate, etc., have been used.

[Problem to be solved by the invention]

However, in order to obtain sufficient latch-up resistance using the method of increasing the distance between two series of 1-transistors, the area required for this is large, making it unsuitable for high-density integration. Also, in the method of enclosing with gart links,
A launch-up phenomenon may occur when passing under the diffusion region forming the gart ring, so it cannot be said to be a perfect countermeasure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a complementary MOS transistor that is highly integrated and does not cause latch-up.

[Means to solve the problem]

In order to achieve the above object, the complementary MOS 1 to transistor of the present invention includes a second conductivity type MO5 transistor formed in a first conductivity type semiconductor substrate and comprising a second conductivity type source region and a 1-rain region. , a first conductivity type MOS transistor consisting of a first conductivity type source region and a drain region formed in a second conductivity type well layer in the semiconductor substrate, and a first conductivity type MOS transistor formed around the second conductivity type MO5I-transistor. a first conductive type guard ring on one surface of the semiconductor substrate; a recessed recessed portion is formed on the other surface of the semiconductor substrate corresponding to at least immediately below the guard ring; It has a first conductivity type diffusion layer in contact with the first conductivity type.

[Effect]

A recessed portion is formed at the bottom of the complementary MOS) transistor formed on a silicon substrate, and a gart ring is formed between the PMOS transistor and the NMOS transistor in contact with the diffusion layer of the recessed portion. ing. Therefore, the P and NMO5 transistors have a structure surrounded by an insulating separation layer. Therefore, even if carriers are injected into the substrate due to external noise or the like, since the substrate and the well are electrically isolated, no positive feedback is applied and no latch-up phenomenon occurs.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

In FIG. 1(a), first, a P-type silicon substrate 1 is oxidized to form an oxide film 21 on the front and back surfaces.

Next, as shown in FIG. 1(b), a window for the dug portion 31 is formed in the oxide film 21 on the back surface using ordinary photolithography and selective etching. Subsequently, using this oxide film 21 as a mask, silicon etching is performed using, for example, a hydrazine aqueous solution, leaving a desired film thickness, for example, 3p, to form a recessed portion 31.

Subsequently, as shown in FIG. 1(C), a window for the guard ring 16 is formed in the oxide film 21 on the surface using ordinary photolithography and selective etching, and then a P-type impurity is diffused to form the guard ring. A bi-diffusion region 41 is formed in the trench 16 and the dug portion 31.

Thereafter, as shown in FIG. 1(d), a layer of an N-type well 2 is formed using ordinary silicon planar technology, and a source 3, a train 4, and a N-region 8 for contours 1 to 8 are formed inside the N-type well 2. , forming the electrode 10 and the All electrode 17 on the gate 1, and
Create a MOS transistor. Further, in the P type silicon substrate 1, a source 5, a train 6, contact areas 1 to 7, a goo 1 electrode 11, and an AQ electrode 17 are formed.
Create MO5+- transistor.

In such a structure, I) MOS l-transistor and N
Since the MOS 1 transistor is formed in an island region surrounded by the Go 1 ring 16 and the diffusion region 41, the P type silicon substrate 1 and the N type well 2 are connected to the bigard ring part and the diffusion region 41. Since the region 41 is electrically isolated, even if carriers are injected into the substrate due to external noise or the like, positive feedback is less likely to occur, and no launch-up phenomenon occurs.

Therefore, compared to conventional structures, it does not hinder integration.
A complementary MO51 helangistor that does not cause the latch-up phenomenon can be manufactured.

In addition, when forming the recessed portion, if the area of the recessed portion is made a little larger, slight misalignment will become a problem, but due to the structure of the present invention, the yield of the device will not be reduced. rare.

〔Effect of the invention〕

According to the present invention, as described in detail below, PMO8
1 ~ Transistor and NMOSI - Since the transistor is formed in an island region surrounded by guard links and diffusion regions, it is electrically isolated from the substrate and the well.
Therefore, even if carriers are injected into the substrate due to external noise or the like, positive feedback is less likely to occur, and a complementary MOS transistor that does not cause a latch-up phenomenon can be obtained without hindering integration.

In addition, conventionally, in order to reduce the punch-through voltage between the well and the substrate to some extent, the well indentation diffusion was carried out at a temperature of, for example, 1200°C.
However, according to the present invention, each transistor can be formed within an island isolated by a guard ring and a diffusion region, so the punch-through voltage can be increased. . Therefore, the indentation diffusion can be carried out under the conditions necessary to form a well of, for example, 3 μm. Therefore, the time required for indentation diffusion can be shortened, and the manufacturing cost 1- can be reduced.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to (d) are cross-sectional views showing the structure of each step of an embodiment of the present invention, and FIGS. 2 and 3 are conventional complementary MO
FIG. 2 is a cross-sectional view showing an example of an S transistor, FIG. 2 is a diagram for explaining a latch-up phenomenon, and FIG. 3 is a diagram showing measures taken against latch amplifiers.

Claims (1)

[Claims] (1) A second conductivity type MO consisting of a second conductivity type source region and a drain region formed in a first conductivity type semiconductor substrate
a first conductivity type MOS transistor formed in a second conductivity type well layer in the semiconductor substrate and formed around the second conductivity type MOS transistor, the first conductivity type MOS transistor comprising a first conductivity type source region and a drain region; a first conductivity type guard ring formed on one surface of the semiconductor substrate, a recessed recessed portion is formed on the other surface of the semiconductor substrate corresponding to at least immediately below the guard ring, and the guard ring is provided within the recessed portion. A complementary MOS transistor characterized by having a first conductivity type diffusion layer in contact with a ring.