JPH01300554A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a latchup and to improve integration of a semiconductor integrated circuit device by relatively displacing the surface positions of first and second conductivity type regions perpendicularly in the main face of a semiconductor substrate. CONSTITUTION:A stepwise region is formed on a semiconductor substrate 1, and a first MOS semiconductor element 23 and a second MOS semiconductor element 24 are formed on the recess and protrusion regions of the stepwise region. Accordingly, the elements 23, 24 are formed at a distance in three- dimensional manner in the planar and stepwise directions of the main face of the substrate to reduce the planar distance. Thus, an occurrence of a latchup can be suppressed, and the integration of a device can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a CMOS
(Complementary Metal 0x
This invention relates to a structure for achieving high integration of integrated circuit devices.

[Prior art] In a semiconductor integrated circuit device, n-channel MOS FETs (CMOS field effect transistors) are mounted on the same substrate.
A complementary MOS semiconductor device (hereinafter referred to as CMOS IC) is a device in which a p-channel MOS FET and a p-channel MOS FET are formed together and electrically connected to form a complementary circuit. FIG. 2 is a cross-sectional structural diagram of a conventional 0MOSIC, and the structure will be explained below based on this figure.

An n-well region 2, which is an n-type impurity region, is formed in a surface region of a p-type silicon substrate 1. A pMOS semiconductor element 3 is formed on the surface of the n-well region 2, and an nMOS semiconductor element 4 is formed on the surface of the p-type silicon substrate 1. A thick element isolation oxide film 5 is formed on the surface of the p-type silicon substrate 1 located between the pMOS semiconductor element 3 and the nMOS semiconductor element 4. The pMOs semiconductor element 3 is formed on the surface area of the n-well region 2 in a self-aligned manner with a gate electrode 7 which is laminated on the surface of the n-well region 2 with a gate oxide film 6 interposed therebetween. It is composed of a source region 8 and a drain region 9, which are p-type impurity diffusion regions. Furthermore, n M OS
The semiconductor element 4 includes a gate electrode 11 formed on the surface of the p-type silicon substrate 1 through a gate oxide film 10, and
It is composed of an n+ drain region 12 and an n+ source region 13, which are n-type impurity diffusion regions, formed on the surface of the p-type silicon substrate 1 in a self-aligned positional relationship with the gate electrode 11. Further, the surfaces of the pMOS semiconductor element 3 and the nMOS semiconductor element 4 are covered with an interlayer insulating film 14. Metal wiring layers 15a and 15b made of aluminum or the like are connected to predetermined impurity diffusion regions of the silicon substrate via contact holes 16 formed in interlayer insulating film 14.

These pMOS semiconductor device 3 and nMOS semiconductor device 4
are connected to each other by metal wires 15a and 15b to form an inverter circuit, the metal wire 15a is connected to the output terminal of the inverter, and each gate electrode 7.11 is connected to the input terminal of the inverter. Further, the p-type silicon substrate 1 is connected to the ground voltage vss.

[Problem to be solved by the invention] However, in a CMOSIC having such a structure,
Conventionally, the occurrence of latch-up phenomenon has been a problem.

That is, in a CMOS structure, a pnp parasitic bipolar transistor and an npn parasitic bipolar transistor, which are originally generated, combine to form a thyristor structure, and when external noise is added to this, an excessive current is generated between both source regions. This causes a latch-up phenomenon that disrupts the operation of the CMOS circuit. This latch-up phenomenon will be explained using FIG. 3.

In the figure, the CMOS IC includes a pnp parasitic bipolar transistor 17 with a p+ source region 8 as an emitter, an n well region 2 as a base, and a p-type silicon substrate 1 as a collector, and a pnp-type parasitic bipolar transistor 17 with an n+ source region 13 as an emitter and a p-type silicon substrate 1. is the base and n well region 2 is the collector.
A pn type parasitic bipolar transistor 18 is formed. Now, if a high positive external noise is applied between the external terminals VCC, v, and s, the reverse breakdown voltage between the n-well region 2 and the p-type silicon substrate 1 will be exceeded, and a current due to holes will flow in the p-type silicon substrate 1. arise. When this flows to the VCC terminal, a voltage drop occurs due to the substrate resistance ri of the p-type silicon substrate 1,
pn between p-type silicon substrate 1 and n+ source region 13
The junction is positively biased and an emitter current of the npn parasitic bipolar transistor 18 is generated. At this time, the electrons injected from the emitter (n1 source region 13) are np
The current passes through the base (p-type silicon substrate 1) of the n-type parasitic bipolar transistor 18, flows into the n-well region 2, and becomes a collector current. This collector current is
Since it is supplied from the external terminal VCC through the resistor rw of the n-well region 2, it causes a voltage drop across the resistor rw of the n-well region 2, and makes a positive bias between the p+ source region 8 and the n-well region 2, increasing the emitter current of the pnp parasitic bipolar transistor 17. arise.

As a result, p + source region 8, n well region 2 and p
A collector current due to holes flows between the mold silicon substrates 1,
This flows through the p-type silicon substrate 1 to the external terminal VSS. Because such a positive feedback loop is formed, current continues to flow as long as an appropriate voltage is applied between the external terminals Vcc1vss even if the external noise subsides. The collector currents of the parasitic bipolar transistors 17 and 18 increase at an accelerating rate due to the feedback amplification effect, resulting in a thyristor phenomenon.

For this reason, an overcurrent flows through both source regions 8.13 of the MOS type semiconductor element 3.4, and the Am electrode 15b or other extraction electrode connected to the source region 8.13 corresponding to the path of this overcurrent flows. There are also cases where it is destroyed and fused due to Joule heat caused by the current.

One method for preventing such a latch-up phenomenon is to reduce the current amplification factor of the pn l) type parasitic bipolar transistor 17 or the npn type parasitic bipolar transistor 18.

Specifically, the diffusion depth of the n-well region 2 is increased to form a pnp
The base width of the npn parasitic bipolar transistor 18 is increased by increasing the base width of the npn parasitic bipolar transistor 17, or by increasing the distance between the n well region 2 and the n+ source region 13. Therefore, traditional CMO
In the SIC, as shown in FIG.
It is necessary to form a distance Md from one end of the n+ drain region 12 to a predetermined distance, for example, 20 μm or more.

However, this has become a major problem as it increases the size of the CMOS IC structure and impedes higher integration of the device.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and provides an element structure that can prevent the latch-up phenomenon from occurring in a semiconductor integrated circuit device having a 0MOS structure, and can also improve the degree of integration. An object of the present invention is to provide a semiconductor integrated circuit device with high performance.

[Means for Solving the Problems] The present invention provides a semiconductor substrate including a first conductivity type region and a second conductivity type region formed adjacent to each other, and a semiconductor substrate including a first conductivity type region and a second conductivity type region formed adjacent to each other; a first channel having two conductivity types;
A MOS type semiconductor element and a second MOS type semiconductor element having a first conductivity type channel formed on the surface of a second conductivity type region, the first MOS type semiconductor element and the second MOS type semiconductor element are connected. It is a semiconductor integrated circuit device that constitutes a complementary circuit, and the first conductivity type region and the second conductivity type region are formed so that their surface positions are shifted from each other in a direction perpendicular to the main surface of the semiconductor substrate. Features.

[Operation] In order to prevent a latch-up phenomenon due to the thyristor structure of a parasitic bipolar transistor that is originally formed in a semiconductor integrated circuit device such as a CMOS IC, a first MOS type semiconductor element and a second MOS type semiconductor element are used. They are required to be formed a certain distance apart from each other.

In the present invention, a step region is formed on the surface of a semiconductor substrate, and a first MOS type semiconductor element and a second MOS type semiconductor element are formed in the recessed region and the convex region of this step, respectively. As a result, the first MOS type semiconductor element and the second MOS type semiconductor element are formed three-dimensionally apart from each other in the planar direction and the step direction of the main surface of the semiconductor substrate. The distance between the two MOS type semiconductor elements required to prevent the latch-up phenomenon is ensured by the three-dimensional distance. Therefore, compared to the conventional method where the distance between both MOS type semiconductor elements was secured in a two-dimensional manner, the two-dimensional distance can be reduced.

[Example] Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

1A to 1D are commercials according to an embodiment of the present invention.
FIG. 3 is a cross-sectional structure diagram showing the cross-sectional structure of an OS IC in the order of manufacturing steps. This will be explained below using this figure.

First, as shown in FIG. 1A, a resist 19 is applied on the surface of the p-type silicon substrate 1 and patterned to form an n-well region for 9MOs.

After that, using the patterned resist film 19, p
The mold silicon substrate 1 is etched and removed to a predetermined depth. The predetermined depth of this etching will be described later.

Thereafter, using one patterned resist as a mask, nJJ1 impurity such as phosphorus is ion-implanted to form an n-well region 2.

Next, as shown in FIG. 1B, after removing the resist 19, an element isolation oxide film 20 made of a thick oxide film is selectively formed on the surface of the p-type silicon substrate 1.

Among the surface regions of the p-type silicon substrate 1 separated by the element isolation oxidation H20, the recessed portions formed by removal by etching become pMOS formation regions 21, and the regions of the surface of the p-type silicon substrate 1 adjacent thereto are nMOS. This becomes the formation area.

Furthermore, as shown in FIG. 1C, a thin oxide film and a polysilicon layer are formed on the surface of the p-type silicon substrate 1 by CVD (Ch
chemical vapor deposition
n) by depositing and patterning using a method;
A gate oxide film 6 and a gate electrode 7 of a pMOS transistor and a gate oxide film 10 and a gate electrode 11 of a run risk (nMOS) are formed. Next, after covering the surface of the nMOS formation region 22 with a resist, p-type impurities such as boron are ion-implanted into the surface of the n-well region 2 of the pMOS formation region 21 to form a p+ source region 8 and a p+ drain region 9. do. Furthermore, after covering the surface of the 9MOS formation region 21 with a resist, the resist covering the surface of the nMOS formation region 22 is removed, and the p-type silicon substrate 1
An n-type impurity such as arsenic or phosphorus is ion-implanted into the surface of the substrate to form an n+ drain region 12 and an n+ source region 13 of an nMOS transistor. Through these steps, a 9MOS) run risk 23 is formed on the surface of the n-well region 2, which is a concave region of the p-type silicon substrate 1, and furthermore, a 9MOS) run risk 23 is formed on the surface of the p-type silicon substrate 1 adjacent to this.
Os) A run risk 24 is formed.

Finally, as shown in FIG. 1D, an interlayer insulating film 14 is formed on the surface of the p-type silicon substrate 1 on which the pMOs run risks 23 and the nMOS run risks 24 are formed. Then, a contact hole 16 for wiring is formed in this interlayer insulating film 14.

Thereafter, metal wiring layers 15a and 15b made of aluminum or the like are wired to complete the manufacturing of the device.

9MOS) run risk 23 and nMOS) run risk 24
and are interconnected to form an inverter circuit. That is, in the pMOS transistor 23, the p+ source region 8 is connected to the external terminal VCC of the power supply voltage, the gate electrode 7 is connected to the input terminal of the inverter, and the p+ drain region 9 is connected to the output terminal of the inverter. ing. In addition, the nMOS transistor 2
4, the n+ source region 13 is connected to the external terminal V5.4. The gate electrode 11 is connected to the input terminal of the inverter, and the n+ drain region 12 is connected to the output terminal. Further, the n-well region 2 is connected to the external terminal VCC of the power supply voltage, and the p-type silicon substrate 1 is connected to the external terminal VCC.
Connected to SS.

Here, the effect of preventing the latch-up phenomenon in a CMOSIC having a structure like this example will be explained. As described above, a parasitic bipolar transistor is inherently formed in a CMOSIC due to its structure. That is, one of them is the p+ source region 8 of the pMOS transistor 23.
, a pnp parasitic bipolar transistor formed between the n-well region 2 and the p-type silicon substrate 1;
s) An npn parasitic bipolar transistor formed between the run risk 24 and the n◆source region 13. As mentioned above, both parasitic bipolar transistors form a silicon risk structure and operate due to external noise, causing a latch-up phenomenon. Second, the latch-up phenomenon is prevented by lowering the current amplification factor of this bipolar transistor. In other words, the current amplification factor of the npn parasitic bipolar transistor can be reduced by widening its base region, that is, the region of the p-type silicon substrate 1.

Therefore, for example, p+ of the pMOS transistor 23
The end of the drain region 9 and n of the nMOS) run risk 24
Considering the distance between + and the end of the drain region 12 as a guideline, the distance 1Iild between them should be set wide. Conventionally, this distance has been manufactured to ensure, for example, 20 μm or more. In this embodiment, a pMOS (pMOS) run risk 23 and an nMOS transistor 24 are formed with a step on the surface of the p-type silicon substrate 1. Therefore, the effective distance of the base of the p-type silicon substrate 1, which becomes the base region of the npn-type parasitic bipolar transistor, is given by the sum of the horizontal distance M a + and the vertical distance d2, as shown in FIG. 1D. Therefore, if the distance between both transistors 23 and 24 required to prevent the latch-up phenomenon is, for example, 20 μm or more, this distance should be ensured by the sum of the horizontal distance 111d and the vertical distance d2. What is necessary is to determine the step structure of the CMOS IC. Therefore, in the etching removal process of the p-type silicon substrate 1 shown in FIG. 1A, it is sufficient to perform the etching removal to a depth corresponding to the above-mentioned vertical distance of 11 ft d 2 . It should be noted that the etching depth must also take into account effects such as prevention of breakage with the interlayer insulating film 14 and metal wiring layers 15a and 15b, which will be formed in a later process.

In this way, in the above embodiment, the n-well region 2 was formed in the etched region of the silicon substrate, but the transistor was formed so that the n-well region 2 was formed in a region other than the etched region of the silicon substrate. Good too.

Further, in the above embodiment, a structure having a p-type silicon substrate and an n-well region formed therein has been described, but the structure is not limited to this. I do not care.

[Effects of the Invention] As described above, in the present invention, the first MOS type semiconductor element and the second MOS type semiconductor element constituting the complementary circuit are configured with a step provided on the same substrate, so that it is possible to improve the structure of the planar element. By reducing the formation interval and ensuring a three-dimensional distance between both MOS semiconductor elements, it is possible to realize a semiconductor integrated circuit device that can suppress the occurrence of latch-up and improve the degree of integration of the device. .

[Brief explanation of the drawing]

FIGS. 1A, 1B, 1C, and 1D are cross-sectional structural diagrams showing the cross-sectional structure of an 0MOSIC according to an embodiment of the present invention in the order of its manufacturing steps. FIG. 2 is a cross-sectional structural diagram of a conventional CMOS IC. FIG. 3 is a schematic diagram of a parasitic silicon risk structure for explaining the latch-up phenomenon of a conventional CMOS IC.
1 is a p-type silicon substrate, 3 and 23 are pMOS semiconductor elements, 4.24 is an nMOS semiconductor element, 8 is a p+ source region, 9 is a p+ drain region, 12 is an n+ drain region, and 13 is an n+ source region. ing. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A semiconductor substrate including a first conductivity type region and a second conductivity type region formed adjacent to each other, and a second conductivity type channel formed in a surface region of the first conductivity type region. a first MOS type semiconductor element having a first conductivity type region; and a second MOS type semiconductor element having a first conductivity type channel region formed in a surface area of the second conductivity type region; In a semiconductor integrated circuit device in which two MOS type semiconductor elements are connected to form a complementary circuit, the first conductivity type region in which the first MOS type semiconductor element is formed and the first conductivity type region in which the second MOS type semiconductor element is formed. A semiconductor integrated circuit device, wherein the two conductivity type regions are formed such that their surface positions are relatively shifted from each other in a direction perpendicular to the main surface of the semiconductor substrate.