JPS6155950A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6155950A
JPS6155950A JP59178021A JP17802184A JPS6155950A JP S6155950 A JPS6155950 A JP S6155950A JP 59178021 A JP59178021 A JP 59178021A JP 17802184 A JP17802184 A JP 17802184A JP S6155950 A JPS6155950 A JP S6155950A
Authority
JP
Japan
Prior art keywords
semiconductor pellet
conductor
lead
semiconductor
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59178021A
Other languages
Japanese (ja)
Inventor
Kenji Miyajima
宮島　賢治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59178021A priority Critical patent/JPS6155950A/en
Publication of JPS6155950A publication Critical patent/JPS6155950A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To apply predetermined potential to a substrate for a semiconductor pellet by bonding the semiconductor pellet and a tape under the state in which a conductor enabling an ohmic contact is preset onto the back of the semiconductor pellet. CONSTITUTION:Lead nose sections 1a in lead frames 1 are bonded with an adhesive tape 2 so as to be arranged toward a space section 5. A conductor 3 for applying potential to the back side of a semiconductor pellet 4 is also formed onto the adhesive tape 2. The semiconductor pellet 4 is fixed to the conductor 3 and the adhesive tape 2 through conductive adhesives 5. The lead nose sections 1a and electrodes for the semiconductor pellet 4 are connected by bonding wires 7, and lead nose sections 1b and the conductor 3 are also connected by bonding wires 7. The whole is molded with a molding resin 8.

Description

【発明の詳細な説明】 （発明の技術分野〕 本発明は半導体装置に関する。[Detailed description of the invention] (Technical field of invention) The present invention relates to a semiconductor device.

（発明の技術的背景〕 一般に半導体装置としては、ガラスまたはガラスエポキ
シ種層板を用いたパッケージタイプと、リードフレーム
を用いてプラスチックで持止したプラスチックパッケー
ジタイプとがある。(Technical Background of the Invention) Semiconductor devices generally include a package type using a glass or glass epoxy seed layer, and a plastic package type using a lead frame and supported by plastic.

プラスチックパッケージタイプの半導体装置では、アイ
ランドとよばれる半尋体ペレットｌｆｉ部の周辺に複数
のリードが接近して設けられ、このリードと半導体ペレ
ットの電極部とがワイヤボンディングされ、しかるのち
に半導体ペレットおよびリードを含む部分を樹脂封止し
て半導体装置が完成する。In a plastic package type semiconductor device, a plurality of leads are provided close to each other around the LFI part of a half-body pellet called an island, and the leads and the electrode part of the semiconductor pellet are wire-bonded, and then the semiconductor pellet is Then, the portion including the leads is sealed with resin to complete the semiconductor device.

このようなアイランドを用いる半導体装置では、素子の
小型化とａ集積化が進むにしたがって、半導体ペレット
とリードとのワイヤボンディングに伴う種々の問題が発
生してきたため、これを解決する手段としてリードフレ
ームのアイランドの替わりに接着テープを用いる方法が
提案されている。In semiconductor devices using such islands, various problems have arisen with wire bonding between semiconductor pellets and leads as devices become smaller and more integrated. A method has been proposed in which adhesive tape is used instead of islands.

たとえば特公昭５６−２０７０４号公報や特開昭５４−
１２６４６５号公報には、このようなアイランドに接着
テープを用いる技術がＯｉｌ示されている。ここで示さ
れている技術では、従来アイランドが存在した部分に半
導体ペレット保持用のテープを位置させ、このテープを
周辺のリードに接着保持して固定し、テープ上の半導体
ペレットとリードとの間にワイヤボンディングを施すよ
うにしている。For example, Japanese Patent Publication No. 56-20704 and Japanese Patent Publication No. 54-
Japanese Patent No. 126465 discloses a technique using adhesive tape for such an island. In the technology shown here, a tape for holding semiconductor pellets is placed in the area where an island conventionally existed, and this tape is adhesively held and fixed to the surrounding leads, and the semiconductor pellets on the tape and the leads are fixed. wire bonding is applied to the

〔背景技術の問題点〕[Problems with background technology]

特開昭５４−１２６４６５号公報によれば金属板材をエ
ツチング等によりパターンニングすることによってリー
ドフレームを形成する。このようにして形成されたリー
ドフレームはアイランド部に相当する部分が空間となっ
ており、その周りに多数のリードが先端部をその空間部
に向けるように設けられている。そして各リードの先端
部に張り付けるようにして、空間部に接着テープを配設
し、この接着テープの接着剤を利用して半導体ペレット
を貼着固定し、次に半導体ペレットのｍ１部とリードの
インナリード部とをワイヤボンディングして接続し、そ
の侵エポキシ樹脂により樹脂封止して半導体装置を構成
するようにしている。According to Japanese Unexamined Patent Publication No. 54-126465, a lead frame is formed by patterning a metal plate material by etching or the like. The lead frame thus formed has a space corresponding to the island portion, and a large number of leads are provided around the space with their tips directed toward the space. Then, an adhesive tape is placed in the space so as to be pasted on the tip of each lead, and the semiconductor pellet is stuck and fixed using the adhesive of this adhesive tape, and then the m1 part of the semiconductor pellet and the lead are attached. The semiconductor device is constructed by connecting the semiconductor device to the inner lead portion of the semiconductor device by wire bonding and sealing the semiconductor device with an epoxy resin.

しかしこのような半導体装置では、半導体ペレットの裏
面から？′ｌｌｆ極を取り出したり、また半導体ペレッ
トの裏面に所定の電位を印加することが不可能である。However, in this kind of semiconductor device, is it possible to see from the back side of the semiconductor pellet? It is impossible to take out the 'llf electrode or to apply a predetermined potential to the back surface of the semiconductor pellet.

このような事情は特公昭５６−２０７０４号公報の技術
によっても同様であった。This situation was also the same with the technique disclosed in Japanese Patent Publication No. 56-20704.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情を考慮してなされたもので、半導体ペ
レットの基板に所定の電位を印加することができる半導
体装置を提供することを目的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device that can apply a predetermined potential to a substrate of a semiconductor pellet.

（発明の概要） 上記目的を達成するために、本発明による半導体装置は
、空間部のまわりに位置した複数のリードと、前記″！
！！間部のまわりのリードに接着保持され前記空間部に
位置するテープと、このテープ上の所定位置に貼着され
た導電体と、少なくともこの導電体の一部にオーミック
接触するよう前記テープ上に配設された半導体ペレット
とを有し、この半導体ペレットの電橋部と前記リードお
よび前記導電体と前記リードとをそれぞれ電気的に接続
したことを特徴とする。(Summary of the Invention) In order to achieve the above object, a semiconductor device according to the present invention includes a plurality of leads located around a space, and the ``!
! ! a tape adhesively held to the leads around the gap and located in the space; a conductor stuck to a predetermined position on this tape; The semiconductor pellet is characterized in that the electric bridge portion of the semiconductor pellet is electrically connected to the lead, and the conductor and the lead are electrically connected to each other.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づいて詳細に説明する。 The present invention will be described in detail below based on examples.

第１図は本発明の一実施例によるプラスチックパッケー
ジタイプの半導体装置の断面図であり、第２図はその平
面図である。FIG. 1 is a sectional view of a plastic package type semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof.

リードフレーム１のリード先端部１ａは、接着剤テープ
２に、空間１６に向けて配列するように接着されている
。半導体ペレット４の裏側に電位を加えるための１ｍ休
体も接着剤テープ２上に設けられている。半導体ペレッ
ト４は導電性接着剤５を介して導電体３１５よび接着剤
テープ２に固着されている。リード先端部１ａと半導体
ペレット４のｆｆｉ極とはボンディングワイヤ７により
接続されており、また、リード先端部１ｂと導電体３と
もボンディングワイヤ７により接続されている。Lead tip portions 1a of lead frame 1 are adhered to adhesive tape 2 so as to be aligned toward space 16. A 1 m break is also provided on the adhesive tape 2 for applying a potential to the back side of the semiconductor pellet 4. The semiconductor pellet 4 is fixed to the conductor 315 and the adhesive tape 2 via the conductive adhesive 5. The lead tip 1a and the ffi pole of the semiconductor pellet 4 are connected by a bonding wire 7, and the lead tip 1b and the conductor 3 are also connected by a bonding wire 7.

そして全体がモールド樹脂８によりモールドされている
。The whole is molded with mold resin 8.

この半導体装置の製造方法を説明する。まずリードフレ
ーム１のリード先端部１ａを空間部６に向けて配列し、
この空間部６に位置するように接着剤テープ２を用意し
、この接着剤テープ２の端部に周りのリード先端部１ａ
を接着保持する。そして、このリードフレーム１を自動
ペレット接着機（オートマウンタ）に複数個セットする
。ついで、金メッキまたは銀メッキを施した約０．０２
ｍの厚さで０．２部ｍのテープ状ＩＩ体３をオートマウ
ンタのブリフォーマ部にセットする。そしてこのリード
フレーム１が供給移送され、ブリフォーマポジションが
所定位置にくると、この導電体３が２〜３＃１Ｉ１１の
長さに自動的に切断されて接着剤テープ２の接着面のあ
らかじめ定められた位置に接着される。A method of manufacturing this semiconductor device will be explained. First, the lead tips 1a of the lead frame 1 are arranged toward the space 6,
An adhesive tape 2 is prepared so as to be located in this space 6, and the end of the adhesive tape 2 is attached to the surrounding lead tip 1a.
Glue and hold. Then, a plurality of lead frames 1 are set in an automatic pellet bonding machine (auto mounter). Then, about 0.02 gold plated or silver plated
A tape-shaped II body 3 having a thickness of 0.2 parts m is set in the preformer section of an automounter. When the lead frame 1 is fed and transferred and the preformer position is at a predetermined position, the conductor 3 is automatically cut into lengths of 2 to 3#1I11 to predetermine the adhesive surface of the adhesive tape 2. glued in place.

このさい、導電体３は最終的に半導体ペレット４がテー
プ２上に塔載されたさいにペレット４の境に半分半分に
接着されるような位置にプリセットされる。そののち、
Ｇｍ性接着剤５たとえば日立化成製ＥＮ４０００　（商
品名）を滴下ぎせてその上に半導体ペレット４を押し付
けて固定させ、１００〜２００℃で１〜３時間焼結して
完全固着する。At this time, the conductor 3 is preset in such a position that when the semiconductor pellet 4 is finally placed on the tape 2, it will be glued in half to the border of the pellet 4. after that,
A Gm-based adhesive 5, such as EN4000 (trade name) manufactured by Hitachi Chemical, is dropped onto the adhesive, the semiconductor pellet 4 is pressed and fixed thereon, and the semiconductor pellet 4 is sintered at 100 to 200° C. for 1 to 3 hours to be completely fixed.

その後、半導体ペレット４上の［ｉとリード先端部１ａ
とをワイヤーボンディングする。さらに導電体３と所定
のリード先端部１ｂとをワイヤーボンディングする。こ
れらの作業が終了した後にエポキシ樹脂等を用いてトラ
ンクファーモールド法等により樹脂封止し、半導体装置
が完成する。After that, [i on the semiconductor pellet 4 and the lead tip 1a]
and wire bonding. Further, the conductor 3 and a predetermined lead tip portion 1b are wire-bonded. After these operations are completed, resin sealing is performed using epoxy resin or the like by trunk firm molding or the like, and the semiconductor device is completed.

このように、本実施例では半導体ペレットの裏面にオー
ミック接触を可能とするような導電体をプリセットした
状態で半導体ペレットとテープとを接着するようにした
ため、半導体ペレットの裏面からの電位を必要とする半
導体装置に適用することが可能となる。したがって特公
昭５６−２０７０４号公報や特開昭５４−１２６４６５
号公報に示されるようなボンディング時のリード変形や
ワイヤショート不良等の防止効果を発揮しつつ、しかも
裏面電位の確保が可能となる。In this way, in this example, the semiconductor pellet and the tape were bonded with a conductor preset on the back surface of the semiconductor pellet to enable ohmic contact, so a potential from the back surface of the semiconductor pellet was not required. This makes it possible to apply this method to semiconductor devices. Therefore, Japanese Patent Publication No. 56-20704 and Japanese Unexamined Patent Publication No. 54-126465
While exhibiting the effect of preventing lead deformation and wire short defects during bonding as shown in the above publication, it is possible to secure the back surface potential.

なお、先の実施例ではリードフレームを用いたプラスチ
ックパッケージタイプの半導体装置を具体例として説明
したが、ガラスエポキシ型やセラミツ型パッケージの半
導体装置にも本発明を適用することができる。またリー
ドフレームを用いないタイプの半導体装置にも適用可能
である。In the previous embodiment, a plastic package type semiconductor device using a lead frame was explained as a specific example, but the present invention can also be applied to a glass epoxy type or ceramic type package semiconductor device. It is also applicable to a type of semiconductor device that does not use a lead frame.

〔発明の効果〕〔Effect of the invention〕

以上の通り本発明によれば半導体ペレットの基板に所定
の電位を印加することができる。As described above, according to the present invention, a predetermined potential can be applied to the substrate of the semiconductor pellet.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図はこの発明の一実施例を示ず半導体
装置の構成図で、第１図はその断面図、第２図はこの平
面図である。 １・・・リードフレーム、１ａ・・・リード先端部、２
・・・接着剤テープ、３・・・導電体、４・・・半導体
ペレット、５・・・導電性接着剤。1 and 2 do not show one embodiment of the present invention, but are configuration diagrams of a semiconductor device, with FIG. 1 being a cross-sectional view thereof, and FIG. 2 being a plan view thereof. 1...Lead frame, 1a...Lead tip, 2
... Adhesive tape, 3... Conductor, 4... Semiconductor pellet, 5... Conductive adhesive.

Claims (1)

【特許請求の範囲】[Claims] 　空間部のまわりに位置した複数のリードと、前記空間
部のまわりのリードに接着保持され前記空間部に位置す
るテープと、このテープ上の所定位置に貼着された導電
体と、少なくともこの導電体の一部にオーミック接触す
るよう前記テープ上に配設された半導体ペレットとを有
し、この半導体ペレットの電極部と前記リードおよび前
記導電体と前記リードとをそれぞれ電気的に接続したこ
とを特徴とする半導体装置。a plurality of leads located around the space, a tape adhesively held to the leads around the space and located in the space, a conductor affixed to a predetermined position on the tape, and at least the conductor. and a semiconductor pellet disposed on the tape so as to make ohmic contact with a part of the body, and the electrode part of the semiconductor pellet and the lead, and the conductor and the lead are electrically connected, respectively. Characteristic semiconductor devices.
JP59178021A 1984-08-27 1984-08-27 Semiconductor device Pending JPS6155950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59178021A JPS6155950A (en) 1984-08-27 1984-08-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59178021A JPS6155950A (en) 1984-08-27 1984-08-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6155950A true JPS6155950A (en) 1986-03-20

Family

ID=16041187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59178021A Pending JPS6155950A (en) 1984-08-27 1984-08-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6155950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117790A (en) * 1987-10-30 1989-05-10 Chemo Sero Therapeut Res Inst Recombinant plasmid integrated with gene coding prealbumin and production of prealbumin using said plasmid

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117790A (en) * 1987-10-30 1989-05-10 Chemo Sero Therapeut Res Inst Recombinant plasmid integrated with gene coding prealbumin and production of prealbumin using said plasmid

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