JPH0432243A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPH0432243A
JPH0432243A JP2137100A JP13710090A JPH0432243A JP H0432243 A JPH0432243 A JP H0432243A JP 2137100 A JP2137100 A JP 2137100A JP 13710090 A JP13710090 A JP 13710090A JP H0432243 A JPH0432243 A JP H0432243A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
tape
terminal
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2137100A
Other languages
Japanese (ja)
Other versions
JP2875591B2 (en
Inventor
Ken Ogura
謙 小椋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2137100A priority Critical patent/JP2875591B2/en
Publication of JPH0432243A publication Critical patent/JPH0432243A/en
Application granted granted Critical
Publication of JP2875591B2 publication Critical patent/JP2875591B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the area of a chip and to prevent an electric short-circuit by adhering an integrated circuit chip on a mount in the same plane as an external connection terminal, adhering a tape to the surfaces, sealing its rear surface with an insulating material, peeling the tape, and then forming a metal wiring between bonding pads by a direct plotting method. CONSTITUTION:A mount 12 is coated with conductive paste 15, an integrated circuit chip 14 is adhered, and electrically connected. Thus, the surface of the chip 14 becomes the same in height as that of a terminal 13. Then, a tape 26 with adhesive is bonded to the surface of the terminal 13 and the surface of the chip 14. Then, the tape 16 is inverted upside down, sealer such as epoxy resin is dropped or screened on the chip mount, and a molding part 17 is formed. Thereafter, after the tape 16 is peeled, in order to connect a bonding pad 18 to the terminal 13, a metal wiring 19 is formed directly (without mask, etc.,) by an ion beam method.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は、半導体集積回路におけるチップと外部端子
との接続を同一平面でできるようにした半導体素子の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor element in which a chip in a semiconductor integrated circuit and an external terminal can be connected on the same plane.

（従来の技術） 従来、この種の半導体集積回路は半導体チップと外部端
子と接続するのに金属ワイヤ（ＡｕまたはＣｕ）を用い
接続部を熱圧着する方法が一般的である。(Prior Art) Conventionally, in this type of semiconductor integrated circuit, a metal wire (Au or Cu) is generally used to connect a semiconductor chip and an external terminal, and the connection portion is bonded by thermocompression.

第２図は従来の半導体集積回路のチップと外部端子との
接続状態を示す斜視図であり、この第２図における１は
チップ保持台であり、このチップ保持台１上に半導体チ
ップ２が導電性ペーストで接着されて、両者が電気的に
接続され、かつ機械的に保持されている。FIG. 2 is a perspective view showing the state of connection between a chip and an external terminal of a conventional semiconductor integrated circuit. 1 in this FIG. The two are electrically connected and mechanically held together by adhesion using adhesive paste.

この半導体チップ２の表面には、チップの外部端子、い
わゆるパッド部３が形成されている。On the surface of this semiconductor chip 2, external terminals of the chip, so-called pad portions 3, are formed.

この状態において、従来パッド部３と外部端子４とは、
ワイヤ５により接続されている。ワイヤ５とパッド部３
とはワイヤ５を熱圧着あるいは超音波圧着により圧着部
６で圧着されて接続される。In this state, the conventional pad portion 3 and external terminal 4 are
They are connected by a wire 5. Wire 5 and pad part 3
The wire 5 is connected to the wire 5 by being crimped at the crimping part 6 by thermocompression bonding or ultrasonic crimping.

同様にして、外部端子４とワイヤ５も熱圧着あるいは超
音波Ｖ着により圧着部７で圧着されて接続される。Similarly, the external terminal 4 and the wire 5 are also crimped and connected at the crimping portion 7 by thermocompression bonding or ultrasonic V-bonding.

この後、前記半導体チップ２と外部端子４との接続部は
樹脂（例えばエポキシ樹脂）で封止（モールディング）
され、完成品となる。After this, the connection portion between the semiconductor chip 2 and the external terminal 4 is sealed (molded) with resin (for example, epoxy resin).
and becomes the finished product.

（発明が解決しようとする課！１） しかしながら、上記構成の半導体集積回路では、ワイヤ
５と半導体チップ２間がワイヤ５の垂れ下がりにより、
電気的にショートする事故が発生するという問題点があ
った。(Problem to be solved by the invention! 1) However, in the semiconductor integrated circuit having the above configuration, the wire 5 hangs down between the wire 5 and the semiconductor chip 2.
There was a problem in that electrical short-circuit accidents occurred.

また、パッド部３が１００ｎ〜８０ｎ口と大きいこと、
およびパッド部３は半導体チップ２の周辺のみに限定さ
れるという制約があった。In addition, the pad portion 3 is large with an opening of 100n to 80n,
Furthermore, there is a restriction that the pad portion 3 is limited only to the periphery of the semiconductor chip 2.

この発明は前記従来技術が持っている問題点のうち、ワ
イヤと半導体チップ間が電気的にショートする事故が発
生する点と、パッド部が半導体チップ周辺のみに限定さ
れる点について解決した半導体素子の製造方法を提供す
るものである。This invention is a semiconductor device that solves the problems of the prior art, such as the occurrence of electrical shorts between the wire and the semiconductor chip, and the fact that the pad portion is limited only to the periphery of the semiconductor chip. The present invention provides a method for manufacturing.

（課題を解決するための手段） この発明は前記問題点を解決するために半導体素子の製
造方法において、外部接続用の端子の表面と半導体集積
回路チップの表面が同一表面となるように、マウント部
に半導体集積回路チップを接着した状態で裏面側を絶縁
材で封止した後に端子と半導体集積回路チップのボンデ
ィングパッド間に直接描画法により金属配線を形成する
工程を導入したものである。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device in which mounting is performed so that the surface of a terminal for external connection and the surface of a semiconductor integrated circuit chip are on the same surface. This method introduces a process in which a semiconductor integrated circuit chip is adhered to the semiconductor integrated circuit chip, the back side is sealed with an insulating material, and then metal wiring is formed by direct writing between the terminal and the bonding pad of the semiconductor integrated circuit chip.

（作　用） この発明によれば、半導体素子の製造方法において、以
上のような工程を導入したので、端子と半導体集積回路
チップの表面が同一表面にした状態で、その両者の裏面
側を絶縁材で封止し、表面側において端子と半導体集積
回路チップのボンディングパッド間に直接描画法で金属
配線を形成して、この両者間を切れ目なく水平に配線で
き、したがって、前記問題点を除去できる。(Function) According to the present invention, since the above-described steps are introduced in the method for manufacturing a semiconductor element, the terminals and the semiconductor integrated circuit chip can be made on the same surface, and the back surfaces of both can be insulated. The semiconductor integrated circuit chip is encapsulated with metal, and metal wiring is formed using a direct drawing method between the terminal and the bonding pad of the semiconductor integrated circuit chip on the front side, allowing horizontal wiring between the two without any breaks, thus eliminating the above-mentioned problem. .

（実施例） 以下、この発明の半導体素子の製造方法の実施例につい
て図面に基づき説明する。第１図（ａ）〜第１図（ロ）
はその一実施例の工程説明用の概略説明図である。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1 (a) to Figure 1 (b)
1 is a schematic explanatory diagram for explaining the process of one example.

まず、第１図（ａ）はリードフレームを平面的に示した
状態であり、薄板金属を格子状に打ち抜いたいわゆるリ
ードフレーム１１は薄板金属の打ち抜き、エツチングな
どにより行われるが、これらに限定されるものではない
。First, FIG. 1(a) shows a lead frame in a plan view, and the so-called lead frame 11, which is formed by punching out a thin metal sheet in a lattice shape, is formed by punching a thin sheet metal, etching, etc., but is not limited to these methods. It's not something you can do.

この実施例においては、リードフレーム１１中に半導体
チップを載置するマウント部１２の形状の断面は第１図
（ロ）のごとくになっている、そして、端子１３の形状
は同じく第１図（ｂ）のごとくになっている。In this embodiment, the cross section of the mount portion 12 on which the semiconductor chip is placed in the lead frame 11 is as shown in FIG. b).

次に、第１図（ｃ）に示すように、マウント部１２上に
導電性ペースト１５を塗布して、この導電性ペースト１
５に集積回路チップ１４を接着するとともに、マウント
部１２と半導体集積回路チップ１４を電気的に接続する
。Next, as shown in FIG. 1(c), a conductive paste 15 is applied on the mount part 12, and
At the same time, the integrated circuit chip 14 is bonded to the mount portion 12 and the semiconductor integrated circuit chip 14 is electrically connected to the mount portion 12 and the semiconductor integrated circuit chip 14 .

かくして、半導体集積回路チップ１４の表面と端子１３
の表面の高さの位置は同じ高さとなる。Thus, the surface of the semiconductor integrated circuit chip 14 and the terminal 13
The height position of the surface of is the same height.

次に、第１図（ロ）に示すように、端子１３の表面と半
導体集積回路チップ１４の表面に接着剤の付着したテー
プ２６を張り付ける。これらの作業は流れ作業として連
続的に行なうことが可能である。Next, as shown in FIG. 1(b), a tape 26 with an adhesive attached is pasted on the surface of the terminal 13 and the surface of the semiconductor integrated circuit chip 14. These operations can be performed continuously as assembly line operations.

すなわち、リードフレーム１１もテープ状態が可能であ
るから、実際上テープを張り付ける動作となる。That is, since the lead frame 11 can also be in a tape state, this is actually an operation of pasting tape.

その後、このテープ１６は第１図（ｅ）に示すように、
上下を反転し、チップマウント上にエポキシ樹脂、ポリ
イミド樹脂、あるいはシリコン樹脂などの封止剤を滴下
あるいは捺印（スクリーン）してモールド部１７を形成
する。Thereafter, this tape 16 is as shown in FIG. 1(e).
The chip mount is turned upside down and a sealing agent such as epoxy resin, polyimide resin, or silicone resin is dropped or stamped (screened) on the chip mount to form a mold portion 17.

このモールド部１７を形成した後、このモールド部１７
に適した温度で樹脂溶剤を揮発させ、また樹脂を反応さ
せるべく、ベーキングする。その温度は５０°Ｃ〜４０
０℃の温度である。After forming this mold part 17, this mold part 17
Baking is performed at a temperature suitable for volatilizing the resin solvent and causing the resin to react. Its temperature is 50°C ~ 40°C
The temperature is 0°C.

その後、第１図（ｆ）に示すように、上記テープ１６を
引き剥がし、テープ１６を除去する。Thereafter, as shown in FIG. 1(f), the tape 16 is peeled off and removed.

次に、テープ１６の剥離後、テープ１６の接着剤により
、半導体集積回路チップ１４の表面とモールド部１７の
表面および端子１３、マント部１２の表面に付着した接
着剤の残渣を除去するために洗浄する。Next, after peeling off the tape 16, the adhesive of the tape 16 is used to remove adhesive residues that have adhered to the surface of the semiconductor integrated circuit chip 14, the surface of the mold section 17, the terminals 13, and the surfaces of the mantle section 12. Wash.

次いで、第１図（６）に示すように、ボンデイングバッ
ド１８と端子１３とを接続するために、イオンビーム法
により、直接（マスク等を介さずに）第１図面に示すよ
うに、金属配線１９を形成する。Next, as shown in FIG. 1 (6), in order to connect the bonding pad 18 and the terminal 13, metal wiring is formed directly (without using a mask or the like) by the ion beam method as shown in the first drawing. form 19.

金属を直接描画的に堆積する方法はイオンビーム法の他
に、金属化合物ガス中にレーザビームを所望金属配線形
成場所に照射して堆積する方法も可能であり、堆積方法
に限定されるものでない。In addition to the ion beam method, the method for depositing metal by direct writing is not limited to the deposition method, and it is also possible to deposit the metal by irradiating the desired metal wiring formation location with a laser beam in a metal compound gas. .

すなわち、マスクを介さずに直接的に金属配線１９を形
成できる方法ならば、どのような方法でも、この発明に
は適用できる。That is, any method that can directly form the metal wiring 19 without using a mask can be applied to the present invention.

なお、金属配線材の種類もＭ９Ｍ化合物、ＡｕＪＩＴｉ
超電導材など特に限定されるものでないことは言うまで
もない。In addition, the types of metal wiring materials include M9M compound and AuJITi.
Needless to say, the material is not particularly limited to superconducting materials.

さらに、リードフレーム１１も金属板のみならずプラス
チックに金属端子を形成した連続リボンタイプを使用す
ることも可能であり、特に限定されるものではない。Further, the lead frame 11 is not limited to a particular metal plate, and may be of a continuous ribbon type made of plastic with metal terminals formed thereon.

（発明の効果） 以上詳細に説明したように、この発明によれば、パッケ
ージの端子と半導体集積回路チップとを同一平面として
両者をテープで接着するとともに、その反対側の端子と
半導体集積回路チップ間を絶縁材で充填し、テープの剥
離後、端子と半導体集積回路チップのボンディングパッ
ド間にイオンビーム等により直接金属を堆積して金属配
線を切れ目なく形成するようにしたものである。(Effects of the Invention) As described above in detail, according to the present invention, the terminals of the package and the semiconductor integrated circuit chip are bonded to each other with tape on the same plane, and the terminals on the opposite side and the semiconductor integrated circuit chip are bonded together using tape. The gap is filled with an insulating material, and after the tape is peeled off, metal is deposited directly between the terminal and the bonding pad of the semiconductor integrated circuit chip using an ion beam or the like to form seamless metal wiring.

従って電流容量で決定される開口部は、数−〜ザブーの
極めて小さな開口部でよく、またワイヤボンディングの
よ・うにボンディング時に機械的圧力を生じることがな
く、半導体集積回路チップの表面の中央部などのいかな
る所でも接続できるので、チップ面積縮小が可能である
。Therefore, the opening determined by the current capacity can be an extremely small opening on the order of several tens of times, and unlike wire bonding, no mechanical pressure is generated during bonding, and the opening can be placed in the center of the surface of the semiconductor integrated circuit chip. Since it can be connected at any location, such as, it is possible to reduce the chip area.

さらに、ワイヤの垂れ下がりによる半導体集積回路チッ
プへの電気的シラ−１−を防止できる。Furthermore, electrical damage to the semiconductor integrated circuit chip due to hanging wires can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）ないし第１図（５）はこの発明の実施例の
工程説明用の概略説明図、第２図は従来の半導体チップ
と外部端子との接続状態を示す斜視図である。 １１・・・リードフレーム、１２・・・マウント部、１
３・・・端子、１４・・・半導体集積回路チップ、１５
・・・導電性ペースト、１６・・・テープ、１７・・・
モールド部、１８・・・ボンディングパッド、１９・・
・金属配線。 １”＞−ｙフ゛イイオ縛１お ４・外鼾Ｙ熱） ５・ワイヤ ６．７・斥肩軒 糸イ、墳５ｔｎ−？鷲瞬レイ本＋４．フ・ヒタ■ア）１
＠Ｉｎ計１匁景受、り）俯足りの第２図FIGS. 1(a) to 1(5) are schematic explanatory diagrams for explaining the process of an embodiment of the present invention, and FIG. 2 is a perspective view showing a state of connection between a conventional semiconductor chip and external terminals. 11...Lead frame, 12...Mount part, 1
3...Terminal, 14...Semiconductor integrated circuit chip, 15
... Conductive paste, 16... Tape, 17...
Mold part, 18... Bonding pad, 19...
・Metal wiring. 1”>-y Fiiio binding 1 4・Outside snoring Y fever) 5・Wire 6.7・Repulsion shoulder eave thread I, tomb 5tn−? Washi Shunrei book + 4. F・Hita ■A) 1
＠In total 1 momekeiuke, ri) 2nd figure of the lower part

Claims (1)

【特許請求の範囲】 （ａ）外部接続用の端子の表面と、半導体集積回路チッ
プの表面を同一平面となるように、この半導体集積回路
チップをマウント部に接着し、上記端子の表面と半導体
集積回路チップの表面とにテープを接着する工程と、 （ｂ）上記端子と上記半導体集積回路チップの裏面側に
絶縁材で封止する工程と、 （ｃ）上記テープの剥離後、上記端子と上記半導体集積
回路チップのボンディングパッド間に直接描画法により
金属配線を形成する工程と、 よりなる半導体素子の製造方法。[Claims] (a) The semiconductor integrated circuit chip is adhered to the mount part so that the surface of the terminal for external connection and the surface of the semiconductor integrated circuit chip are on the same plane, and the surface of the terminal for external connection and the surface of the semiconductor integrated circuit chip are (b) sealing the terminal and the back side of the semiconductor integrated circuit chip with an insulating material; (c) after peeling off the tape, bonding the tape to the surface of the semiconductor integrated circuit chip; A method for manufacturing a semiconductor device, comprising: forming metal wiring between bonding pads of the semiconductor integrated circuit chip by a direct writing method.
JP2137100A 1990-05-29 1990-05-29 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2875591B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2137100A JP2875591B2 (en) 1990-05-29 1990-05-29 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2137100A JP2875591B2 (en) 1990-05-29 1990-05-29 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0432243A true JPH0432243A (en) 1992-02-04
JP2875591B2 JP2875591B2 (en) 1999-03-31

Family

ID=15190861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2137100A Expired - Fee Related JP2875591B2 (en) 1990-05-29 1990-05-29 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2875591B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850690A (en) * 1995-07-11 1998-12-22 De La Rue Cartes Et Systemes Sas Method of manufacturing and assembling an integrated circuit card
US7131183B2 (en) * 2004-04-26 2006-11-07 Ford Motor Company Screw in high voltage housing terminal for ignition coil
JP2008226913A (en) * 2007-03-08 2008-09-25 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850690A (en) * 1995-07-11 1998-12-22 De La Rue Cartes Et Systemes Sas Method of manufacturing and assembling an integrated circuit card
US7131183B2 (en) * 2004-04-26 2006-11-07 Ford Motor Company Screw in high voltage housing terminal for ignition coil
JP2008226913A (en) * 2007-03-08 2008-09-25 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JP2875591B2 (en) 1999-03-31

Similar Documents

Publication Publication Date Title
JP2816239B2 (en) Resin-sealed semiconductor device
JP3304705B2 (en) Manufacturing method of chip carrier
JP2001024135A (en) Manufacture of semiconductor device
JPH0870084A (en) Semiconductor package and its preparation
JPH041503B2 (en)
JP2004153220A (en) Lead frame, its manufacturing method, plastic molding semiconductor device and its manufacturing device
JPH04277636A (en) Preparation of semiconductor device
JPH08148603A (en) Ball grid array type semiconductor device and manufacture thereof
US5308797A (en) Leads for semiconductor chip assembly and method
JPH07321244A (en) Electronic part, and manufacture of electronic part
EP0135416A1 (en) Integrated circuit having a pre-attached conductive mounting media and method of making the same
JPH0432243A (en) Manufacture of semiconductor element
JPS62232948A (en) Lead frame
JPH01196153A (en) Resin-sealed semiconductor device
JP2001077268A (en) Resin sealed semiconductor device and manufacture thereof
JPH0817870A (en) Semiconductor device
JP3691790B2 (en) Semiconductor device manufacturing method and semiconductor device manufactured by the method
JPH11186467A (en) Semiconductor device, lead frame used at manufacturing the device, and manufacture of lead frame
JP2003017644A (en) Method of fabricating resin-sealed semiconductor device
JP3783648B2 (en) Wiring board and method of manufacturing semiconductor device using the same
JPS5930538Y2 (en) semiconductor equipment
JPS62263665A (en) Lead frame and semiconductor device using thesame
JPS63185035A (en) Semiconductor device
JPH10303227A (en) Semiconductor package and its manufacture
JPH07249708A (en) Semiconductor device and its mounting structure

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees