JPS6153745B2 - - Google Patents

Info

Publication number
JPS6153745B2
JPS6153745B2 JP57197327A JP19732782A JPS6153745B2 JP S6153745 B2 JPS6153745 B2 JP S6153745B2 JP 57197327 A JP57197327 A JP 57197327A JP 19732782 A JP19732782 A JP 19732782A JP S6153745 B2 JPS6153745 B2 JP S6153745B2
Authority
JP
Japan
Prior art keywords
data
storage
error
stored
buffer storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57197327A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5987683A (ja
Inventor
Noryuki Toyoki
Masatake Iwato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57197327A priority Critical patent/JPS5987683A/ja
Publication of JPS5987683A publication Critical patent/JPS5987683A/ja
Publication of JPS6153745B2 publication Critical patent/JPS6153745B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57197327A 1982-11-10 1982-11-10 スワツプ方式のバツフアストレイジの制御方法 Granted JPS5987683A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57197327A JPS5987683A (ja) 1982-11-10 1982-11-10 スワツプ方式のバツフアストレイジの制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57197327A JPS5987683A (ja) 1982-11-10 1982-11-10 スワツプ方式のバツフアストレイジの制御方法

Publications (2)

Publication Number Publication Date
JPS5987683A JPS5987683A (ja) 1984-05-21
JPS6153745B2 true JPS6153745B2 (enrdf_load_stackoverflow) 1986-11-19

Family

ID=16372617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57197327A Granted JPS5987683A (ja) 1982-11-10 1982-11-10 スワツプ方式のバツフアストレイジの制御方法

Country Status (1)

Country Link
JP (1) JPS5987683A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891897B2 (ja) * 1995-04-14 1999-05-17 甲府日本電気株式会社 ストアインキャッシュの障害処理システム

Also Published As

Publication number Publication date
JPS5987683A (ja) 1984-05-21

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