JPS615295A - Contrast signal generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an N-tone signal generation circuit in a liquid crystal television receiver.

[Prior art and its problems] In recent years, liquid crystal television receivers that use a liquid crystal display panel in the display section have been put into practical use as small portable television receivers. Furthermore, recently, liquid crystal color televisions using color liquid crystal panels have been considered. There are various methods for color liquid crystal display, but as shown in Figure 3, R
Generally, a color liquid crystal panel 2 is constructed by arranging primary color filters 1 of (red), G (green), and B (blue), and a color display is performed by a combination of the three primary colors. Further, in FIG. 3, 3 is a scanning electrode drive circuit, and n scanning signal lines are connected to the color liquid crystal panel 2. Furthermore, 4 is an R signal electrode drive circuit, 5 is a G signal electrode drive circuit, and 6 is a B signal electrode drive circuit, each of which has m signal lines connected to the color liquid crystal panel 2. Moreover, 7 is a liquid crystal voltage generation circuit, Va to v5, that is, Vn - GND
.

Vl = (1/a)Vlt, V2 = (2/a)
Vs, Vl-(1-2/a) Vi, V+=(1-1/a
) Vs, s are generated and supplied as operating voltages to each of the drive circuits 3.4.5.6. Note that a above is a bias ratio.

Each signal electrode drive circuit 4.5.6 in FIG. 3 above is as follows:
It is constructed as shown in FIG. That is, each signal electrode drive circuit 4.5.6 has m stages of drive circuits 101 to 10m.
It consists of The 4-bit digital data D1 to D4 sent from the video processing circuit (not shown) are first input to the register 11 in the first stage drive circuit 101. This register 11 has a sampling clock φ
The data D1 to D4 are read in synchronization with B, input to the latch circuit 12, and sent to the next stage drive circuit 102. The latch circuit 12 latches the data written in the register 11 in synchronization with the latch pulse φβ, and inverts the inverter 13 . .about.134 to OR circuits 141.about.144.degree. Moreover, in these OR circuits 141 to 144,
Output Q! of the externally provided 4-bit counter 15!
~Q4 is input. The counter 15 is reset by the latch pulse φβ and counts up by the clock pulse φC. And the above OR circuit 1
The outputs of 41 to 144 are input to the reset terminal R of the flip 70 knob 17 via the AND circuit 16. This flip 70 knob 17 is set by the latch pulse φ2, and its output is sent to the multiplexer 18. This multiplexer 18 is supplied with a frame switching signal φF and is supplied with a voltage V from the liquid crystal voltage generation circuit 7.
.

A liquid crystal driving voltage of ~vIi is applied. The multiplexer 18 outputs a signal electrode drive signal, that is, a grayscale signal Y1, in accordance with the output signal of the flip-flop 17. Further, the drive circuits 102 to 10m in the second and subsequent stages are configured similarly to the drive circuit 101, and the gray scale signals Y2 to 10m are configured similarly to the drive circuit 101.
'rI'L is output.

In the above configuration, the digital data D1 to D4 sent from the video processing circuit are first transmitted to the first stage drive circuit 10.
1 and read into the register 11 in synchronization with the sampling clock φB. The data Dl-04 read into this register 11 is then sequentially shifted to the registers 11 of the drive circuits 102 to 10TrL in synchronization with the sampling clock φB.

Then, when the data D1 to D4 are shifted to the register 11 of the drive circuit 10m, the latch pulse φ
β is given. As shown in FIG. 5, this latch pulse φβ is output once every m times the sampling clock φB is output, and the data held in the register 11 in each drive circuit 101 to 10m is latched into the latch circuit 12. be done. At the same time, the counter 15 is reset by the latch pulse φβ, and the flip 70 knob 17 is set as shown in FIG. By setting the flip-flop 11, the output Y1 of the multiplexer 18 rises from the reference level of V3 to the level of 5. In this case, in the next frame, when the flip-flop 17 is set, the multiplexer 1
The output Y1 of No.8 falls from the reference level of No.2 to ■0 level. After being reset by the latch pulse φC, the counter 15° starts counting by the clock pulse φC. As shown in FIG. 5, 14 clock pulses φC are generated for each latch pulse φ2. Then, the count output Qs of the counter 15
~Q4 is connected to the inverters 131 to 13 by the latch circuit 12.
4 and the OR circuits 141 to 14
4, and its output is input to the AND circuit 16.

Therefore, along with the counting operation of the counter 15, the OR circuit 14. ~When the outputs of 144 are all “1”, a.
The output of the hold circuit 16 becomes "1", and the flip-flop 17 is reset. The count value of the counter 15 at which the outputs of the OR circuits 141 to 144 become all "1" is determined by the latch data of the latch circuit 12, and is determined by the latch data of the latch circuit 12, and is determined by the latch data of the latch circuit 12. The time is controlled. When the flip-flop 17 is reset, the output of the multiplexer 18 returns to the reference level. Then, the above operation is repeated by applying the latch pulse φ2. A signal Y+ is output from the multiplexer 18 in accordance with the data held by the circuit 12, and each signal electrode in the color liquid crystal panel 2 is driven for display.

FIG. 6 shows an example of the waveform of the display drive signal, (a>
is the scan electrode drive signal X+ output from the scan mm drive circuit 3, and (b) is the gray scale signal Y+ output from the multiplexer 18 of the signal electrode drive circuit 10.

(C) is a composite waveform of the scanning electrode drive signal X1 and the N11 signal Y1.

As mentioned above, in the conventional signal electrode drive circuit 1o, a fixed output waveform is obtained depending on the input data.
, B differ from the designed value, the hue will differ. That is, the above filter has R, G, B
Since the filter is formed three times for each color, it is extremely difficult to form the filter uniformly, resulting in variations in the filter film thickness.

If there is a difference in filter film thickness, even if the same voltage is applied to the electrodes, there will be a difference in the effective value applied to the liquid crystal, resulting in deterioration of display quality.

[Object of the invention] The present invention has been made in view of the above points, and includes RlG, B
It is an object of the present invention to provide a gradation signal generation circuit that can correctly display a desired color and maintain good display quality even when the filter film thickness is different from a set value.

[Summary of the Invention] The present invention provides an adjustment section for the gradation waveform output from each color drive circuit in a color liquid crystal panel drive circuit, and adjusts the time lIIIM in this adjustment section to adjust the liquid crystal display panel. This allows the execution voltage applied to the device to be adjusted arbitrarily.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 20 is a signal electrode drive circuit, which is composed of m stages of drive circuits 201 to 20m. These drive circuits 2
01 to 20m differ from the drive circuits 101 to 10m in FIG. 4 only in the timing of the set signal of the flip 70 knob 17, and the rest is the same as the drive circuit 10. ~10
Since the configuration is similar to that of FIG. 4, the same reference numerals as those in FIG.

Thus, the flip-flop 70 tube 17 is given a set signal from the flip-flop 22 provided outside the signal electrode drive circuit 20. This flip-flop 22 is reset by the Q4 output of a 4-bit counter 23. This counter 23 is reset by a latch pulse φβ, and performs a door-turn operation by its own 04 output provided via an OR circuit 24 and a clock pulse φc2 shown in FIG. In addition, the Q4 output of the counter 23 is output from the flip 70 as described above.
The signal is input to the reset terminal R of the knob 22 and is also input to the reset terminal R of the counter 15 via the inverter 25.

This counter 15 receives a clock pulse φc shown in FIG.
Counts up by 1. Further, the outputs Q1 to Q3 of the counter 23 are input to OR circuits 26a to 26c. In the OR circuits 26a to 26c,
Initial setting data A1, A2, A3 are inverter 27a~
260. Above initial setting data AI
, A2, and A3 are correction data for correcting changes in hue due to errors in forming the filter film thickness. The outputs of the OR circuits 26a to 28c are input to the reset terminal R of the flip 70 knob 22 via the AND circuit 28.

Next, the operation of the above embodiment will be explained. The present invention is the second
As shown in the figure, each latch pulse φλ is divided into 17 equal parts,
A clock pulse φc1 is generated in each of the other 15 sections except for the first two sections. The first two intervals between two of each of the latch pulses are initial adjustment intervals, and the interval setting is performed by the 04 output of the counter 23. Therefore, although the counting clock pulse φC2 of the counter 23 is set to a frequency four times that of the clock pulse φc1 in this embodiment, its output is prohibited at the timing when the latch pulse φ2 is generated. Therefore, the digital data D1 to D4 sent from the video processing circuit are
First, the signal is input to the first-stage drive circuit 201 and read into the register 11 in synchronization with the sampling clock φ8. The data D1 to D4 read into this register 11 are then sent to the drive circuit 20 in synchronization with the sampling clock φB.
The data is sequentially shifted to registers 11 from 2 to 20m. The data D1 to D4 are stored in the register 1 on the drive circuit 20.
After being shifted to 1, the latch pulse φ2 is then applied. This latch pulse φ°C is output once every m sampling clocks φB, and the data held in the register 11 in each drive circuit 201 to 20m is latched into the latch circuit 12. At the same time, the counter 23 is reset by the latch pulse φ°C. When this counter 23 is reset, its Q4
The output becomes ``(Q$'), the output of the inverter 25 becomes 1'', and the counter 15 is reset. From this point on, the counter 15 is held in the reset state until the content of the counter 23 is counted up to ``8''. Thus, the counter 23 starts a count-up operation by the clock pulse φo2, and outputs the count outputs Q1 to Q3 to the OR circuits 26a to 26b. Setting data AI, A
2, A3 is inverted by inverters 27a to 270 and input. Therefore, after the counter 23 is reset, it is counted up by the low clock pulse φc2, and when the count value becomes equal to the initial setting data A1, A2, A3, the outputs of the OR circuits 26a to 26c are all "1".
", the AND circuit 28 outputs a "1" signal and the flip-flop 22 is set. As a result, the flip-flop 22 outputs the initial setting data A'i, A2 .
Figure 2 (e) according to the contents of A3 rooOJ to N11J
An output signal waveform as shown in ~l) is obtained. Now, if initial setting data A1, A2, and A3 are set to rlolJ, the setting data is
Inverted to roloJ data by 7C, OR circuit 2
The signals are input to the AND circuit 28 via 6a to 260. Therefore, when the counter 24 counts the clock pulse φc2 after being reset and counts up to "5", its outputs 01 to Q3 become "101", and the OR output with the initial setting data AI, A2, A3, that is, The outputs of the OR circuits 26a to 26c are all "1". Therefore, the output of the AND circuit 28 becomes ia I PI,
Set the flip-flop 22. Therefore, the output of the flip-flop 22 becomes "1", setting the flip-flop 17, and its output is sent to the multiplexer 18. As a result, the gradation signal Y1 is output from the multiplexer 18.
is output and the signal electrodes of the display panel are driven for display.

Thereafter, when the counter 23 counts up to 8, the output signal Q4 becomes "1" and the flip-flop 22 is reset. As mentioned above, the period after the counter 23 is reset by the latch pulse φ°C until the Q4 output signal is output is the initial adjustment period, and in this initial adjustment period, after the flip 7O knob 22 is reset. The period t1 until the flip-flop 22 is set and the period t2 until the flip-flop 22 is reset by the Q4 output of the counter 23 are the initial setting data A1, A2.
, A3. Therefore, when the 04 signal is output from the counter 23 as described above, the inverter 2
5 becomes 0", and the reset state of the counter 15 is released. Therefore, the counter 15 then starts counting operation by the clock pulse φo1. The Doma clock pulse φC is reset as shown in FIG. After release, 15 latch pulses φ°C are generated until the next latch pulse φ°C is output.Then, the count output of the counter 15 becomes 0.
1 to Q4 are connected to inverters 131 to 1 by the latch circuit 12.
34 as well as the OR circuits 141 to 141.
144, and its output is input to the AND circuit 16.

Therefore, when the outputs of the OR circuits 141 to 144 become all "*'1 t+" as the counter 15 counts, the output of the AND circuit 16 becomes 1", and the flip 70
The knob 11 is reset. The above OR circuits 141 to 14
The count value of the counter 15 at which the outputs of the flip-flops 11 and 4 are all "1" is determined by the latch data of the latch circuit 12, which controls the time from when the flip-flop 11 is set until it is reset. . For example, when data "8" is latched in the latch circuit 12, when the counter 15 counts eight clock pulses φC as shown in FIG.
*I II, and the flip-flop 11 is reset. By resetting the flip 70 knob 17, the output of the multiplexer 18 returns to the reference level. In this way, the set period tp and the reset period tR of the flip 70 block 11 are determined according to the data held in the latch circuit 12. Figure 2 (
h), (1), (j>, (k>) are flip-flops 1
7 output, initial setting data A1, A2,
When A3 is set to rl, 01J, rooolJ, rooolJ are input data D1 to D4.
, rllllJ, and rloooJ are given. In addition, FIG. 2 <X> to (n) show waveform examples of display drive signals, where (β) is the scan electrode drive signal X+ output from the scan electrode drive circuit, and (m) is the signal electrode drive signal. The grayscale signal Y+, (n) output from the multiplexer 18 of the drive circuit 20 is a composite waveform of the scanning electrode drive signal X1 and the grayscale signal Y1.

As mentioned above, the gradation signal Y1 can be adjusted to multiple levels at each gradation using the initial setting data AI, A2, and A3, for example, to 8 levels in the above embodiment, so even if the filter film thickness differs from the designed value, the initial Setting data AI
, A2, and A3, the hue can be set correctly.

In the above embodiment, the adjustment section is provided at the front stage of the gradation waveform, but it may be provided at the rear stage of the gradation waveform.

〔Effect of the invention〕

As described in detail above, according to the present invention, in the drive circuit of a color liquid crystal panel, an adjustment section is provided for the gradation waveform output from the drive circuit of each color, and the time width in this adjustment section is adjusted. Since the effective voltage applied to the liquid crystal display panel can be adjusted arbitrarily, the desired color can be displayed correctly even if the film thickness of the color liquid crystal panel RlG and B filters is different from the set value. It is possible to provide a gradation signal generation circuit that can display images and maintain good display quality.

[Brief explanation of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a circuit configuration diagram, FIG. 2 is a timing chart for explaining the operation, and FIG. 3 is a diagram of a conventional liquid crystal display device. 4 is a block diagram showing the configuration of the signal electrode drive circuit in FIG. 3; FIG. 5 is a timing chart for explaining the operation of the signal electrode drive circuit in FIG. 4;
FIG. 6 is a waveform diagram of a conventional display drive signal. 11...Register, 12...Latch circuit, 15...
・Counter, 17...Flip-flop, 18...
Multiplexer, 20... Signal electrode drive circuit, 24...
··counter. Applicant's agent Patent attorney Takehiko Suzue Figure 4 p.

Claims (1)

[Claims] In a signal electrode drive circuit for driving signal electrodes provided for each primary color on a color liquid crystal panel, a gradation signal creation means for creating a gradation signal according to display data, and each gradation created by this means are provided. A means for setting an adjustment section for a modulation signal, and an ON time and an O in this adjustment section.
A gradation signal generator comprising: initial setting data input means for specifying FF time; and means for setting ON time and OFF time in the adjustment section based on the initial setting data input by this means. circuit.