JPH0760300B2 - Gradation signal generation circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a gradation signal generating circuit for driving a liquid crystal panel in gradation.

[Prior Art] In recent years, a liquid crystal television receiver using a liquid crystal display panel in a display portion has been put into practical use as a portable small-sized television receiver. Further, recently, a liquid crystal color television using a color liquid crystal panel has been considered. There are various methods for color liquid crystal display, but as shown in FIG.
In general, a color liquid crystal panel 2 is configured by arranging primary color filters 1 of (red), G (green), and B (blue), and color display is performed by a combination of the above three primary colors. Further, in FIG. 3 described above, 3 is a scanning electrode drive circuit, and n scanning signal lines are connected to the color liquid crystal panel 2. Further, 4 is an R signal electrode drive circuit, 5 is a G signal electrode drive circuit, and 6 is a B signal electrode drive circuit, and m signal lines are connected to the color liquid crystal panel 2. Further, 7 is a liquid crystal voltage generating circuit, which is V _{0 to} V ₅ , that is, V ₀ = GND, V ₁ = (1 /
a) V ₅ , V ₂ = (2 / a) V ₅ , V ₃ = (1-2 / a) V ₅ , V ₄ = (1
-1 / a) V ₅ and ₅ are generated, and the above-mentioned drive circuits 3, 4, 5,
6 as the operating voltage. In addition, the above-mentioned a is a bias ratio.

Each of the signal electrode drive circuits 4, 5, 6 in FIG.
It is constructed as shown in FIG. That is, each signal electrode driving circuit 4, 5 and 6 is made from the drive circuit 10 ₁ through 10m of m stages. Then, the digital data D1~D4 of 4 bits sent from the image processing circuit (not shown) is first input to the register 11 of the first stage of the drive circuit 10 _1. The register 11 sends the data D1~D4 in synchronization with the sampling clock phi _S read, the next stage of the drive circuit 10 ₂ and inputs to the latch circuit 12. The latch circuit 12 is
The data written in the register 11 is latched in synchronization with the latch pulse φl, and the OR circuit is passed through the inverters 13 _{1 to} 13 _4.
Enter in 14 _{1 to} 14 ₄ . Moreover, this OR circuit 14 ₁ to 14 _4, the output to Q ₁ 4-bit counter 15 provided outside
~ Q ₄ is entered. The counter 15 has a latch pulse φ
It is reset by 1 and starts counting up by the clock pulse φ _C. Then, the OR circuit 14 ₁ to 1
The output of 4 ₄ is output to the flip-flop 17 via the AND circuit 16.
Is input to the reset terminal R of. This flip flop
17 is set by the latch pulse φl,
Its output is sent to the multiplexer 18. A frame switching signal φ _F is applied to the multiplexor 18, and liquid crystal drive voltages V _{0 to} V ₅ are applied from the liquid crystal voltage generating circuit 7. Then, the multiplexer 18 outputs the signal electrode drive signal, that is, the gradation signal Y ₁ according to the output signal of the flip-flop 17. The drive circuit 10 ₂ through 10m of the second and subsequent stages may be configured similarly to the drive circuit 10 _1, and outputs a tone signal Y ₂ ~m.

In the above configuration, the digital data D1~D4 transmitted from the video processing circuit is first input to the first stage of the driving circuit 10 _1, in synchronization with the sampling clock phi _S register
Read on 11. Data D ₁ read into this register 11
To D ₄ is then sequentially shifted in synchronization with the sampling clock phi _S to the register 11 of the drive circuit 10 ₂ through 10m. Then, when the data D1 to D4 are shifted to the register 11 of the drive circuit 10m, the latch pulse φ1 is applied thereafter. The latch pulse φl is fifth sampling clock phi _S as shown in FIG. Is outputted one shot each time the m onset output, data held in the register 11 in the drive circuits 10 ₁ through 10m latch circuit 12 Latched on. Also,
At the same time, the counter 15 is reset by the latch pulse φl, and as shown in FIG.
17 is set. By setting this flip-flop 17, the output Yi of the multiplexer 18 rises from the reference level of V _{3 to} the level of V ₅ . In this case, in the next frame, when flip-flop 17 is set, output Yi of multiplexer 18 falls from the reference level of V ₂ to V ₀ level. Then, the counter 15 is reset by the latch pulse φl and then starts the counting operation by the clock pulse φ _C. Clock pulse φ
_As shown in FIG. 5, _C is generated 14 times during each latch pulse φl. Then, the count output Q ₁ to
Q ₄ is input to the OR circuits 14 _{1 to} 14 ₄ together with the signal output from the latch circuit 12 via the inverters 13 _{1 to} 13 ₄ , and the output thereof is input to the AND circuit 16. Therefore, the counter 15
The output of the AND circuit 16 becomes "1" when the outputs of the OR circuits 14 _{1 to} 14 ₄ become all "1" in accordance with the counting operation of
The flip-flop 17 is reset. OR circuit 14 above
The count value of the counter 15 the output of the _{1-14 4} is all "1", intended to be determined by the latched data of the latch circuit 12, whereby the time until the flip-flop 17 is reset after being set Controlled. When the flip-flop 17 is reset, the multiplexer 18
Output returns to the reference level. Then, the latch pulse φl is applied thereafter, and the above-described operation is repeated. As described above, the signal Yi is output from the multiplexer 18 according to the data held in the latch circuit 12, and each signal electrode in the color liquid crystal panel 2 is driven for display.

FIG. 6 shows an example of the waveform of the display drive signal.
Is a scan electrode drive signal output from the scan electrode drive circuit 3.
Xi, (b) is a gradation signal Yi output from the multiplexer 18 of the signal electrode drive circuit 10, and (c) is a composite waveform of the scan electrode drive signal Xi and the gradation signal Yi.

[Problems to be Solved by the Invention] As described above, in the conventional signal electrode drive circuit 10, since the output waveform determined by the input data is obtained, R, G,
When the filter thickness of B is different from the designed value, the hue is different. That is, since the filter is formed by dividing into three colors for each of R, G, and B, it is extremely difficult to form it uniformly, and the filter film thickness varies. If there is a difference in the filter film thickness, a difference in the effective value applied to the liquid crystal even if the same voltage is applied to the electrodes causes a deterioration in display quality.

The present invention has been made in view of the above points, and R, G, B
It is an object of the present invention to provide a gradation signal generation circuit that can display a desired color correctly and can maintain good display quality even when the filter film thickness is formed different from the set value.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an ON in a gradation signal generation circuit for driving a liquid crystal panel with a plurality of gradations.
A gradation signal creating means for creating a gradation signal whose gradation is determined by the ratio of the period and the OFF period; and an adjustment period provided separately from the ON period and the OFF period, and an ON period within the adjustment period. And a setting means for setting the ratio of the OFF period.

[Operation] With this configuration, when the gradation signal whose gradation is determined by the ratio of the ON period and the OFF period according to the display data of each primary color is created, the ON period and the OFF period are Separate adjustment period is set, and ON period and OF within the adjustment period
By setting the ratio of the F period, the gradation expression can be finely adjusted, and can be used, for example, to adjust the color balance of each of the R, G, and B primary colors.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 20 is a signal electrode drive circuit, which is an m-stage drive circuit.
It consists of 20 ₁ to 20 m. These drive circuits 20 _{1 to} 20 m
Is only the timing of the set signal of the flip-flop 17 in the fourth diagram of a drive circuit 10 ₁ through 10m are different, and the other identical to Figure 4 have the same configuration as the fourth diagram of a drive circuit 10 ₁ through 10m Reference numerals are given and detailed description is omitted. Thus, the flip-flop 17 is provided with a set signal from the flip-flop 22 provided outside the signal electrode drive circuit 20. This flip-flop 22 is reset by the Q ₄ output of the 4-bit counter 23. The counter 23 is reset by the latch pulse φl, and counts up by its own Q ₄ output given through the OR circuit 24 and the clock pulse φ _C2 shown in FIG. The Q ₄ output of the counter 23 is input to the reset terminal R of the flip-flop 22 and the reset terminal R of the counter 15 via the inverter 25 as described above. The counter 15 counts up in response to the clock pulse φ _C1 shown in FIG. The outputs Q _{1 to} Q ₃ of the counter 23 are input to the OR circuits 26a to 26c. Then, the initial setting data A1, A2, A3 are input to the OR circuits 26a to 26c via the inverters 27a to 26c. The initial setting data A1, A2, A3 are correction data for correcting a change in hue due to a filter thickness formation error. The outputs of the OR circuits 26a to 26c are input to the reset terminal R of the flip-flop 22 via the AND circuit 28.

Next, the operation of the above embodiment will be described. The present invention is the second
As shown in the figure, each latch pulse φl is divided into 17 equal parts, and the clock pulse φ _C1 is generated in each of the other 15 sections except the first two sections. Each latch pulse φl
The first two sections in the interval are initial adjustment sections, and the section setting is performed by Q ₄ output of the counter 23. Therefore, although the counting clock pulse φ _C2 of the counter 23 is set to a frequency four times that of the clock pulse φ _C1 in this embodiment, the output is prohibited at the timing when the latch pulse φl is generated. Then, the digital data D1 to D4 sent from the video processing circuit are first input to the _first- stage drive circuit 201 and read into the register 11 in synchronization with the sampling clock φ _S. The data D _{1 to} D ₄ read in this register 11 are then collected by the sampling clock φ _S.
Are sequentially shifted to the registers 11 of the drive circuits 20 _{2 to} 20 m in synchronism with. When the data D1 to D4 are shifted to the register 11 of the drive circuit 20m, the latch pulse φ
l is given. The latch pulse φl is output once every m times the sampling clock φ _S is output, and the data held in the register 11 in each of the drive circuits 20 _{1 to} 20 m is latched by the latch circuit 12. At the same time, the counter 23 is reset by the latch pulse φl. When the counter 23 is reset, its Q ₄ output becomes “0”, the output of the inverter 25 becomes “1”, and the counter 15 is reset. Thereafter, the counter 15 is held in the reset state until the content of the counter 23 is counted up to "8". Then, the counter 23 starts the count-up operation by the clock pulse φ _{C2 and} outputs the count outputs Q _{1 to} Q ₃ to the OR circuits 26a to 26b. In addition, the OR circuits 26a to 26c have initial setting data A1, A
2, A3 is inverted and input by the inverters 27a to 27c. Therefore, after the counter 23 is reset, it counts up by the clock pulse φ _C2, and when the count value becomes equal to the initial setting data A1, A2, A3, the OR circuit
The outputs of 26a to 26c are all "1", the "1" signal is output from the AND circuit 28, and the flip-flop 22 is set. As a result, the flip-flop 22 obtains output signal waveforms as shown in FIGS. 2E to 2G according to the contents “000” to “111” of the initial setting data A1, A2, and A3.
Now, assuming that the initial setting data A1, A2, A3 is set to "101", the setting data is inverted to "010" data by the inverters 27a to 27c, and the AND circuit is performed via the OR circuits 26a to 26c. Entered in 28. Therefore, the counter
24 counts clock pulses φ _C2 after reset,
When it counts up to "5", the output Q ₁ to Q ₃ is "101", and the OR output of the initial setting data A1, A2, A3, i.e., the output of the OR circuit 26a~26c becomes all "1" . Therefore, the output of the AND circuit 28 becomes "1" and the flip-flop 22 is set. For this reason flip-flops
The output of 22 becomes "1" to set the flip-flop 17, and its output is sent to the multiplexer 18. As a result, the gradation signal Yi is output from the multiplexer 18 and the signal electrodes of the display panel are driven for display. Then, after that, when the counter 23 counts up to 8, the output signal Q ₄ becomes “1” and the flip-flop 22 is reset. As described above, the period from the resetting of the counter 23 by the latch pulse φl to the output of the Q ₄ output signal is the initial adjustment section, and is set after the flip-flop 22 is reset in this initial adjustment section. Period until
t ₁ and the period t ₂ after which the flip-flop 22 is reset by the Q ₄ output of the counter 23 is the initial setting data A
Set to 1, A2, A3. Thus, when Q ₄ signal is output from the counter 23 as described above, the output of the inverter 25 becomes "0", the reset state of the counter 15 is released. Therefore, the counter 15 thereafter starts the counting operation by the clock pulse φ _C1 . As shown in FIG. 2, the clock pulse φ _C is generated 15 times after the reset is released and before the next latch pulse φ 1 is output. Then, the count outputs Q _{1 to} Q ₄ of the counter 15 are input to the OR circuits 14 _{1 to} 14 ₄ together with the signal output from the latch circuit 12 via the inverters 13 _{1 to} 13 ₄ , and the outputs thereof are AND circuits. Input to 16. Accordingly, the output becomes "1" of the AND circuit 16, flip-flop 17 is reset when the output of the OR circuit 14 ₁ to 14 ₄ with the counting operation of the counter 15 becomes all "1". The counter value of the counter 15 in which the outputs of the OR circuits 14 _{1 to} 14 ₄ are all “1” is determined by the latch data of the latch circuit 12, and is reset after the flip-flop 17 is set by this. Until the time is controlled. For example, the latch circuit 12
If the data of "8" is latched in, the output of the AND circuit 16 becomes "1" and the flip-flop 17 is reset when the counter 15 counts eight clock pulses φ _C as shown in FIG. It When the flip-flop 17 is reset, the output of the multiplexer 18 returns to the reference level. In this way flip-flop 17
, The set period t _P and the reset period t _R are determined according to the data held in the latch circuit 12.
2 (h), (i), (j), and (k) show the output of the flip-flop 17, and the initial setting data A1, A
2, when A3 is set to “101”, input data D _{1 to} D ₄ are “0001”, “0001”, “1111”, “10”.
This is the case when "00" is given. Also, FIG. 2 (l)-
(N) shows an example of the waveform of the display drive signal,
(L) is a scan electrode drive signal Xi output from the scan electrode drive circuit, and (m) is a multiplexer of the signal electrode drive circuit 20.
The gradation signal Yi, (n) output from 18 is a composite waveform of the scan electrode drive signal Xi and the gradation signal Yi.

As described above, the gradation signal is set by the initial setting data A1, A2, A3.
Since Yi can be adjusted in multiple steps in each gradation, for example, in eight steps in the above embodiment, even if the filter film thickness is different from the design value, the hue can be correctly set by adjusting the initial setting data A1, A2, A3. can do.

In the above embodiment, the adjustment section is provided before the gradation waveform, but it may be provided after the gradation waveform.

[Effects of the Invention] As described above in detail, according to the gradation signal generating circuit of the present invention, when the gradation signal whose gradation is determined by the ratio of the ON period and the OFF period is created, The adjustment period is provided separately from the OFF period and the ON period, and the ON period and OFF period within the adjustment period
By setting the ratio of the period, it is possible to finely adjust the gradation expression, and for example, it can be used for adjusting the color balance of each of the R, G, and B primary colors.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a circuit configuration diagram, FIG. 2 is a timing chart for explaining the operation, and FIG. 3 is a conventional liquid crystal display device. FIG. 4 is a block diagram showing the configuration, FIG. 4 is a diagram showing the configuration of the signal electrode drive circuit in FIG. 3, and FIG. 5 is a timing chart for explaining the operation of the signal electrode drive circuit in FIG.
FIG. 6 is a waveform diagram of a conventional display drive signal. 11 …… Register, 12 …… Latch circuit, 15 …… Counter,
17 ... Flip-flop, 18 ... Multiplexer, 20 ...
… Signal electrode drive circuit, 24… Counter.

Claims (1)

[Claims] 1. A gradation signal generating circuit for driving a liquid crystal panel with a plurality of gradations, a gradation signal generating means for generating a gradation signal whose gradation is determined by a ratio of an ON period and an OFF period, A gradation signal generating circuit comprising: an adjusting period provided separately from the ON period and the OFF period, and setting means for setting a ratio of the ON period and the OFF period within the adjusting period.