JP2596369B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for a television receiver or the like using a panel display.

[0002]

2. Description of the Related Art In recent years, portable small television receivers using a liquid crystal display panel for a display section have been put to practical use. In this type of television receiver using a conventional liquid crystal display panel, a video signal amplified by a video amplifier circuit is converted into a digital signal by an A / D conversion circuit, and the display of the liquid crystal display panel is driven by the digital signal. ing. However, due to its characteristics, the liquid crystal display panel has a problem that the gradation range from the white level to the black level is narrow, and it is difficult to obtain an image with good contrast. In order to solve such a problem, conventionally, a signal level of a video signal is detected, and a reference voltage of an A / D conversion circuit is set in accordance therewith so as to obtain a good contrast. That is, the video signal does not always change from the white level to the black level, and it is not necessary to A / D convert the entire range of the video signal. The contrast can be improved by varying the conversion level.

[0003]

Recently, as means for controlling the above-mentioned A / D conversion circuit, among the signals digitized by the A / D conversion circuit, for example, all "1" for completely white,
The number of all “0” data corresponding to complete black is counted, and a voltage corresponding to the value is generated.
A method of feeding back as a reference voltage of a D conversion circuit has been considered. That is, the upper and lower reference voltages are set in the A / D conversion circuit, and when an input voltage is applied to the A / D conversion circuit, the level to which the upper and lower reference voltages are equally divided by 16 is determined. It is output as bit data.

However, according to the above-mentioned conventional method, the reference voltage level remains at 1 even when the input video signal changes abruptly.
Since there is only a level change (once every two fields), the response is delayed.

[0005] In particular, in a color liquid crystal television receiver, when only a specific color component changes rapidly, there is a problem that the ratio of the color components changes and the hue changes extremely.

The present invention has been made in view of the above circumstances, and automatically sets an A / D conversion level of a chrominance signal on the basis of the level of a luminance signal. An object of the present invention is to provide an A / D conversion apparatus that can set a D conversion level, does not change the ratio of color components even when only a specific color component changes rapidly, and does not change the hue extremely. .

[0007]

An A / D converter according to the present invention comprises: a white level signal in a luminance signal of a video signal;
Signal level detecting means for detecting and outputting a black level signal
And the white level signal output from the signal level detecting means.
Upper reference voltage setting that sets the upper reference voltage according to the amount of signal
Setting means and the black level output from the signal level detecting means.
Lower reference that sets the lower reference voltage according to the amount of bell signal
Set by the voltage setting means and the upper limit reference voltage setting means
The upper reference voltage and the lower reference voltage setting means.
A color signal A / D conversion circuit for A / D converting a color signal of a video signal based on a lower-limit reference voltage set in advance, wherein the digital signal A / D converted by the color signal A / D conversion circuit is provided. Is used as an A / D conversion output.

[0008]

When the luminance signal is inputted, the luminance signal A / D conversion circuit detects a level higher than the upper limit reference voltage VRH and a level lower than the lower limit reference voltage VRL, and performs sampling by a sampling clock to output. Then, based on the signal output from the luminance signal A / D conversion circuit, the color signal A
A / D conversion level of the / D conversion circuit is set. Color signal A
/ D conversion circuit, ie, red A / D conversion circuit, green A / D
The conversion circuit and the blue A / D conversion circuit perform A / D conversion of the color signals (red signal, green signal, and blue signal) in accordance with the set level, and output the signals to the liquid crystal display circuit.

As described above, the luminance signal of the video signal is A / D converted by the luminance signal A / D conversion circuit, and the A / D conversion level of the color signal A / D conversion circuit is set based on the output signal. Thus, even when only a specific color component changes abruptly, the ratio of the color components does not change, so that an extreme change in hue can be prevented.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, in order to facilitate understanding of the present invention, a case where the present invention is applied to a monochrome liquid crystal television receiver will be described.

FIG. 1 is an overall schematic configuration diagram. A video signal sent from a video amplification circuit (not shown) via a signal line DL is input to a video signal A / D conversion circuit 1 and to a reference level A / D conversion circuit 2. The reference level A / D conversion circuit 2 receives an upper limit reference voltage VRH and a lower limit reference voltage VRL set to predetermined values in advance from a control unit (not shown) and, for example, a sampling clock φs of 3.12 MHz. Is entered. The reference level A / D conversion circuit 2 compares the video signal with the upper reference voltage VRH and the lower reference voltage VRL. If the video signal is equal to or higher than the upper reference voltage VRH, it is determined that the video signal is at the white level and the sampling clock φs And outputs a white digital signal W synchronized with the lower limit reference voltage VRL.
If it is below, it is determined to be at the black level and a black digital signal B is output.

The reference level A / D conversion circuit 2
Is input to the pulse generation circuit 3, and the black level signal B is input to the pulse generation circuit 4. Further, clock pulses .phi.2, .about.CK1 (symbols indicate inverted signals), .about.CK2 are input to the pulse generating circuits 3, 4 from the control unit. The above clock pulse φ
2 are output about 50,000 in one field, the clock pulse ~ CK2 is output when the field changes, and the clock pulse ~ CK1 is output several H later (H is the horizontal period) than ~ CK2. The outputs of the pulse generation circuits 3 and 4 are sent to integration circuits 5 and 6, respectively. The integrating circuits 5 are supplied with operating voltages V1 and V2, and the integrating circuit 6 is supplied with operating voltages V1 'and V2'.

The integration circuit 5 integrates the voltages V1 and V2 according to the signal from the pulse generation circuit 3, outputs the integrated output to the video signal A / D conversion circuit 1 as the upper limit reference voltage VH, 6 integrates the voltages V1 'and V2' according to the signal from the pulse generation circuit 4 and outputs the integrated output to the video signal A / D conversion circuit 1 as a lower limit reference voltage VL. The video signal A / D conversion circuit 1 converts the video signal from the video amplification circuit into a 4-bit digital signal according to the upper reference voltage VH and the lower reference voltage VL given by the integration circuits 5 and 6, and converts the liquid crystal display panel. Output to the used liquid crystal display circuit (not shown).

Next, details of the reference level A / D conversion circuit 2, pulse generation circuit 3, and integration circuit 5 will be described with reference to FIG. The reference level A / D conversion circuit 2 includes an A / D conversion circuit 21 and a decoder 22.
1, an upper limit reference voltage VRH and a lower limit reference voltage VRL are input as well as a video signal from the video amplifier circuit. The A / D conversion circuit 21 converts a white level signal higher than the upper limit reference voltage VRH into a 4-bit digital signal (all "1"), and converts a black level signal lower than the lower limit reference voltage VRL into a 4-bit digital signal. (All "0") and output. The output signal of the A / D conversion circuit 21 is decoded by the decoder 22 in synchronization with the sampling clock φs, and is output as a white level signal W and a black level signal B. Then, the white level signal W is sent to the pulse generation circuit 3 and the black level signal B is output to the pulse generation circuit 4.
Sent to

The pulse generating circuit 3 includes an AND circuit 3
1, for example, includes a counter 32 of 4096 base, a data latch circuit 33, a D / D converter 34, and a latch circuit 35, and a white level signal W from the reference level A / D conversion circuit 2
Is input to the clock terminal of the counter 32 via the AND circuit 31. The AND output of the latch circuit 35 is input to the AND circuit 31. This latch circuit 3
5 is latched by the clock pulse to CK1 and reset by the carry signal of the counter 32. Also,
The above-mentioned clock pulse ~ CK1 is input to the reset terminal ~ R of the counter 32. The count output of the counter 32 is latched by the data latch circuit 33 in synchronization with the clock pulse to CK2.
Sent to 4. The D / D converter 34 converts the latch data of the data latch circuit 33 from a clock pulse to CK2.
, And outputs the converted output to the integration circuit 5.

The integrating circuit 5 includes a time constant circuit 51 including an integrating resistor R and an integrating capacitor C.
1 includes a gate circuit 52 for controlling the supply of the operating voltage V1 and a gate circuit 53 for controlling the supply of the operating voltage V2. The output signal of the D / D converter 34 is directly input to the gate terminal of the gate circuit 53, and the inverter The signal is input to the gate terminal of the gate circuit 52 via 54. The time constant circuit 51 has a time constant set to about 2 ms, and outputs the video signal A / D as the upper-limit reference voltage VH.
Sent to conversion circuit 1. On the other hand, the pulse generation circuit 4 and the integration circuit 6 for processing the black level signal are configured in the same manner as the pulse generation circuit 3 and the integration circuit 5, and the details are omitted.

Next, the operation of the above embodiment will be described with reference to the timing charts of FIGS. In this embodiment, the number of dots of the liquid crystal display panel is set to “120 × 160”.
= 19200 ”, and the ideal numbers of perfect white and perfect black are each“ 2300 ”. When the video signal shown in FIG. 3 is sent from the video amplification circuit to the reference level A / D conversion circuit 2, the reference level A / D conversion circuit 2 converts the video input signal into the upper reference voltage VRH and the lower reference voltage VRH. Compared to the voltage VRL, a 4-bit digital signal of all "1" for a white level signal equal to or higher than the upper limit reference voltage VRH and an all "0" for a black level signal equal to or lower than the lower limit reference voltage VRL is A. Output from the / D conversion circuit 21. And this A /
The digital signals of the white level and the black level output from the D conversion circuit 21 are decoded by the decoder 22 and output as the white level signal W and the black level signal B as shown in FIG. Then, the white level signal W output from the decoder 22 is sent to the pulse creation circuit 3, and the black level signal B is sent to the pulse creation circuit 4.

The pulse generation circuit 3 generates clock pulses ~ C
The counter 32 is reset in synchronization with K1 and
The clock pulse ~ CK1 is latched by the latch circuit 35. When the clock pulse ~ CK1 is latched by the latch circuit 35, its output becomes "1" and the AND circuit 3
Gate 1 is opened. As a result, the white level signal W output from the decoder 22 is sent to the counter 32 via the AND circuit 31, and the counter 32 starts counting up.

The counter 32 counts the white level signal W sent from the decoder 22 for one field, and the content of the count is synchronized with the clock pulse to CK2 when the next field is reached. The signal is latched by the circuit 33 and sent to the D / D converter 34. In this case, when a signal of “4096” or more is sent from the decoder 22 to the counter 32 in one field, the carry signal is output from the counter 32 and the latch circuit 35 is reset. Thereby, the AND circuit 31
Is closed, and further input is prohibited.

The D / D converter 34 performs the D / D conversion operation shown in FIG. 4 according to the contents of the data latch circuit 33. FIG. 4 shows the operation of the D / D converter 34 when, for example, the count value “1000” is latched by the data latch circuit 33 from the counter 32.
The D / D converter 34 is reset by a clock pulse .phi.2 when a field changes. Each field is equally divided into 13 blocks from a first block to a thirteenth block. It is obtained by counting 4096 φ2.

The first to thirteenth blocks are each equally divided into 16 blocks from the first small block to the sixteenth small block, and each small block corresponds to 256 clock pulses φ2. And D /
In the first to sixteenth small blocks, the D converter 34 outputs a pulse signal having a time width corresponding to the latch data of the data latch circuit 33. For example, when the count value “1000” is latched in the data latch circuit 33 as described above, the pulse signals having a time width of 63 clock pulses φ2 for the first to eighth small blocks, Clock pulse φ26 up to 16 small blocks
A pulse signal with a time width of two shots is output. That is, the count value “1000” is averaged and divided in the first to sixteenth small blocks. Then, the signals of the first to sixteenth small blocks are sent to the integrating circuit 5 as the output of the D / D converter 34.

The integrating circuit 5 includes a D / D converter 34
In the first to sixteenth sub-blocks, the gate of the gate circuit 53 opens to output the voltage V2 to the time constant circuit 51 while the high-level signal is being supplied, and to the inverter 54 while the low-level signal is being supplied. The gate of the gate circuit 52 is opened by the output of the clock signal V1 and the voltage V1 is
Output to The time constant circuit 51 integrates the voltages V2 and V1 applied to the input point a through the gate circuit 53 or the gate circuit 52, and uses the integrated voltage as an upper limit reference voltage VH to produce a video signal A / D converter circuit 1. Give to.
The voltage V1 is the lower limit value of the video signal with respect to the white signal,
Voltage V2 is the upper limit.

When the latch data of the data latch circuit 33 in the pulse generation circuit 3 is "0",
The output of the D / D converter 34 is always at a low level, so that the output of the gate circuit 52 becomes "1", the gate of the gate circuit 52 opens, and the voltage V1 is output as the upper limit reference voltage VH. If the latch data of the data latch circuit 33 is "4096", the output of the D / D converter 34 is at a high level, so that the gate of the gate circuit 53 is opened and the voltage V2 becomes higher than the upper limit reference voltage V2.
Output as H. Therefore, every time the latch data of the data latch circuit 33 decreases by "1", the output of the integration circuit 5 decreases by "| V2-V1 | / 4096". When the latch data of the data latch circuit 33 is "2300", the upper limit reference voltage VH output from the integration circuit 5 is equal to the voltage V1
And V2.

On the other hand, in the pulse generating circuit 4 and the integrating circuit 6 for processing the black level signal B output from the reference level A / D conversion circuit 2, the same processing as that for the white level signal W is performed. The lower limit reference voltage VL is output from the integration circuit 6 and sent to the video signal A / D conversion circuit 1.

The video signal A / D conversion circuit 1 converts the video signal sent from the video amplification circuit into a 4-bit digital signal 200 times within 1H according to the upper limit reference voltage VH and the lower limit reference voltage VL. D-converted and output to liquid crystal display circuit.

However, when a video signal for a general screen is output from the video amplifier circuit, the screen looks most beautiful because the reference level A / D conversion circuit 2 outputs one.
This is when the white level signal W and the black level signal B output between fields, that is, the numbers of all “1” and all “0” are each about “2300”. Then, based on the white level signal W and the black level signal B output from the reference level A / D conversion circuit 2, the pulse generation circuit 3 and the pulse generation circuit 4 generate pulse signals as described above,
An upper reference voltage VH and a lower reference voltage VL are created from the integration circuits 5 and 6 according to the pulse signals, and sent to the video signal A / D conversion circuit 1. The video signal A / D conversion circuit 1 includes the upper reference voltage VH and the lower reference voltage VL.
A / D conversion processing is performed according to the above. In the case of a basic screen as described above, each circuit is adjusted such that the white and black signals are substantially "2300" for one screen.

Next, assuming that a sufficiently white screen is input as an input video signal and the number of all “1” s output from the reference level A / D conversion circuit 2 becomes “2300 + n”, the D The signal time width in the first to sixteenth small blocks output from the / D converter 34 is increased, and the upper limit reference voltage V output from the integration circuit 5 is increased.
H rises by “(| V1−V2 | / 4096) · n” (V). When the upper limit reference voltage VH rises, all "1" s output from the video signal A / D conversion circuit 1 are output.
That is, the number of white level signals W is sufficiently close to "2300", and a beautiful screen is obtained. The same processing is performed on the black level signal B by the pulse generation circuit 4 and the integration circuit 6.

However, when the liquid crystal display panel is used as described above, it can be confirmed by an experiment that the most beautiful image appears at about 10% to 15% on the completely white and completely black data screens. Was. Therefore, the number of perfect white and perfect black that looks the most beautiful is calculated from the total number of dots and is set to X.
X + a ”is beautiful. Assuming that the number of dots of the liquid crystal display panel is “120 × 160 = 19200”, the data of perfect white and perfect black is 12%, and the value of a is 3%,

(Equation 1) And the completely white and completely black data are “2300-600”.
If it is in the range of “2300 + 600”, the screen looks beautiful. Accordingly, the upper limit reference voltage VH and the lower limit reference voltage VL of the video signal A / D conversion circuit 1 are changed according to the video signal, and the number of complete whites and perfect blacks on the screen is brought close to the value of X, so that a beautiful picture is always obtained. Can be obtained.

Next, an example in which the present invention is applied to a color liquid crystal television receiver will be described with reference to FIG. In FIG. 5, reference numeral 2a denotes a luminance signal A / D conversion circuit to which a luminance signal Y is input from a video signal processing circuit (not shown). Also,
The upper limit reference voltage VRH and the lower limit reference voltage VRL preset to predetermined values from the control unit are input to the luminance signal A / D conversion circuit 2a, and the sampling clock φs is input thereto. The luminance signal A / D conversion circuit 2a detects the level of the luminance signal Y that is equal to or higher than the upper reference voltage VRH and the level that is equal to or lower than the lower reference voltage VRL, and samples the signal in synchronization with the sampling clock φs. 'And B' to the pulse generating circuits 3 and 4.

The pulse generation circuits 3 and 4 generate the luminance signal A / D
In accordance with the level signals W 'and B' from the conversion circuit 2a, a pulse is generated in the same manner as in the above embodiment, and is output to the integration circuits 5 and 6. The integrating circuits 5 and 6 perform an integrating operation in accordance with the pulse signals from the pulse generating circuits 3 and 4, and input the integrated outputs to the level shifters 7a, 7b and 7c. These level shifters 7a, 7b and 7c shift the levels of the output signals of the integration circuits 5 and 6 in accordance with a preset value, and provide a red A / D conversion circuit 1a, a green A / D conversion circuit 1b and a blue A / D conversion. The upper limit reference voltage VH and the lower limit reference voltage VL are input to the circuit 1c. Also,
The red A / D conversion circuit 1a and the green A / D conversion circuit 1
b, a red signal R, a green signal G, and a blue signal B are input from a color signal processing circuit (not shown) to the blue A / D conversion circuit 1c.

The A / D conversion circuits 1a, 1b,
1c is a color signal R, G, B according to the upper reference voltage VH and the lower reference voltage VL from the level shifters 7a, 7b, 7c.
Is A / D converted and output to a liquid crystal display circuit. When the present invention is applied to the color liquid crystal television receiver, the processing for the upper reference voltage VH and the lower reference voltage VL is performed for the R, G, B color signals in the same manner as in the monochrome television receiver.

As described above, the luminance signal Y of the video signal is A / D converted by the luminance signal A / D conversion circuit 2a to output level signals W 'and B'. A / D conversion of the color signal A / D conversion circuits 1a, 1b, 1c
By setting the conversion level, even when only a specific color component changes abruptly, the ratio of the color components does not change, and it is possible to reliably prevent an extreme change in hue.

[0033]

As described above in detail, according to the present invention,
Even when the color video signal is A / D converted, the A / D conversion level of the color signal is set based on the luminance signal. There is an effect that the color does not change and the hue does not change extremely.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall schematic configuration when the present invention is applied to a monochrome liquid crystal television receiver.

FIG. 2 is a circuit diagram showing details of a main part in the embodiment.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing a circuit configuration example when the present invention is applied to a color liquid crystal television receiver.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Video signal A / D conversion circuit, 1a ... Red A / D conversion circuit, 1b ... Green A / D conversion circuit, 1c ... Blue A / D conversion circuit, 2 ... Reference level A / D conversion circuit, 2a ... Brightness Signal A / D conversion circuit, 3 ... pulse creation circuit, 4 ... pulse creation circuit, 5 ... integration circuit, 6 ... integration circuit, 7a-7c ... level shifter, 21 ... A / D conversion circuit, 22 ... decoder, 3
2: Counter, 33: Data latch circuit, 34: D / D
Converter, 35: latch circuit, 51: time constant circuit, 5
2 ... gate circuit, 53 ... gate circuit.

Claims (1)

(57) [Claims] 1. A luminance signal of a video signal.White level signal in Japan
Signal level detection that detects and outputs the signal and black level signal
Means, Of the white level signal output from the signal level detecting means.
Upper limit reference voltage setting procedure to set the upper limit reference voltage according to the amount
Steps and Of the black level signal output from the signal level detecting means.
Lower reference voltage setting procedure to set the lower reference voltage according to the amount
Steps and The upper limit reference voltage set by the upper limit reference voltage setting means.
And the lower limit set by the lower reference voltage setting means.
Based on the reference voltage A / D conversion of color signal of video signal
A color signal A / D conversion circuit, wherein the digital signal A / D converted by the color signal A / D conversion circuit is provided.
A digital signal as an A / D conversion output.
A / D converter.