JP2811195B2 - Display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT display device for displaying, for example, a pixel data signal converted into an analog signal on a CRT, and more particularly to control of the pixel data signal.

[Prior Art] FIG. 4 is a circuit diagram of a conventional CRT display device, and FIG.
It is a timing chart figure shown based on a figure. In the figure, (1) is a D-FF having D and C input terminals on the input side and a Q output terminal on the output side, and the dot serial (D) shown in FIG. (Not shown), the converted pixel data input signal (PD) is input,
The pixel clock signal (P shown in FIG.
C) is input, the pixel data input signal (PD)
Is synchronized with the pixel clock signal (PC) (C)
Is obtained and output from the output terminal Q. This pixel data signal (Q)
Is a waveform delayed in time with respect to the pixel clock signal (PC).

The pixel clock signal (PC) input to the D-FF (1) is also input to an AND gate (2) and a D / A converter (3).

The AND gate (2) receives the pixel data signal (Q) and the pixel clock signal (PC) from the D-FF (1), and outputs both the pixel data signal (Q) and the pixel clock signal (PC). At the time of "H", a pixel data output signal (GD) as shown in (d) is output.

The D / A converter (3) converts the pixel data output signal (GO) from the AND gate, the pixel clock signal (PC), and the synchronization signal (CS) into an analog signal (CV). (4) is a CRT for displaying an analog signal (CV) as an image.

Next, the operation of the conventional CRT display device will be described with reference to FIGS. When the pixel data input signal (PD) shown in FIG. 5B is input to D-FF (1), D-FF
According to (1), a pixel data signal (Q) as shown in (c) is obtained synchronized with the pixel clock signal (PC). At this time, the pixel data signal (Q) is output to the AND gate (2) as a signal delayed with respect to the pixel clock signal (PC). The pixel data signal (Q) input to the AND gate (2) is based on the pixel clock signal (P) input to the AND gate (2).
C) is gated to obtain a pixel data output signal (GO) as shown in (d), which is output to the D / A converter (3). The pixel data output signal (GO) input to the D / A converter (3) is converted into an analog amount together with a pixel clock signal (PC) and a synchronizing signal, and an analog signal (CV) as shown in (e) is obtained. Output to CRT (4).

[Problem to be Solved by the Invention] In the conventional CRT display device as described above, the pixel data output signal (GO) input to the D / A converter (3) is
This signal is synchronized with the pixel clock signal (PC) by D-FF (1), and has a delayed waveform. Therefore, the conversion of the pixel data output signal (GO) to the D / A converter (3) is delayed, and the signal output to the CRT (4) has the waveform shown in FIG. There is a problem that the size of the pixel becomes small.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a CRT display device in which a pixel data signal synchronized with a pixel clock signal is not delayed in a D / A converter.

[Means for Solving the Problems] A CRT display device according to the present invention provides a pixel data output signal obtained by being synchronized with a pixel clock signal by D-FF and being gated with the pixel clock signal by an AND gate. In a CRT display device which converts an analog signal by a D / A converter and displays the analog signal on a CRT, the H or L level of the pixel data output signal obtained by the AND gate is changed to the nth H or L of the pixel clock signal. And a delay line for outputting a pixel data delay signal to the D / A converter after delaying the signal to a level.

[Operation] In the present invention, D / A is performed by delaying the H or L level of the pixel data output signal delayed by the synchronization of the pixel clock signal to the nth H or L level of the pixel clock signal by the delay line. The pixel data delay signal is output to the converter.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart based on FIG. 1, and FIG. 3 is a specific example of the D / A converter shown in FIG. It is a block diagram showing an example. (1) is a D-FF, (2) an AND gate, and (5) is a delay line. When a gated pixel data output signal (GO) is input to the AND gate (2), the signal (G) is output.
A pixel data delay signal (DO) is output to the D / A converter (3) with a time delay of O).

The D / A converter (3) is a register (3a) and a D / A converter (3b)
The pixel data delay signal (DO) from the delay line (5) is input to the S terminal of the register (3a), the pixel clock signal (PC) is input to the C terminal, and the R terminal is synchronized. A signal (CS) is input, and a digital signal fixed to the “L” level is input to all n-bit digital input terminals. The n-bit output terminal of the register (3a) is connected to the input terminal of the D / A converter (3b). (4) is a CRT.

In the CRT display device configured as described above, the pixel data input signal (PD) shown in FIG.
When the pixel clock signal (PC) shown in (a) is input to the D-FF (1) while being input to the FF (1), the pixel data input signal (PD) becomes the pixel clock signal (PC). ) To obtain pixel data (Q) as shown in (c), and the signal (Q) is input to the AND gate (2). The pixel data signal (Q) input to the AND gate (2) is gated with the pixel clock signal (PC), and the pixel data output signal (GO) as shown in (d) is input to the delay line (5). You. The delay line (5) to which the pixel data output signal (GO) is input is a position (PC) at which "H" of this signal (G0) rises to "H" of the next pixel clock signal (PC).
Delay to 1) and register (3a) of D / A converter (3)
Outputs a pixel data delay signal (DO). The pixel data delay signal (DO) input to the register (3a) is
Since the pixel clock signal (PC) is at "H" at the position (PC1) where it rises to "H", n fixed at "L" level
The digital input of the bit is not latched in the register (3a), the signal of “H” is output to the D / A converter (3b), and the position (PC) where the next pixel clock signal (PC) rises
It is held until 2). Since the pixel data delay signal (DO) is "L" at this position (PC2),
The n-bit digital input fixed to the “L” level is latched in the register (3a), and the signal output to the D / A converter (3b) becomes “L”, as shown in FIG. An analog signal (CV) is output to CRT (4). This signal (C
“H” of V) is displayed as white on the CRT (4), and “L” is displayed as black.

In the above embodiment, n input to the register (3a)
Although all the digital inputs of bits have been fixed at the “L” level, the image data is also used as an n-bit digital input of the register (3a) to superimpose characters, graphics, etc. The same can be said for the pixel data as the matching information data.

[Effects of the Invention] As described above, according to the present invention, the pixel data output signal converted by the D / A converter is delayed at an appropriate time by the delay line. The effect is obtained that the display pixel width is sharpened without narrowing, and that the displayed data becomes clear even when the image is transferred to a film or the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a timing chart, FIG. 3 is a block diagram showing a configuration of a D / A converter, and FIG. 4 is a circuit of a conventional CRT display device. FIG. 5 is a timing chart. In the figure, (1) is a D-FF, (2) is an AND gate,
(3) is a D / A converter, (3a) is a register, (3b) is a D / A converter, (4) is a CRT, and (5) is a delay line.

Claims (1)

(57) [Claims] A D-type flip-flop to which a first image signal and a clock signal are input; an AND element to which the clock signal and an output signal from the D-type flip-flop are input; And a register to which an output from the delay element is inputted to a set terminal, a second image signal is inputted to an input terminal, and the clock signal is inputted to a clock terminal. A display device comprising: a D / A conversion unit that performs D / A conversion of an output of the D / A converter; and a display that displays an image based on a signal output from the D / A conversion unit.