JPS62209488A - Sampling of analog data - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention is a matrix display device that samples analog data and displays gradation. To substantially reduce the frequency of a clock and enable display within the operating limits of a shift register even when the display capacity is large.

[Industrial application field]

The present invention relates to a sampling method for analog data when sampling analog data and supplying and displaying it to a 71-RIS display device, and particularly relates to a sampling method that allows sampling to be performed at a low clock frequency. It is.

Matrix display device that performs gradation display-b Like other display devices, a large display capacity 61 is required, but even if the display capacity is large, there is a method that samples data with a relatively low frequency clock. Needed.

[Conventional technology]

For example, the "Nikkei Elec i-2s J 1
984.9-10. There are methods such as those described in P., 234-235, but a conventional non-pulling method for analog data will be described below.

FIG. 6 is an explanatory diagram of a conventional sampling method, and FIG. 7 is an explanatory diagram of the sampling method. The display data (analog data) of the video signal input to the terminal 1 and the data sampling clock input to the terminal 2 are supplied to the data side drive circuit 3. Here, since the display data (analog data) shown in FIG. 7 is input sequentially for each line of the matrix display panel 4 from 71 to 71, the number of pixels in the horizontal direction of the matrix display panel 4 is (■ in Figure 6.

■, ..., @ indicates the time ts divided by 1), which is 1
One pixel is numbered.

Similarly, as shown in FIG. 7, one line of analog data is taken into the data side drive circuit 3 by numbering from the second pixel to the nth pixel.
displayed at each predetermined position on the risk display panel 4. In this case, the shift register in the data side drive circuit 3 determines which pixel data is to be fetched, and the timing thereof is determined by the frequency of the data sampling clock.

[Problem that the invention seeks to solve]

In the conventional method, the surface area 11 is small, and the number of pixels in the horizontal direction n
There is no particular problem if n is small, but if n is large, (horizontal) x (
For example, if the number of pixels (vertical) is about 300×200 pixels, the frequency of the data sampling clock must be increased to 4MH7 or more, and the operating frequency of the shift 1 to registers exceeds 4M1−IZP2 degrees.

Therefore, in a display device that performs binary display, two data-side drive circuits are provided above and below the matrix display panel, and serially incoming digital data is alternately latched and divided into two systems, upper and lower. In this way, even a large display capacity can be handled with a relatively simple configuration.

However, when trying to apply this to a display device that displays analog data in gradations, in addition to providing two data-side drive circuits above and below a 7-trix display panel, two correspondingly
It is necessary to newly provide a sample bold circuit for each system, sample and hold incoming analog data corresponding to the two systems, and supply data to the upper and lower systems in a time-sharing manner. Therefore, such a display device requires two systems of sample and hold circuits, resulting in a large circuit.

In addition, in a display device that has two data-side drive circuits, analog data corresponding to the R (red) signal, G (green) signal, and [3 (blue) signal of the video signal is colored as shown in FIG. When displaying corresponding to each pixel of R2O and B in the horizontal direction of the display panel, if the same timing is numbered according to two systems of -b sampling clocks, as shown in Fig. 8, the result is as follows. At the quantity numbering timing, only one of R, G, and B is always not recombined for a period of one cycle of the data sampling clock, which causes a problem that smooth color display cannot be performed.

[Means for solving problems]

FIG. 1 shows a block diagram of an embodiment of the analog data sampling method according to the present invention. In the figure, 5 is an input terminal for the data sampling clock (a), 6 is an input terminal for the data sampling clock (b), 7 is a display data input terminal, and 8 is a data side drive supplied with the data sampling clock (a). 9 is a data side drive circuit supplied with a data sampling clock (b), and 10 is a matrix display panel.

(effect) One line of pixels ■ on the matrix display panel 10.

Two systems of data-side drive circuits 8° and 9 are provided that sample data using data sampling clocks (a) and (b) that are shifted by 1/2 period relative to ■, ■, ..., ■. Therefore, it is possible to correspond to a frequency substantially twice that of each other within the operating limits of the shift register, and even if the display capacity is large, it is possible to display within the operating limits of the shift register.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention.

In the figure, terminal 5 is the terminal to which the data sampling clock (a) is input as shown in FIG.
) is the input terminal for the data sampling block (b). Data sampling clock (a), (b)
) is Fig. 2 (Δ).

As is clear from (B), they are shifted from each other by 1 or 2 cycles in the time axis direction.

Terminal 7 is a display data input terminal. 8 is a data side drive circuit corresponding to the data sampling circuit (a); 9
is a data side drive circuit corresponding to the data sampling clock (b). Here, the data side drive circuit 8 corresponds to the pixels ■, ■, ■, etc. of the matrix display panel 10, respectively, and the data side drive circuit 9 corresponds to the pixels ■, ■, ■, . . , each corresponds to [stock]. In other words, the data side drive circuits 8.9 are alternately connected to pixels for one line.

In FIG. 1, the display data of the video signal shown in FIG. A) is supplied to the data side drive circuit 8, and the data sampling clock input to the terminal 6 (b) is supplied to the data side drive circuit 9, respectively.

In the data side drive circuit 8, display data is transmitted at timing a1.J: shown in FIG. a3,... is numbered,
On the other hand, in the data side drive circuit 9, the display data is sampled by the data sampling clock (b) at timing b2゜ba, . . . as shown in FIG. Depending on the output signal, the pixels of the matrix display panel 10 ■, ■, ■,...
is displayed, while pixels ■, ■, ■, .
, @ are displayed.

In this case, two systems sample data using data sampling clocks (a) and (b) that are shifted by 1!2 cycles from each other for pixels ■, ■, ■, ..., @ of one line of the matrix display panel 10. Since the data side drive circuit 8.9 is provided, it is possible to support frequencies up to substantially twice that frequency within the operating limits of the shift register, and even without using a lean pull hold circuit, the number of pixels can be increased more than the number of pixels explained in Fig. 6. The number can be displayed within the operating limits of the shift register.

FIG. 4 shows a block diagram of another embodiment of the present invention, in which the same components as those in FIG. 1 are given the same numbers and their explanations will be omitted. The difference from the one shown in FIG. 1 is that the pixels of the color display panel 11 are color pixels like R2O and B, and the display data input to the terminals 12R212c and 12e are also R and G.

This point is the display data of each color video signal of B.

As shown in FIG. 5, in the data side drive circuit 13, R
The display data of is sampled by the data sampling clock (a) and displayed on pixel ■, the display data of G is sampled by the data sampling clock (b) and displayed on pixel ■, and the display data of B is sampled by the data sampling clock (b) and displayed on pixel ■. is numbered as J to the data sampling clock (a) and displayed at pixel ■. In this case too, Uini 17
Because data sampling (a>, (b)) with a two-cycle shift is used, the 11 periods that are not rippled are only 1!2 cycles of the data ring ring clock, and the shift is also only 1!2 cycles. Therefore, color display is smoother than the conventional one shown in FIG. 8.

Note that the data side drive circuit is not limited to two systems as in each of the above embodiments, but may be set to three or more N systems. In this case, a data sampling clock with a period shift of 360°/N is used.

〔Effect of the invention〕

According to the present invention, even without using a sample and hold circuit as in the past, a larger number of pixels can be shifted than the conventional one.
display within the operating limits of the register17, thereby making the circuit smaller than conventional ones, or, when applied to a color display device, providing a smoother color display than conventional ones. Do (qru)

[Brief explanation of drawings]

Figure 1 is a block diagram explaining one embodiment of the present invention, Figure 2 is a data limp ring clock timing diagram, Figure 3 is a sampling timing diagram explaining how data is sampled, Figures 4 and 5. 6 and 7 are block diagrams and sampling timing diagrams for explaining other embodiments of the present invention, respectively. FIGS. 6 and 7 are diagrams for explaining the conventional method and sampling thereof, respectively. FIG. 8 is a sampling timing diagram for the conventional method. , is. In Figures 1 and 4, 5.6 is a data sampling clock input terminal, 7.12n, 12G, 12e are display data input terminals, 8.9, 13.14 are data side drive circuits, and 10 is a matrix display panel. , 11 is a color display panel. Book, starting point /) Voice i 1 j 2 111 Tips 1 Tips 7 Electric diagram 3 UIA Figure 4 Figure G

Claims (1)

[Scope of Claims] An analog data sampling method for a matrix display device in which analog data is sampled using a data sampling clock and supplied to a matrix display panel (10) for display, comprising: N (N is plural) systems of data-side drive circuits (8) and (9) are provided alternately for pixels, and the N systems of data-side drive circuits (8) and (9) have a 360° angle.
/N period shifted data sampling clock (a),
A method for sampling analog data, characterized in that the analog data is sampled by supplying each of the components (b) and (b) respectively.