JPS5917587A - Control system of crt display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control system for a CRT display device that performs all functions such as graphic display.

Conventionally, the refresh memory for the CR7 display in this type of device was constructed using memory elements with a capacity that matched the target number of pixels, so as pixels became finer, memory elements with a correspondingly larger capacity were required. There was a drawback.

As an example, 25 of 512 dots x 400 lines
204.80 for a 6-color graphic CRT display device
A capacity of 0 bytes is required, and if it is set to 1024 dots, a capacity of 409,600 bytes is required.

Furthermore, since CRT display tubes and video amplifiers have limited frequency characteristics, in order to achieve high-definition display, screen brightness, focus, and display position accuracy must be increased, which is extremely difficult compared to normal display devices. It had the disadvantage of being expensive.

The present invention has been made in view of the above points, and it is necessary to provide display start position information for subdividing pixels in the pixel data to be displayed.
To provide a control method for a CRT display device, which can use a video amplifier and a video amplifier, and can display with double or quadruple or more high definition and the same performance with only a slight increase in memory capacity and a slight increase in software burden. The target is □.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an example of a diagonal line graphic display according to the conventional method. Figures 2 to 6 are examples of the present invention, and Figure 2 shows an example of a display using the same number of pixels as Figure 1, which is a conventional method. Figure 3 is a pixel display position comparison diagram. □ and 1 are standard Display position, 2~
4 is a display position shifted by 1/4, Figure 4 is a display screen diagram, 5 is a 512-dot pixel, and 6 is a 400-dot pixel.
It's a dot. Figure 5 is a table of contents of pixel data, 7.8
is display start position data, 9.10 is color information indicating the brightness of blue color, 11 and 12 is color information indicating the brightness of kneading, and 13.14 is color information indicating the brightness of red color. FIG. 6 is a block diagram of an embodiment of the present invention, in which 15 is a CPU that processes data, 16 is a pixel data memory for display, 17 is a latch that temporarily stores the output of the pixel data memory, and 18 is a The same latch, 19 is a shift register that delays color information according to display start position data, 20 is a latch that temporarily stores display start position data, 2
1 is a D-A converter that converts digital values of color information into analog values; 22 is a CRT drive circuit that converts voltage for the CRT; 23 is a CRT display;
24 is a deflection circuit for CRT scanning, 25 is a basic clock oscillation circuit for operating the entire system, 26 is a counter for advancing the display address, and 27 is a timing generation circuit for obtaining CRT scanning timing. 28
32 is a display data line, 33 is a voltage line for display, 34 is a display start position data line, 36 is an address line for setting pixel data, 37 is an address line for reading out for display, 38 is a CPU 1
39 is a clock line that separates each pixel; 40 is a clock line that outputs four times the frequency of clock 39 for moving the display position; 4
1 is a control line that controls the timing generation circuit 27 from the display address counter 26, 42 is a control line for the position data latch 20, and 43 is a CRT.
This is a synchronizing signal line for 23 scanning. Reference numeral 44 denotes an AND gate which receives as input the signal outputted from the basic clock generation circuit 25 and the signal outputted from the position data latch 2o for each pixel.

Next, the operation of the above configuration will be explained.

The CPU 15 loads pixel data 7 to 14 in FIG. 5 to the pixel data memory 16 through the data line 28 to the address specified by the address line 36. The pixel data that has entered the memory 16 is temporarily stored in the latch 17 in synchronization with the clock 39 through the data line 29 in response to an instruction from the address line 37 output from the count state of the display address counter 26. Furthermore, the pixel data is transferred to the latch 18 at the timing of the next clock 39. The pixel data appearing at the output of the latch 18 is as shown in FIG.
According to the contents, input to position data latch 2o through
When color information data 9 to 14 of the pixel data from Latte 18 are input to the color data delay shift register 19 through the data line 32, the output of display positions 1 to 4 is delayed as shown in FIG. Let's do it. Data 7 shown in Figure 5
．． When both 8 are '0〃, the display position is 1, when data 7 is ``Ant O'' and data 8 is 11〃, the display position is 2, and when data 7 is 11N and data 8 is ``OI'', the display position is 3. At the display position of
The control line 42, which is the output of the position data latch 2o, controls the shift register 19 so that only the necessary number of clocks 4o are required in order to display data 7 and 8 at the display position of the clock 4 of '1'. The clock 39 is 1 for each pixel.
cycle, but clock 4o is 4 times 4 cycles
' is output, and the timing of display start positions 1 to 4 shown in FIG. 3 is created. Furthermore, the control line 42 of the position data latch 20 is controlled so that pre-processing is prioritized so that if display position 4 and display positions 1 to 3 are consecutive, the next display is not performed until the display of display position 4 is completed. .

On the other hand, if display position 1 and display position 4 are consecutive, the data at display position 1 will continue to be displayed because it is latched and the blank space will not be left open. In these cases, if the basic size of a pixel is 1, the largest pixel is 1+0.75=1.75, and the smallest pixel is 0.25. Therefore, a frequency band that is four times the maximum is required, but this is because the CPU 15
Since this is based on the instruction, the internal processing of the CPU 15 is used to control the frequency so that it does not reach this frequency. Also, it can be said that there is usually no need to change the color continuously from display position 4 to display position 1 to display position 4. In the display shown in Figure 4, the pixel size is 0.35 m x 0.3 m. (Length x Width) is the standard.Due to the human color sense, it is impossible to see a point as thin as 1 unless the eye is brought close to it, and the color shift of high-precision CRTs is usually 0.1 point. Therefore, it is completely meaningless. The reasons why high definition is usually used are (1) for graphic display devices that draw free straight lines or curves as smooth lines, and (2) for image processing devices that mix colors alternately to produce intermediate colors. It is considered possible to do so. In the present invention, these problems can be solved by shifting the display position and increasing the color information itself, and the CRT drive circuit 22, CRT 23, and deflection circuit 24 can have the same performance as the conventional ones, which is an additional effect. .

As explained above, by including the display start position information in the pixel data, it is possible to achieve almost the same display as an expensive high-definition CRT display device using the same CRT, video amplifier, and peripheral circuitry as before. It has the effect of being able to do the following.

Furthermore, since the number of pixels is small, the remaining pixel data storage area can be used for display colors, allowing for richly colored expressions.

Furthermore, in the case of conventional displays on TV receivers in ordinary homes, since both the cathode ray tube and the video amplifier are intended for receiving images from broadcasting, the frequency characteristics are narrow and display performance cannot be increased by other means. For example, it has the effect of providing graphics display comparable to that of a dedicated CR7 display device.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of diagonal line display using pixels in the conventional method.
FIG. 2 is a diagram showing an example of diagonal line display with the same number of pixels as in FIG. 1 according to the present invention, FIG. 3 is a pixel display comparison diagram according to the present invention, FIG. The figure is a diagram showing the contents of pixel data according to the present invention, and FIG. 6 is a block diagram showing the configuration of an embodiment of the present invention, in which 7 and 8 are display start position information data, 9 to 14 are color information, and 16 is a block diagram showing the configuration of an embodiment of the present invention. An image data memory, 17 a shift register for delaying color data, 2o a position data latch, and 23 a CRT display. 1

Claims (1)

[Claims] A control method for a CRT display device, characterized in that pixel data to be displayed includes display start position information for subdividing pixels.