JP2004118217A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which can display not only a video signal corresponding to a 4:3 aspect ratio, but also a video signal corresponding to a 16:9 aspect ratio without causing distortion and without altering functions of an existent video signal processing system. <P>SOLUTION: An RGB signal obtained from a video chroma circuit 1 is thinned out for every 4th horizontal scanning line and the RGB signal corresponding to the respective remaining horizontal scanning lines which are left without being thinned out is displayed on respective lines on a liquid crystal display panel. A timing signal generating circuit 7 supplies a timing signal necessary for this display control to a data line driving circuit 5 and a scanning line driving circuit 6. In the area of the liquid crystal panel 4 where no picture is displayed, display of, for example, black color is made by sending a MASK signal generated by a mask signal generating circuit 2 which is specially provided. <P>COPYRIGHT: (C)2004,JPO

Description

<< The present invention relates to a so-called active matrix type liquid crystal display device.

In an active matrix type liquid crystal display device, a plurality of scanning lines and a plurality of data lines are arranged orthogonally, and a switching transistor such as a TFT (thin film transistor) is provided at each intersection of the scanning lines and the data lines to drive a liquid crystal. And an electrode. In this type of liquid crystal display device, a pixel is displayed by applying a signal voltage to an electrode via each switching transistor. At that time, the switching transistor and the electrode exhibit an action of holding the signal voltage. Therefore, the signal voltage is less attenuated, so that a display with a high gradation can be performed. For this reason, the use of the active matrix type liquid crystal display device is gradually expanding.

Now, in the display device, generally, the arrangement of pixels corresponding to the aspect ratio of the video signal to be displayed is determined. For example, an NTSC video signal generally corresponds to an aspect ratio of 4: 3 (hereinafter simply referred to as 4: 3), and a display device for displaying the video signal conforms to this aspect ratio. The position of each pixel is determined.

However, depending on the application, a video signal corresponding to an aspect ratio different from the optimum aspect ratio is supplied to the display device, and the display is performed. For example, an image signal of a wide image captured by a video camera generally corresponds to an aspect ratio of 16: 9 (hereinafter simply referred to as 16: 9). When such a display of a video signal having an aspect ratio of 16: 9 is performed by a display device adapted to an aspect ratio of 4: 3, an original video is compressed in the horizontal direction, and a vertically distorted video is displayed. The Rukoto.

As a means for solving such a problem, it is conceivable to change the design of the display device itself so as to support the aspect ratio of 16: 9. The displayed video signal cannot be displayed normally.

Therefore, as a solution in this case, when a video signal having an aspect ratio that is not compatible with the display device is supplied, a video corresponding to the video signal is uniformly compressed in the vertical or horizontal direction and displayed. Thus, means for performing display without distortion can be considered.

In this case, since the video of one screen is compressed and displayed, a blank area where no video is displayed is generated on the display screen, and handling of the display of the blank area becomes a problem. Here, when displaying an image corresponding to the image signal, it is necessary to convert the image signal into a color signal such as an RGB signal by a video signal processing system such as a video chroma circuit and supply the color signal to a display device. In general, in this video signal processing system, a method of generating an RGB signal for displaying black using an external video input function such as an on-screen function and supplying the same to a display device is considered. However, if this method is adopted, when the video signal processing system stops generating the RGB signal corresponding to the black display and starts generating the RGB signal corresponding to the video signal, the control of the level of the RGB signal is transient. A problem that the state becomes unstable. Further, most of the video signal processing system such as a video chroma circuit is generally implemented as an IC. Therefore, it is preferable to realize the display control of the margin area without changing the design of this part.

The present invention has been made in view of the above circumstances, and can display images of video signals corresponding to various aspect ratios without changing the design of a video signal processing system, and It is an object of the present invention to provide a liquid crystal display device capable of displaying a fixed color in a blank area generated on a display screen in such a case.

The present invention has a liquid crystal display panel in which a plurality of pixels are arranged in a matrix, inputs a video signal composed of a plurality of horizontal scanning lines, and forms an image corresponding to each horizontal scanning line based on the video signal. In a liquid crystal display device for sequentially displaying on each row constituting the liquid crystal display panel,
Based on the video signal, video signal processing means for generating a display signal for displaying the video represented by the video signal on the liquid crystal display panel,
Mask signal generating means for generating a mask signal for displaying a predetermined color on the liquid crystal display panel;
A switching circuit that selects and outputs one of the display signal or the mask signal based on a selection signal,
The selection signal for selecting the display signal is supplied to the switching circuit during a period in which the display signal representing the display target is output from the video signal processing means, and the other period is used for selecting the mask signal. A selection signal is supplied to the switching circuit, and a display signal and a mask signal output through the switching circuit are respectively supplied to pixels of a predetermined area of the liquid crystal display panel, and the display signal is supplied to the predetermined area. The display signal is thinned out in a period of supplying to the pixel, and a timing signal for outputting the mask signal to the liquid crystal display panel at a higher frequency than supplying the display signal to the liquid crystal display panel is output. A liquid crystal display device comprising a timing signal generating means.

According to the invention, display based on the display signal is performed in a predetermined area of the liquid crystal display panel, and display based on the mask signal is performed in other areas. Here, since the mask signal is generated by means different from the display signal, there is no need to change the design of the video signal processing means for generating the display signal. Further, since the mask signal is generated, the function of the video signal processing means is not impaired.
According to the present invention, display control is performed in a blank area generated when a video signal corresponding to various aspect ratios or a video signal of a different signal system is displayed on a common liquid crystal display panel. There is an effect that it can be implemented without any change.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
A. FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention. As shown in the figure, the liquid crystal display device according to the present embodiment includes a video chroma circuit 1, a mask signal generating circuit 2, a switching circuit 3, a liquid crystal display panel 4, a data line driving circuit 5, a scanning line driving circuit 6, and a timing. It has a signal generation circuit 7. Note that the present embodiment holds both when the data line driving circuit 5 and the scanning line driving circuit 6 are formed inside the liquid crystal display panel 4 and when the data line driving circuit 5 and the scanning line driving circuit 6 are arranged outside the liquid crystal display panel 4 and connected to the liquid crystal display panel 4. I do.

This liquid crystal display device is supplied with an NTSC video signal VIDEO from a tuner or a personal computer (not shown). As is well known, in the NTSC system, one screen is represented by 525 horizontal scanning lines (line images), and a horizontal synchronizing signal and a vertical synchronizing signal are added to a video signal corresponding to the 525 horizontal scanning lines. A video signal for one screen is configured. Such a video signal VIDEO is supplied to the liquid crystal display device at a transmission rate of one screen every fixed frame period, and the display is performed by the liquid crystal display panel 4.

The video chroma circuit 1 is a circuit that generates and outputs an RGB signal and a synchronization signal CSYNC based on the video signal VIDEO supplied in this manner. Here, the RGB signals are composed of analog signals for three colors of R, G, and B that determine the display color of each pixel constituting the liquid crystal display panel 4, and correspond to the horizontal scanning lines in the video signal VIDEO. It is generated based on the obtained video signal. The synchronization signal CSYNC is a signal composed of a horizontal synchronization signal and a vertical synchronization signal included in the video signal VIDEO.

The mask signal generation circuit 2 is a circuit that generates a MASK signal. The MASK signal is used to display a halftone color (hereinafter, referred to as a mask color) such as black, white, or gray in a margin region where no image is displayed in the liquid crystal display panel 4 when the margin region is not displayed. Signal. That is, in the present embodiment, display is performed on the liquid crystal display panel 4 by the RGB signal generated based on the video signal VIDEO. However, depending on the type of the video signal VIDEO, a blank area where no video is displayed is provided on the liquid crystal display panel 4. May occur. In the present embodiment, a mask color is displayed in the blank area generated in this manner. A signal for displaying the mask color is a MASK signal.

Here, in order to display both the image and the mask color on the liquid crystal display panel 4, it is necessary to switch between the RGB signal and the MASK signal and supply them to the liquid crystal display panel 4. The switching circuit 3 is a means provided to switch between the RGB signal and the MASK signal. The switching circuit 3 uses an analog switch or the like to generate an RGB signal based on a selection signal VLS supplied from a timing signal generation circuit 7 described later. One of the MASK signals is selected and output.

Next, the liquid crystal display panel 4, the data line driving circuit 5, and the scanning line driving circuit 6 will be described. First, the liquid crystal display panel 4 is configured by arranging pixels for display in a matrix. FIG. 2 shows a basic configuration of the liquid crystal display panel 4. Since the liquid crystal display panel 4 performs color display, the actual pixels are composed of portions corresponding to each of the three colors of RGB. However, in FIG. not going.

As shown in this figure, the liquid crystal display panel 4 has a large number of scanning lines 11, 11,... And a large number of data lines 12, 12,. An electrode 13 (hereinafter, referred to as a pixel electrode) constituting a pixel and a TFT (thin film transistor) 14 are arranged in each section. The liquid crystal is interposed between the pixel electrode 13 disposed at each intersection and a common electrode connected to a reference power supply (not shown). The drains of the TFTs 14 arranged at the respective intersections are connected to the pixel electrodes 13 at the intersections, and the gates and the sources are respectively connected to the scanning lines 11 and the data lines 12 constituting the intersections.

In such a configuration, for example, when an H-level voltage is applied to the uppermost scanning line 11 in FIG. 2, the TFTs 14, 14,... As a result, the voltage output to each data line 12, 12,... Is applied to the uppermost row of pixel electrodes 13, 13,. The liquid crystal drive for performing the operation is performed.

The data line driving circuit 5 and the scanning line driving circuit 6 are means for sequentially applying a voltage corresponding to an RGB signal or a MASK signal to each of the pixel electrodes 13, 13,... Constituting the liquid crystal display panel 4.

More specifically, the data line driving circuit 5 includes the following components.
a. Sample hold circuits corresponding to one row of pixels in the liquid crystal display panel 4 These sample hold circuits sequentially hold RGB signals or MASK signals corresponding to one row of pixels, and Is output.

b. Means for sequentially holding the RGB signal or MASK signal output from the switching circuit 3 to each of the sample and hold circuits. This means includes a pointer constituted by a shift register, and a sample and hold circuit which stores the RGB signal and the like indicated by the pointer. And a circuit for supplying the circuit. Here, a shift register CL serving as a pointer is supplied with a shift clock CLX and a write command signal DX. These are all signals generated by a timing signal generation circuit 7, which will be described later. The shift clock CLX is continuously generated at a constant frequency, and the write command signal DX is used to display an image for one horizontal scanning line. This is generated prior to displaying on one row of pixels of the liquid crystal display panel 4. This write command signal DX is sequentially shifted to a subsequent stage by a shift register in synchronization with a shift clock CLX. Then, the RGB signal or the MASK signal is written to the sample and hold circuit corresponding to the stage that holds and outputs the write command signal DX among the stages of the shift register.

The scanning line driving circuit 6 is constituted by a shift register. This shift register plays a role of a pointer, similarly to the shift register in the data line driving circuit 5, and outputs a write command signal DY generated by a timing signal generating circuit 7 described later to a shift command generated by the same. Shift to the subsequent stage sequentially in synchronization with the clock CLY. By this shift operation, a write command signal DY is output from each stage of the shift register and sequentially applied to the scanning lines of each row of the liquid crystal display panel 4. In this way, a row in the liquid crystal display panel 4 is selected, and the voltage output to each data line by the driver is applied to each pixel electrode belonging to the selected row.

Based on the synchronization signal CSYNC output from the video chroma circuit 1, the timing signal generation circuit 7 performs various operations required for display control of the liquid crystal display panel 4, such as the above-described write command signals DX, DY, shift clocks CLX, CLY, and the like. This is a means for generating a timing signal.

Here, in the liquid crystal display panel 4, the arrangement of each pixel electrode is determined on the assumption that a video signal corresponding to an aspect ratio of 4: 3 is supplied. Therefore, when the video signal VIDEO corresponding to such an aspect ratio is supplied to the video chroma circuit 1, the RGB signals corresponding to the respective horizontal scanning lines sequentially output from the video chroma circuit 1 are directly applied to the respective rows of the liquid crystal display panel 4. , And the timing signal generation circuit 7 outputs a timing signal for such display control.

However, the present embodiment handles not only such a video signal but also a video signal VIDEO corresponding to a 16: 9 aspect ratio. When the RGB signals obtained from the video signal VIDEO corresponding to the 16: 9 aspect ratio are displayed on each row of the liquid crystal display panel 4 as they are, an image extending in the row arrangement direction is displayed. Therefore, when the video signal VIDEO having such an aspect ratio is supplied, the following display control is performed.

a. Thinning-out display control Instead of displaying the RGB signals corresponding to each horizontal scanning line obtained from the video signal VIDEO on the liquid crystal display panel 4 as they are, the RGB signals are thinned out at a rate of one per four horizontal scanning lines, and the remaining RGB signals are left. The signal is displayed on the liquid crystal display panel 4. The timing signal generation circuit 7 generates a write command signal DX, a write command signal DY, and a shift clock CLY necessary for such thinning display. The specific generation of these timing signals will be clarified in the description of the operation of the present embodiment. As a result of such control, the display image represented by the RGB signals is compressed in a pseudo manner to 3/4 in the row direction, and the original image represented by the video signal VIDEO is displayed without distortion. Displayed on panel 4. In this case, the display mode of the image includes a first display mode in which the image is displayed in the vertical center of the liquid crystal display panel 4 as shown in FIG. 3 and a display mode in which the image is packed above the liquid crystal display panel 4 as shown in FIG. There is a second display mode. The user can select a desired display mode from these.

b. Mask Color Display Control When the display on the liquid crystal display panel 4 is performed by thinning out the RGB signals, a blank area where no image is displayed is generated on the liquid crystal display panel 4 as shown in FIGS. Therefore, using a period in which no image is displayed, the MASK signal generated by the mask signal generation circuit 2 is supplied to the liquid crystal display panel 4 to display a mask color in a blank area. The timing generation circuit 7 generates a write command signal DX, a write command signal DY, and a shift clock CLY necessary for displaying the mask color.

B. Operation of the present embodiment Next, the operation of the present embodiment will be described. The operation when the video signal corresponding to the aspect ratio of 4: 3 is supplied is not different from the operation of the conventional general liquid crystal display device, and therefore the description is omitted, and the aspect ratio of 16: 9 will be described below. Only the operation for displaying a video signal corresponding to the above will be described.

(1) First Display Mode FIGS. 5 and 6 are time charts showing waveforms of various timing signals generated in the first display mode (FIG. 3). FIG. 5 shows an odd field in the first half of one frame period. FIG. 6 shows each waveform in the period, and FIG. 6 shows each waveform in the latter half even field period. 5 and 6, there is an item "scanning line No.". A series of numbers shown here indicates a horizontal line corresponding to the RGB signal output from the video chroma circuit 1 at each time. This shows the number of the scanning line.

(5) As shown in FIGS. 5 and 6, the synchronization signal CSYNC includes a horizontal synchronization signal and a vertical synchronization signal originally included in the video signal VIDEO. The timing signal generation circuit 7 separates the horizontal synchronization signal and the vertical synchronization signal, extracts them from the synchronization signal CSYNC, and outputs them as signals OFH and MVSYNC.

The signal OFH is counted by a counter provided in the timing signal generation circuit 7. 5 and 6, an item "internal count number" is provided, which indicates the count value of this counter.

Also, the scanning line No. 4 to the scanning line No. 5 and the scanning line No. 5 266 to the scanning line No. At the timing of transition to 267, the first rise of the signal OFH exists after the signal MVSYNC goes high, and the rise of the signal OFH is used as a vertical reset signal. That is, at the rise of the signal OFH, the counter that counts the signal OFH is reset. Therefore, the internal count number changes from 1 to 262 in the odd field and from 1 to 263 in the even field. Further, each time the vertical reset signal appears, the level of the signal MFS is inverted.

Therefore, it can be determined whether the current field is an odd field or an even field based on the level of the signal MFS. Based on the internal count number, the RGB signal currently output from the video chroma circuit 1 can be determined based on the current field. It is possible to determine the number of the horizontal scanning line corresponding to. The timing signal generation circuit 7 refers to these pieces of information instead of a clock, and controls generation of a timing signal necessary for display control. That is, it is as follows.

First, the shift clock CLY is a two-phase clock composed of a normal phase clock CLY and an inverted phase clock obtained by inverting the same (in FIG. 5 and FIG. 6, the signal name is indicated by a signal name with “CLY” overlined). . Note that, in FIG. 1, in order to prevent the drawing from being complicated, “CLY” is simply used. The shift clock CLY is generated by dividing the frequency of the signal OFH. However, the level is not inverted every time in synchronization with the rise of the signal OFH, and there are some places where the level is not inverted. The control of the level inversion of the shift clock CLY is also performed based on the value of the internal count number. The signal FRP is a timing signal for inverting the polarity of the RGB signal output from the video chroma circuit 1 with respect to the potential of the common electrode of the liquid crystal display panel 4 in synchronization with the shift clock CLY. 1 and the mask signal generation circuit 2. The mask signal generation circuit 2 outputs the MASK signal whose polarity is inverted with respect to the potential of the common electrode of the liquid crystal display panel 4 in synchronization with the shift clock CLY by receiving the signal FRP.

(4) The write command signal DY is at the H level during a period from when the internal count number becomes “250” to “252” in each field. The write command signal DY is written to the scanning line drive circuit 6 by the shift clock CLY, and thereafter, is sequentially shifted to a subsequent stage in synchronization with the shift clock CLY. When the internal count reaches “257”, the write command signal DY reaches the stage connected to the first line of the liquid crystal display panel 4, and the write command signal DY is output to the scan line. Is done. As a result, the voltage output to each data line of the liquid crystal display panel 4 at that time is applied to the pixel electrodes in the first row.

Thereafter, the write command signal DY is shifted in synchronization with the shift clock CLY, the write command signal DY is sequentially applied to the scanning lines of the second and subsequent rows of the liquid crystal display panel 4, and each pixel of each row is Writing to the electrodes is performed. At the bottom of FIG. 5 and FIG. 6, an item “write line to panel” is provided, and the series of numbers described here correspond to each row of the liquid crystal display panel 4 to which writing is performed in this manner. Are shown.

On the other hand, when the internal count number becomes “252” in the even field, the selection signal VLS goes to the H level, and thereafter, the selection signal VLS is at the H level during the period until switching to the odd field and the internal count number to “22”. To maintain.

Therefore, during this time, scan No. 519 to 525 and scanning line Nos. The RGB signals corresponding to 1 to 26 are output from the video chroma circuit 1, but not the RGB signals but the MASK signal is selected by the switching circuit 3. Then, this MASK signal is output to each data line of the liquid crystal display panel 4 via the data line driving circuit 5 and written to each pixel electrode of the row designated by the write command signal DY output from the scanning line driving circuit 6. It is. Also, during the period when the signal VLS is at the H level, the level of the shift clock CLY is inverted each time the signal OFH rises. Accordingly, during this time, the scanning line No. Each time is updated, the row number for writing on the liquid crystal display panel 4 is updated by one.

By the way, during the period from when the internal count number becomes “257” to “18”, as shown in FIG. 5, writing to each row of row numbers “1” to “24” of the liquid crystal display panel 4 is not performed. Proceed. This writing is performed as a result of shifting the write command signal DY output when the internal count number becomes “250” in the scanning line driving circuit 6 in synchronization with the shift clock CLY.

On the other hand, in parallel with the writing, writing to each row of the liquid crystal display panel 4 with the row numbers “207” to “230” proceeds. This is because the write command signal DY written in the scan line drive circuit 6 at a timing one field earlier than the time when the write command signal DY is written to the scan line drive circuit 6 is applied to the scan line drive circuit 6. The write instruction signal DY remains in the drive circuit 6 and is performed.

As described above, over a certain period, the voltage output to each data line of the liquid crystal display panel 4 is redundantly written to each pixel electrode of two rows, so that the mask color is displayed in the blank area of the liquid crystal display panel 4. Required time can be adjusted.

(4) When the internal count number becomes “22” in the odd field, the selection signal VLS is set to the L level. As a result, the RGB signals are selected by the switching circuit 3 and supplied to the liquid crystal display panel 4 via the data line driving circuit 5 to start displaying an image. During the period in which the video is displayed, the shift clock CLY repeats a level change in which, instead of inverting the level every time in response to the rise of the signal OFH, inverts the level three times and then pauses once.

(4) When the level inversion of the shift clock CLY does not occur, the write command signal DX is not generated. Therefore, at this time, the RGB signals output through the switching circuit 3 are not written to the data line driving circuit 5 and are not output from the data line driving circuit 5 to the data lines of the liquid crystal display panel 4. . For example, the scanning line No. in FIG. Since the write command signal DX is not given to the data line drive circuit 5 at the time of output of each of the RGB signals 28, 32, and 36, writing to the liquid crystal display panel 4 is not performed.

When the writing is not performed, the level inversion of the shift clock CLY does not occur, so that the writing command signal DY in the scanning line driving circuit 6 is not shifted, and the row number to be written in the liquid crystal display panel 4 is also changed. It does not change.

Thus, in the period in which an image is displayed, the RGB signals are thinned out at a ratio of one horizontal scanning line to four horizontal scanning lines. As a result, the image of the image signal corresponding to the aspect ratio of 16: 9 is displayed on the liquid crystal display panel 4 without distortion.

Then, when the internal count number becomes “252” in the odd field, the selection signal VLS is set to the H level, and thereafter, the mode is switched to the even field, and the selection signal VLS remains at the H level until the internal count number becomes “23”. Maintain the level (Figure 6). During this time, the MASK signal for displaying the mask color is written to the liquid crystal display panel 4 as described above.

(4) Then, when the internal count number becomes “23” in the even field, the selection signal VLS is set to L level, and the display of the video is started again. Also in this case, as in the case of the odd field, the RGB signals are thinned out at a rate of one horizontal scanning line to four horizontal scanning lines. However, in this case, RGB signals corresponding to horizontal scanning lines different from those culled in the odd field are culled. FIG. 7 shows a horizontal scanning line in which thinning is performed in an odd field and a horizontal scanning line in which thinning is performed in an even field, which are indicated by oblique lines and compared. As shown in the figure, each horizontal scanning line sandwiched between each horizontal scanning line that has been thinned out in the odd field is subjected to thinning in the even field. Since the thinning target is made different between the odd field and the even field as described above, loss of display information can be reduced, and deterioration of image quality can be prevented.

(2) Second Display Mode In this second display mode, a blank area is provided below the liquid crystal display panel 4, as shown in FIG. In the second display mode, after the writing of the RGB signals of the video to be displayed in each field to the liquid crystal display panel 4 is completed, the RGB signals of the video to be displayed in the next field are changed to the video chroma circuit 1. The MASK signal must be written in each row of the liquid crystal display panel 4 corresponding to the above-mentioned margin area until the signal is output. In the first display mode, writing of the MASK signal was performed in synchronization with the shift clock CLY obtained by dividing the signal OFH. However, if the shift clock CLY having such a low frequency is used in the second display mode, the RGB signal of the image to be displayed is converted to the video chroma circuit before the writing of the MASK signal to the liquid crystal display panel 4 is completed. 1 is output. Therefore, in the present embodiment, as shown in FIGS. 8 and 9, a high-frequency shift clock CLY in which a signal having the same frequency as the signal OFH and a signal obtained by dividing the signal OFH are interleaved is generated. The writing of the MASK signal to the liquid crystal display panel 4 is performed using the clock CLY. Note that the thinning-out display control when displaying the RGB signals on the liquid crystal display panel 4 is the same as in the case of the first display mode, and a description thereof will be omitted.

As described above, the case where the video signal corresponding to the aspect ratio of 16: 9 is displayed on the liquid crystal display panel corresponding to the aspect ratio of 4: 3 has been described as an example. As shown in FIG. Also, when a video signal corresponding to 16 is displayed on a liquid crystal display panel corresponding to a 16: 9 aspect ratio, a blank area where no video is displayed occurs. Therefore, the present invention may be applied to such processing of the blank area.

Also, as shown in FIG. 11, for example, a liquid crystal display panel designed to support the PAL system is designed to display video signals of the NTSC system, and is originally designed to support more horizontal scanning lines. Also, when displaying an image of a signal system having a smaller number of horizontal scanning lines on the liquid crystal display panel, a blank area where no image is displayed occurs. Therefore, the present invention can be applied to the processing of such a blank area.

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a liquid crystal display panel of the same embodiment. FIG. 3 is a diagram showing a display mode of the embodiment. FIG. 3 is a diagram showing a display mode of the embodiment. It is a time chart which shows operation of the embodiment. It is a time chart which shows operation of the embodiment. It is a time chart which shows operation of the embodiment. It is a time chart which shows operation of the embodiment. It is a time chart which shows operation of the embodiment. It is a figure explaining other embodiments of the present invention. It is a figure explaining other embodiments of the present invention.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... Video chroma circuit 2 ... Mask signal generation circuit 3 ... Switching circuit 4 ... Liquid crystal display panel 5 ... Data line drive circuit 6 ... Scan line drive circuit 7 ... Timing signal generation circuit

Claims (5)

A liquid crystal display panel in which a plurality of pixels are arranged in a matrix, a video signal composed of a plurality of horizontal scanning lines is input, and an image corresponding to each horizontal scanning line is displayed based on the video signal. In a liquid crystal display device that sequentially displays on each row constituting
Based on the video signal, video signal processing means for generating a display signal for displaying the video represented by the video signal on the liquid crystal display panel,
Mask signal generating means for generating a mask signal for displaying a predetermined color on the liquid crystal display panel;
A switching circuit that selects and outputs one of the display signal or the mask signal based on a selection signal,
The selection signal for selecting the display signal is supplied to the switching circuit during a period in which the display signal representing the display target is output from the video signal processing means, and the other period is used for selecting the mask signal. A selection signal is supplied to the switching circuit, and a display signal and a mask signal output through the switching circuit are respectively supplied to pixels of a predetermined area of the liquid crystal display panel, and the display signal is supplied to the predetermined area. The display signal is thinned out in a period of supplying to the pixel, and a timing signal for outputting the mask signal to the liquid crystal display panel at a higher frequency than supplying the display signal to the liquid crystal display panel is output. A liquid crystal display device comprising: timing signal generating means. The liquid crystal display device according to claim 1, wherein the timing signal for supplying the mask signal to the liquid crystal display panel is a signal in which a signal of a predetermined frequency and a signal obtained by dividing the signal are mixed. 2. The liquid crystal display device according to claim 1, wherein the timing signal is a signal for thinning out the display signal in units of the horizontal scanning lines. The video signal is composed of a plurality of fields,
4. The liquid crystal display device according to claim 3, wherein the timing signal is a signal for thinning out the display signal by a different thinning method for each of the plurality of fields. 2. The liquid crystal display device according to claim 1, wherein the timing signal is a signal for thinning out the display signal in at least one of a direction along the horizontal scanning line and a direction crossing the horizontal scanning line.

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