JP2001343951A - Liquid crystal driving device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving device in which frequency of the shift clock of a scanning driver is reduced while displaying a black strip region that is set for displaying a wide image on a liquid crystal display panel and which has reduced size (integrated) and saved power consumption and a method for driving the device. SOLUTION: When a wide image having an aspect ratio that differs from a display screen size is to be displayed on a liquid crystal display panel in which plural liquid crystal pixels are arranged in a matrix manner, a portion of the wide image is displayed in either one of an upper display region or a lower display region, black color display is provided to an upper black strip Bu or a lower black strip Bd included in an another display region and the process, in which a scanning line of the black strip region is selected and the scanning is conducted, and the process, in which a scanning line of the wide image is partially selected and the scanning is conducted, are overlapped in time wise (simultaneously) and executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device and a driving method therefor, and more particularly to a liquid crystal driving device in which an image displayed based on a video signal is longer than a screen of a liquid crystal display panel.
The present invention relates to a liquid crystal driving device for displaying a black band in upper and lower regions of a liquid crystal display panel and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, as a monitor or a display of an information terminal such as a computer or a video device, a liquid crystal display (Liquid Crystal Display) having features such as thinness, space saving and power saving has been used instead of a conventional cathode ray tube (CRT). L
CD) is being used frequently. On the other hand, in the field of broadcasting technology, ordinary NTSC (National Tel
evision System Committee), which has a wider aspect ratio (aspect ratio) of 9:16 than that of a 3: 4 aspect ratio television image, that is, a wide-screen television image (hereinafter referred to as a “wide image”) is widely used. Is being used.

When such a wide image is displayed on a television provided with a liquid crystal display panel having an aspect ratio of 3: 4 corresponding to the NTSC system, for example, FIG.
As shown in (a), while maintaining the aspect ratio 9:16 of the wide image Gw, the image size is compressed in accordance with the screen width of the liquid crystal display panel 110, and displayed in the center area of the screen. Above and below Gw, a black upper black band Bu and a lower black band Bd where no image is displayed are displayed.

More specifically, as shown in FIG. 6B, in the case of a liquid crystal display panel 110 having 240 scanning lines X1 to X240, a wide image Gw
Of the scan lines X31 to X210
0 lines are set, and scanning lines X1 to X30 and X211 to X24 above and below the wide image Gw are set as display areas of the upper black band Bu and the lower black band Bd.
30 lines each for 0 (a total of 60 lines) are set.
In the following description, it is assumed that the wide image Gw, the upper black band Bu, and the lower black band Bd are displayed on the liquid crystal display panel 110 by the setting shown in FIG.

[0005] Next, a liquid crystal driving device for driving a liquid crystal display panel as described above will be briefly described, and then a display driving method of a wide image will be described. As shown in FIG. 7, the liquid crystal driving device generally includes a source driver 120 arranged in a column direction of the liquid crystal display panel 110.
And a gate driver (scan driver) 130 arranged in the row direction. The configuration other than the source driver 120 and the gate driver 130 will be described later.

The liquid crystal display panel 110 is arranged in a matrix, and has pixel electrodes and a common electrode (common electrode: not shown) arranged opposite to the pixel electrodes.
com), a liquid crystal capacitor Clc made of liquid crystal filled between the pixel electrode and the common electrode, a thin film transistor (hereinafter referred to as a pixel transistor) TFT having a source connected to the pixel electrode, and a liquid crystal capacitor Clc in parallel. A plurality of liquid crystal pixels 111 configured with the formed storage capacitors Cs, a gate line (scan line) Lg extending in the row direction of the matrix and connected to the gates of the plurality of pixel transistors TFT, Stretching in the column direction of
A signal line (data line) Ld connected to the drains of the plurality of pixel transistors TFT, and by applying a signal voltage to the liquid crystal pixel 111 selected by the source driver 120 and the gate driver 130,
The liquid crystal array is controlled to display and output predetermined image information.

[0007] The source driver 120 generally includes R, G,
Sample hold circuit 122 to which B image signal is input
And a shift register 121 for controlling the sample and hold operation of the sample and hold circuit 122. The sample and hold circuit control signal is output after being shifted in a certain direction by the shift register 121 based on the horizontal control signal. Are sequentially applied to the sample-and-hold circuit 22, so that the R, G, and B image signals (analog RG
A signal voltage corresponding to B) is supplied to each pixel electrode via each signal line Ld of the liquid crystal display panel 110.

On the other hand, the gate driver 130 is generally configured to include a shift register 131 and a buffer 132, and based on a vertical control signal, the shift register 131
The control signal (selection signal) shifted and output in a predetermined direction is applied to each gate line Lg of the liquid crystal display panel 110 via the buffer 132 as a predetermined gate signal (scanning signal). The driving of each pixel transistor TFT is controlled, and the signal voltage applied to each signal line Ld by the source driver 120 is applied to each pixel electrode via the pixel transistor TFT.

Here, a specific circuit configuration of the gate driver 130 applied to the conventional liquid crystal driving device is connected in series as shown in FIG.
By inputting PCK, a plurality of flip-flop circuits F / F1, F / F2 that output a selection signal (shift pulse signal) for each gate line while sequentially shifting a single gate start signal GSRT to a subsequent stage. , ... F
/ F240 and a plurality of logic gates (AND gates) AND1, which control the application state of the selection signal to each of the gate lines X1 to X240 based on a single output enable signal (also referred to as a “gate reset signal”) GRES. AND
2,... AND240.

Although not shown, a plurality of flip-flop circuits F / F1 and F / F1
F2,..., F / F240 are flip-flop circuits F / F1, F / F2, F / F3,.
In a fixed direction (forward direction) in this order.
Function of shifting T, and flip-flop circuit F
A function of shifting the gate start signal GSRT in the reverse direction (reverse direction) in the order of / F240, F / F239, F / F238,... Is appropriately controlled during image display drive processing.

Next, a method of driving a wide image display in the liquid crystal driving device having the above-described configuration will be described.
This will be described with reference to the drawings. Here, description will be made with reference to the configuration of the gate driver (FIG. 8) as appropriate. <
Step S101> In the gate driver 130 having the above-described configuration, first, the output enable signal G
RES is switched to the active level (low level),
In this state, the gate start signal GSRT is input to the input terminal IN of the flip-flop circuit F / F1, and the flip-flop circuits F / F1, F / F2,.
While sequentially shifting based on the timing of the gate pulse clock GPCK, the selection signal is applied to each of the logic gates AND1,
, And gate lines X1 to X31 are sequentially selected as shown in FIGS. 9A and 9B. Here, in step S101, a flip-flop circuit F / F1,
The shift operation executed by F / F2,... Is 31 times.

<Step S102> Next, at the timing when the gate line X31 is selected, the output enable signal GRES is switched to the off level (high level), and the image signal having the aspect ratio of 9:16 is supplied via the source driver 120. Is applied to each signal line. As a result, the scanning signal is applied from the logic gate AND31 to the gate line X31, and the signal voltage applied to the signal line is supplied to the liquid crystal pixels connected to the gate line X31, and the image on the first row of the wide image Gw The signal is written and displayed.

Then, while the output enable signal GRES is held at the off level (high level), the gate lines X31 to X210 are sequentially shifted in the forward direction while being selected, and the scanning signal is applied.
By applying a signal voltage based on the image signal to each gate line with 0, the wide image Gw is sequentially displayed as shown in FIG. 9C. Then, at the timing when the display of the wide image Gw ends, the flip-flop circuit F
By inputting the reset signal RESET to / F1, F / F2,..., The shift operation is reset, and the output enable signal GRES is switched to the active level (low level), thereby the scanning signal to each gate line is changed. Is interrupted to reset the selected state.

<Step S103> Next, the output enable signal GRES is switched to the off level (high level), and the flip-flop circuit F is switched at the timing of every other line of the gate pulse clock GPCK while being held.
The gate start signal GSRT is input to the input terminal IN of / F1, and the flip-flop circuits F / F1, F / F2,.
.. To sequentially output the selection signal to the logic gates AND2, AND4,... Every other line based on the timing of the gate pulse clock GPCK.
As shown in FIG. 9D, the gate lines X1 to X30
Even lines up to (X2, X4, X6,..., X30)
15) are selected to apply the scanning signal, and apply a signal voltage based on the image signal (black signal) of the upper black band Bu to each signal line via the source driver 120.

Thus, the gate lines X1 to X30
In the upper black band Bu region up to, black data is written to the liquid crystal pixels connected to the even lines. Here, in step S103, the gate lines X1 to X3
In the upper black band Bu region up to 0, only 15 even-numbered gate lines are selected. However, in order to output a selection signal, flip-flop circuits F / F1, F / F
The shift operation executed by 2,... Becomes 30 times.

<Step S104> Next, with the output enable signal GRES held at the off level (high level), the even lines (X2, X4, X6,..., X30) from the gate lines X1 to X30 are processed. .. By shifting the flip-flop circuits F / F1, F / F2,.
As shown in the figure, odd-numbered lines from the gate lines X1 to X30 (15 lines of X1, X3, X5,..., X29)
Only one of them is selected to apply a scanning signal, and a signal voltage based on the image signal (black signal) of the upper black band Bu is applied to each signal line via the source driver 120.

As a result, the gate lines X1 to X30
In the upper black band Bu region up to, black data is written to the liquid crystal pixels connected to the odd lines. Here, in step S104, the gate lines X1 to X3
The number of gate lines selected in the upper black band Bu region up to 0 is fifteen of the odd lines, but the flip-flop circuits F / F1, F / F2,
Is performed only once.
Accordingly, in addition to the above-mentioned fifteen even-numbered lines, black data is written to the fifteen odd-numbered gate lines, so that the entire upper black band Bu region of the liquid crystal display panel 110 (from the gate line X1 to the X30) is displayed in black.

The output enable signal GRES is switched to the active level (low level) at the timing when the black data is written to the liquid crystal pixels connected to the odd lines, thereby cutting off the application of the scanning signal to each gate line. To reset the selected state.

<Step S105> Next, with the output enable signal GRES held at the off level (high level), the flip-flop circuit F / F240 is output every other line of the gate pulse clock GPCK.
A gate start signal GSRT is input to an input terminal IN of the flip-flop circuits F / F240 and F / F23.
.., And sequentially shifts in the reverse direction based on the timing of the gate pulse clock GPCK, and changes the selection signal every other line to the logic gates AND239 and AND23.
, And the odd lines (X) from the gate lines X240 to X211 as shown in FIG.
239, X237, X235,..., X211
Only), a scanning signal is applied, and a signal voltage based on the image signal (black signal) of the lower black band Bd is applied to each signal line via the source driver 120. Here, in synchronization with the selection operation of the odd-numbered lines, the scanning signals applied to the gate lines X1 to X30 held in the selected state are changed in the opposite direction (from the lines X30 to X1).
In the direction) and reset.

As a result, the gate lines X211 to X2
In the lower black band Bd region up to 240, black data is written to the liquid crystal pixels connected to the odd lines. Here, in step S105, the gate line X2
Only 15 odd gate lines are selected in the lower black band Bd region from 11 to X240, but the flip-flop circuit F is used to output a selection signal.
/ F240, F / F239,... Are shifted 30 times.

<Step S106> Next, with the output enable signal GRES held at the off level (high level), odd lines (X239, X237, X235,..., X) from the gate lines X240 to X211 are held.
211), the flip-flop circuit F / F24
0, F / F 239,... Are shifted once in the forward direction at once, as shown in FIG. 10C, so that even-numbered lines (X21
2, X214, X216, ..., X240)
Only one is selected to apply a scanning signal, and a signal voltage based on an image signal (black signal) of the lower black band Bd is applied to each signal line via the source driver 120.

As a result, the gate lines X211 to X2
In the lower black band Bd area up to 240, black data is written to the liquid crystal pixels connected to the even lines. Here, in step S106, this gate line X2
The number of gate lines selected in the lower black band Bd region from 11 to X240 is fifteen of even lines,
A flip-flop circuit F / F for outputting a selection signal
The shift operation performed by the 211, F / F 212,... Is performed only once.

Therefore, in addition to the above-mentioned fifteen odd-numbered lines, the black data is written into the fifteen even-numbered gate lines.
10 (the gate line X211).
To X240) are displayed in black. By switching the output enable signal GRES to the active level (low level) at the timing when the black data is written to the liquid crystal pixels connected to the even-numbered lines, the application of the scanning signal to each gate line is cut off and selected. Reset state.

The polarity of the signal voltage applied to each signal line in step 103 and the polarity of the signal voltage applied to each signal line in step 104 are set to be opposite to each other. The polarity of the signal voltage applied to the line and step 1
In step 06, the polarity of the signal voltage applied to each signal line is set to be opposite to each other, and driving is performed so as to reduce the occurrence of flicker in the upper black band Bu region and the lower black band Bd region.

The above series of display driving processes S101 to S1
06 is repeatedly performed with a predetermined period as one cycle, but during the retrace period in which the wide image Gw is not displayed in the display driving process, the upper black band Bu and the lower black band Bd are displayed.
Must be displayed. In a series of display driving processes, in step S101, the gate line X
The shift operation when selecting 1 and the shift operation when selecting the even-numbered lines of the gate lines X211 to X240 in step S106 can be performed simultaneously. In step S104, the gate line X1
A shift operation when selecting an odd line of X30 from
In step S105, the gate lines X211 to X2
The first shift operation when selecting 240 can be performed simultaneously.

Therefore, by executing the above-described series of display driving processes, if the shift operation in step S101 and the shift operation in step S106 are performed simultaneously, the upper black band Bu region and the lower black band The number of shift operations required to drive the gate line in the Bd region for display is 92 (= 1 + 30 + 30 + 1).
+30), and the number of gate pulse clocks GPCK (shift clock) corresponding to the shift operation is supplied.

[0027]

As described above, in the conventional wide image display driving method, the shift operation for displaying and driving the upper and lower black bands is performed 92 times within an extremely short retrace period. Because of the necessity of the execution, the frequency of the shift clock supplied to the gate driver had to be greatly increased. Therefore, there was a problem as described below.

(1) In order to keep the frequency of the shift clock high, it is necessary to lower the impedance of the clock line. For that purpose, it is necessary to increase the width (thickness) of the wiring of the clock line, When the drivers are integrated, there is a problem that the device scale cannot be sufficiently reduced. (2) In addition, since a buffer circuit (not shown) for outputting a shift clock needs to be increased in accordance with an increase in frequency, there is a problem that it is difficult to reduce the size of the liquid crystal driving device. . (3) Further, there is a problem that power consumption increases as the frequency of the shift clock increases.

In view of the above problems, the present invention reduces the frequency of the shift clock of the scan driver when displaying a black band set with the display of a wide image on a liquid crystal display panel. Accordingly, it is an object of the present invention to provide a liquid crystal driving device and a driving method thereof, which can reduce the size of the device (integration) and reduce power consumption.

[0030]

According to the present invention, an image is displayed on a liquid crystal display panel having a plurality of liquid crystal pixels arranged in a matrix near an intersection of a plurality of scanning lines and signal lines. A liquid crystal driving device for transmitting a driving signal for applying the driving signal to the scanning lines of a first display area obtained by dividing the liquid crystal display panel in a horizontal direction. Generating means, and second drive signal generating means for applying the drive signal to the scan lines in a second display area obtained by dividing the liquid crystal display panel in the horizontal direction. It is characterized in that a preset band image is displayed in an area that is included in the second display area and does not display the image while displaying a part of the image.

That is, a driving signal (scanning signal) is applied to the scanning lines of the first display area of the liquid crystal display panel by the first driving signal generating means, and the driving signal of the liquid crystal display panel is applied by the second driving signal generating means. Since the drive signal is applied to the scan line in the second display area, the first signal of the liquid crystal display panel
And the second display area are individually controlled.
Therefore, when an image having an aspect ratio different from that of the display screen of the liquid crystal display panel, for example, when displaying a wide image, an operation of selecting and scanning a gate line of a black band image displayed above and below the wide image, The operation for selecting and scanning the gate line of the wide image can be performed in a manner overlapping with the time.

The liquid crystal driving device according to the second aspect is the first aspect of the invention.
In the liquid crystal driving device described above, the first drive signal generation means sequentially shifts a predetermined start signal to generate and output the drive signal applied to the scan line at a predetermined timing, And a first gate circuit for applying the drive signal output from the shift register to the scan line in the first display area based on a first control signal. The second drive signal generation means applies the drive signal output from the shift register to the scan line in the second display area based on a second control signal. And a gate circuit.

That is, the first drive signal generation means and the second drive signal generation means apply drive signals to the scan lines based on different control signals (output enable signals), and the liquid crystal display panel is driven by the first drive signal generation means and the second drive signal generation means. The display is divided into a first display area and a second display area, and the display is individually controlled. Therefore, for example, the liquid crystal display panel is divided into the first display region and the second display region by a simple configuration in which the existing gate circuit is divided into two groups and the operation of the gate circuits in each group is controlled by individual control signals. The display can be divided into two display areas and individually controlled.

According to a third aspect of the present invention, there is provided a liquid crystal driving device.
3. The liquid crystal driving device according to claim 2, wherein the liquid crystal driving device is connected to the scan line in the first display area and the second line.
, At least a part of the scanning lines in the display area are simultaneously selected. That is, the first drive signal generation means and the second drive signal generation means allow a part of the scan lines in the first display area of the liquid crystal display panel to be
Some of the scan lines in the second display area are selected at the same timing. Therefore, the first display area or the second display area
The operation of selecting and scanning the gate line of the wide image displayed in one of the display areas of the display area and the operation of selecting and scanning the gate line of the black band image displayed in the other area can be executed simultaneously. The number of operations for selecting only the black band image (shift operation during the flyback period) can be substantially reduced.

According to a fourth aspect of the present invention, there is provided a liquid crystal driving device.
4. The liquid crystal driving device according to any one of items 1 to 3, wherein the liquid crystal display panel has an aspect ratio of 3: 4, and the image displayed on the liquid crystal display panel has an aspect ratio of 9:16. It is characterized by having. That is, the liquid crystal display panel has an aspect ratio corresponding to the NTSC system, and a display of a so-called wide image having an aspect ratio different from that of the liquid crystal display panel is controlled on the liquid crystal display panel. Therefore, each of the above configurations is
The present invention is also well applied to a case where a wide image having an aspect ratio of 9:16 is controlled to be displayed on a liquid crystal display panel having an aspect ratio of 3: 4 corresponding to the system.

According to a fifth aspect of the present invention, there is provided a method of driving a liquid crystal driving device, comprising:
In a driving method of a liquid crystal driving device for transmitting a driving signal for displaying an image on a liquid crystal display panel having a plurality of liquid crystal pixels arranged in a matrix, a first display area obtained by dividing the liquid crystal display panel in a horizontal direction Alternatively, simultaneously with the step of displaying a part of the image in one of the second display areas, the image is included in the other of the first display area or the second display area, and the image is displayed. A step of displaying a preset band image in a region not to be set.

That is, when displaying an image having an aspect ratio different from the display screen size of the liquid crystal display panel, for example, a wide image, the first display area and the second display area of the liquid crystal display panel are individually controlled by display. Then, the operation of displaying a part of the wide image and the operation of displaying the black band images displayed above and below the wide image are performed at the same time. Therefore, the operation of selecting and scanning the gate line of the black band image can be executed simultaneously with the operation of selecting and scanning a part of the gate line of the wide image, and the operation of selecting only the black band image (return period). Medium shift operation)
Can be substantially reduced.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the display driving device according to the present invention will be described with reference to the drawings.
First, a liquid crystal display device to which the liquid crystal driving device according to the present invention is applied will be described. FIG. 1 is a schematic configuration diagram showing an overall configuration of a liquid crystal display device to which a liquid crystal driving device according to the present invention is applied. Here, as an example of the liquid crystal display device, a liquid crystal display device using an active matrix type liquid crystal display panel will be described, and a description of a configuration equivalent to the above-described related art (FIG. 7) will be simplified. .

As shown in FIG. 1, the liquid crystal display device to which the liquid crystal driving device according to the present invention is applied is roughly divided into a liquid crystal display panel 10, a source driver 20, a gate driver 30, an LCD controller 40, A system control IC 50 and a digital-analog converter (hereinafter referred to as D
/ A converter 60). Similar to the configuration shown in FIG. 7, the liquid crystal display panel 10 includes a plurality of liquid crystals arranged in a matrix at intersections of a plurality of gate lines (scan lines) extending in the row direction and signal lines extending in the column direction. A pixel is provided, and predetermined image information is displayed and output by applying a signal voltage based on an image signal to a liquid crystal pixel selected by the source driver 20 and the gate driver 30. Here, the liquid crystal display panel 10 applied to the present embodiment has, for example, an aspect ratio of 3: 4 corresponding to the NTSC system.

The source driver 20 has a sample and hold circuit 22 and a shift register 21 in the same manner as the configuration shown in FIG. 7, and is based on a horizontal control signal supplied from an LCD controller 40 described later. And a signal voltage corresponding to an analog RGB signal (RGB image signal) is supplied to the signal line Ld. Also, the gate driver 30
Is substantially the same as the configuration shown in FIG.
And a buffer 32, based on a vertical control signal supplied from the LCD controller 40, sequentially applying a scanning signal to each gate line Lg to select a gate line Lg, and intersecting the signal line Ld A signal voltage Ld supplied to the above-mentioned signal line is applied to the liquid crystal pixels arranged in the above. The specific configuration of the gate driver will be described later.

The LCD controller 40 includes a horizontal synchronizing signal HD, a vertical synchronizing signal VD, and a system clock SYS supplied from a system control IC 50 described later.
Generate a horizontal control signal and a vertical control signal based on CK,
By supplying the signals to the source driver 20 and the gate driver 30, respectively, a signal voltage is applied to the liquid crystal pixels at a predetermined timing, and control for displaying desired image information on the liquid crystal display panel 10 is performed.

The system control IC 50 supplies the system clock SYSCK to the source driver 20, the LCD controller 40, the D / A converter 60, and the like, and outputs the horizontal synchronizing signal HD and the vertical synchronizing signal VD synchronized with the system clock SYSCK to the LCD. Controller 4
Supply 0. In addition, a video signal composed of a digital RGB signal supplied from the outside of the liquid crystal display device is converted into an analog RGB signal (RGB image signal) via a D / A converter 60 and output to the source driver 20.

Next, a specific configuration of the gate driver applied to the present embodiment will be described with reference to the drawings. FIG. 2 is a main part configuration diagram showing a gate driver applied to the liquid crystal driving device according to the present embodiment. Here, the same reference numerals are given to the same components as those in the conventional technique (FIG. 8), and the description will be simplified.

As shown in FIG. 2, the gate driver 30 according to the present embodiment is connected in series, and receives a common gate pulse clock GPCK, thereby sequentially shifting the gate start signal GSRT, A plurality of flip-flop circuits F / F1, F / F2,... F for outputting a selection signal (shift pulse signal) for each line
/ F240 and a plurality of logic gates (AND gates) AN for controlling the application state of the selection signal to each of the gate lines X1 to X120 based on the output enable signal GRES1.
D1, AND2,... AND120, and each gate line X121 based on the output enable signal GRES2.
, And a plurality of logic gates AND121,..., AND2 for controlling the application state of the selection signal to X240
40. In addition, RESET
Are the flip-flop circuits F / F1, F / F2,.
And are common reset signals for simultaneously resetting the signals held in the F / F 240.

That is, each flip-flop circuit F / F
, F / F240 are connected to one input of each of logic gates AND1, AND2,..., AND240, and an output enable signal GRES1 is connected to logic gates AND1, AND2. , ...
The scanning signal is applied to the gate lines X1 to X120 formed in the upper half display area (upper display area) of the liquid crystal display panel by being connected to the other input of the AND 120, and the output enable signal GRES2
Are logic gates AND121, AND122,.
By being connected to the other input of the AND 240, a scanning signal is applied to the gate lines X121 to X240 formed in the lower half display area (lower display area) of the liquid crystal display panel.

Therefore, the flip-flop circuits F / F1,
, F / F120 (shift register) and logic gates AND1, AND2, ..., AND1
20 (first gate circuit) constitutes first drive signal generation means, and includes flip-flop circuits F / F121, F / F
, F / F 240 (shift register) and logic gates AND 121, AND 122,.
The ND 240 (second gate circuit) forms a second drive signal generation unit. The setting of the display area of the liquid crystal display panel in the present embodiment will be described later.

Here, although not shown, a plurality of flip-flop circuits F / F1, F
, F / F240 have a function of shifting the gate start signal GSRT in the forward direction, as in the prior art.
In addition, a function of shifting the gate start signal GSRT in the reverse direction is provided, and switching is appropriately controlled during the image display driving process. Further, the gate start signal GSRT, the gate clock signal GPCK, and the output enable signal GRES supplied to the gate driver according to the present embodiment
1, GRES2 are vertical control signals generated by the LCD controller 40.

Next, the setting of the display area of the liquid crystal display panel set by the gate driver will be described with reference to the drawings. FIG. 3 is a schematic diagram showing a display area setting of the liquid crystal display panel set by the gate driver according to the present embodiment. Here, description will be made with reference to the configuration of the above-described gate driver (FIG. 2).

In the gate driver 30 described above,
Single shift register (flip-flop circuit F / F
1, F / F2,..., F / F240) are sequentially shifted and output by the logic gates AND1 to A1.
ND120 and logic gates AND121 to AND24
0, the gate lines X1 to X120 and the gate lines X121 to X2
As shown in FIG. 3, the liquid crystal display panel has a configuration in which application is individually controlled to the gate line X1.
To X120, and a lower half display region (lower display region) Rd including gate lines X121 to X240, and the display driving process is executed. .

Here, as in the case of the above-described prior art, the liquid crystal display panel has a 3: 4 aspect ratio compatible with the NTSC system and displays a wide image Gw having an aspect ratio of 9:16. The wide image Gw
Is a central area of the screen, which is formed by compressing the image size according to the screen width of the liquid crystal display panel 10 while maintaining the aspect ratio of 9:16, and including the gate lines X31 to X210 extending over the upper display area Ru and the lower display area Rd. Will be displayed.

On the other hand, upper black band Bu and lower black band Bd above and below wide image Gw are gate lines X1 to X30 included in upper display region Ru and gate lines X211 to X240 included in lower display region Rd, respectively.
Are displayed in a band-like area consisting of In other words, the wide image Gw displayed in the region consisting of 180 lines of the gate lines X31 to X210 is output from the output enable signal GRE.
The display is driven by controlling both S1 and GRES2, and the upper black band Bu displayed in the region consisting of 30 lines of the gate lines X1 to X30 is display-driven by the output enable signal GRES1, and the gate line X is driven.
The lower black band Bd displayed in an area composed of 30 lines 211 to X240 is driven for display by the output enable signal GRES2.

According to the liquid crystal display device to which the gate driver having such a configuration is applied, the display area of the liquid crystal display panel is divided into an upper display area and a lower display area so as to correspond to each area. By dividing the logic gate and inputting different output enable signals, it is possible to individually control the display of the upper display area and the lower display area of the liquid crystal display panel. Therefore, as described later, when the wide image Gw is displayed, the process of selecting and scanning the gate lines of the upper black band Bu region and the lower black band Bd region is partially performed by selecting the gate lines of the wide image Gw. Since the scanning process can be performed at the same time as the scanning process (simultaneously), the selection of the gate line in the black belt region and the number of scanning processes in the flyback period can be reduced, and the shift operation in the gate driver is required. The number of shift clocks can be reduced.

Next, a display driving method of a liquid crystal display device to which the gate driver according to the present embodiment is applied will be described with reference to the drawings. FIG. 4 shows screen scanning states in screen scanning steps S11 to S13 when a wide image having an aspect ratio of 9:16 is displayed on a liquid crystal display panel having an aspect ratio of 3: 5 in the liquid crystal display device according to the present embodiment. FIG. 5 is a schematic diagram schematically showing a screen scanning state in screen scanning steps S14 to S17. Here, the configuration of the above-described gate driver (FIG. 2) will be described with appropriate reference.

<Step S11> In the gate driver 30 having the above-described configuration, first, the output enable signals GRES1 and GRES2 are switched to the active level (low level), and while the output enable signals GRES1 and GRES2 are held, the input of the flip-flop circuit F / F1 is maintained. A gate start signal GSRT is input to a terminal IN, and a flip-flop circuit F / F
1, F / F2,..., The gate pulse clock G
While sequentially shifting based on the timing of the PCK, the selection signal is output to each of the logic gates AND1, AND2,..., And as shown in FIGS. Set to the selected state sequentially. Here, in step S11, the number of shift operations executed by the flip-flop circuits F / F1, F / F2,... To output the selection signal is 31 times.

<Step S12> Next, at the timing when the gate line X31 is selected, the output enable signal GRES1 is switched to the off level (high level), and the image signal having the aspect ratio of 9:16 is supplied via the source driver 20. Is applied to each signal line. As a result, the scanning signal is applied from the logic gate AND31 to the gate line X31, and the signal voltage applied to the signal line is supplied to the liquid crystal pixels connected to the gate line X31. Row) is written and displayed.

Then, while the output enable signal GRES1 is held at the off level (high level), the scanning signal is applied by selecting from the gate line X31 to X120 at which the upper display area ends, while sequentially shifting in the forward direction. 4 by applying a signal voltage based on an image signal to each gate line by the source driver 20.
As shown in (c), the upper half image of the wide image Gw is sequentially displayed.

<Step S13> Next, at the timing when the gate line X121 enters the selected state, the output enable signal GRES1 is switched to the active level (low level), and the output enable signal GRES2 is switched to the off level (high level) and held. In this state, the gate lines subsequent to X121 are sequentially selected while sequentially shifting in the forward direction, and a scanning signal is applied. As a result, as shown in FIG. indicate.

The gate line X210, which is the lowermost row (180th row) of the lower half image of the wide image Gw.
The gate start signal G is input to the input terminal IN of the flip-flop circuit F / F1 every other line at the timing when the gate line X181 that is 30 lines higher than the selected line becomes the selected state.
The flip-flop circuits F / F1 and F / F1 are input in synchronization with the operation of inputting the SRT and selecting the gate line X181 and thereafter.
F2,..., And sequentially outputs a selection signal every other line to logic gates AND1, AND3,..., As shown in FIG.
Up to 30 odd lines (X1, X3, X5,..., X
29 (15) are selected.

<Step S14> Next, at the timing when the gate line X211 is selected, the output enable signal GRES1 is switched to the off level (high level), and the output enable signal GRES2 is switched to the active level (low level) and held. As a result, as shown in FIG. 5A, the gate lines X1 to X29 (X1,
X3, X5,..., X29) are applied with a scanning signal, and the source driver 120
A signal voltage based on the image signal (black signal) of the upper black band Bu is applied to each signal line. As a result, in the upper black band Bu region from the gate lines X1 to X30, black data is written to the liquid crystal pixels connected to the odd lines.

<Step S15> Next, with the output enable signal GRES1 held at the off level (high level), the odd lines (X1, X3, X5,..., X29) from the gate lines X1 to X30 are applied. .. Are shifted once in the reverse direction at once, as shown in FIG. 5B, so that even-numbered lines (from gate lines X1 to X30) X2, X4, X6,..., X30), a scanning signal is applied, and a signal voltage based on the image signal (black signal) of the upper black band Bu is supplied via the source driver 20. Is applied to each signal line.

As a result, the gate lines X1 to X30
In the upper black band Bu region up to, black data is written to the liquid crystal pixels connected to the even lines. Here, in step S15, the gate lines X1 to X30
The gate lines selected in the upper black band Bu region up to 15 are even-numbered lines, but the flip-flop circuits F / F1, F / F2,.
Is performed only once.

Therefore, in addition to the above-mentioned fifteen odd-numbered lines, the black data is also written to the fifteen even-numbered gate lines.
0 (the gate lines X1 to X
30) is displayed in black. The shift operation is reset by inputting the reset signal RESET to the flip-flop circuits F / F1, F / F2,... At the timing when the display of the wide image Gw and the upper black band Bu is completed.

<Step S16> Next, the output enable signal GRES1 is switched to the active level (low level), the output enable signal GRES2 is switched to the off level (high level), and one line of the gate pulse clock GPCK is held. The gate start signal GSRT is input to the input terminal IN of the flip-flop circuit F / F240 at every other timing, and the flip-flop circuits F / F240, F / F239,.
, And sequentially shifts in the reverse direction on the basis of the timing of the gate pulse clock GPCK, and changes the selection signal every other line to the logic gates AND239, AND237,.
To the gate line X as shown in FIG.
Odd lines from 240 to X211 (X239, X2
37, X235,..., X211), a scanning signal is applied, and a signal voltage based on the image signal (black signal) of the lower black band Bd is applied via the source driver 20 to each signal. Apply to signal line.

As a result, the gate lines X211 to X2
In the lower black band Bd region up to 240, black data is written to the liquid crystal pixels connected to the odd lines. Here, in step S16, this gate line X21
Although only 15 odd-numbered gate lines are selected in the lower black band Bd region from 1 to X240, the flip-flop circuit F
/ F240, F / F239,... Are shifted 30 times.

<Step S17> Next, with the output enable signal GRES1 held at the active level (low level) and the output enable signal GRES2 held at the off level (high level), the odd numbers of the gate lines X240 to X211 are held. Line (X239,
X237, X235,..., X211), flip-flop circuits F / F240, F / F239,.
By shifting once once in the forward direction at once,
As shown in (d), the gate lines X211 to X24
0 even lines (X212, X214, X216,
,..., X240) are selected, a scanning signal is applied, and via the source driver 120,
A signal voltage based on the image signal (black signal) of the lower black band Bd is applied to each signal line.

As a result, the gate lines X211 to X2
In the lower black band Bd area up to 240, black data is written to the liquid crystal pixels connected to the even lines. Here, in step S17, this gate line X21
The number of gate lines selected in the lower black band Bd region from 1 to X240 is fifteen even-numbered lines, but the flip-flop circuit F / F2
, The shift operation executed by the F / F 212 is only one time.

Therefore, in addition to the above-mentioned fifteen odd-numbered lines, black data is written into fifteen even-numbered gate lines.
0 (the gate lines X211 to X2).
240) is displayed in black. Then, at the timing when the black data is written to the liquid crystal pixels connected to the even lines,
By switching both the output enable signals GRES1 and GRES2 to the active level (low level), the application of the scanning signal to each gate line is cut off to reset the selected state.

The above-described series of display driving processes S11 to S17
Is repeatedly performed with a predetermined period as one cycle. In the display driving process, during the flyback period in which the wide image Gw is not displayed, black bands of the upper black band Bu and the lower black band Bd are displayed. In a series of display driving processes,
The shift operation when selecting the gate line X1 in step S11 and the shift operation when selecting the even-numbered lines of the gate lines X211 to X240 in step S17 can be performed simultaneously.

Therefore, in the above-described series of display driving processes, when the shift operation in step S11 and the shift operation in step S17 are performed simultaneously, the gate lines of the upper black band Bu and the lower black band Bd are changed during the retrace period. The shift operation required for display driving is 6
This is twice (= 1 + 30 + 1 + 30), and the number of gate pulse clocks GPCK (shift clock) can be greatly reduced compared to the display drive processing shown in the related art.

According to the liquid crystal driving device and the driving method according to the present embodiment, when a wide image having a 9:16 aspect ratio is displayed on a liquid crystal display panel having an aspect ratio of 3: 4, the upper display is performed. When displaying a wide image in either the area or the lower display area,
Since the upper black band Bu or the lower black band Bd included in the other display region can be displayed in black, the process of selecting and scanning the gate line of the black band region is partially performed by selecting the gate line of the wide image, The scanning can be performed simultaneously (simultaneously) with the scanning process, and the selection is performed in the gate driver by reducing the number of scanning processes (the number of shifts) of the selection of the gate line in the black belt region during the retrace period. The number of shift clocks required for the operation can be reduced.

Therefore, the frequency of the shift clock supplied to the gate driver can be set low, so that the wiring width of the clock line is increased to reduce the impedance of the clock line as shown in the prior art. It is not necessary to make the device thicker, and the size of the device can be sufficiently reduced when the scan driver is integrated. Further, since the frequency of the shift clock can be reduced, the size of the buffer circuit for outputting the shift clock can be reduced, and the power consumption can be reduced. In the embodiment described above,
A 9:16 liquid crystal display panel having a screen ratio of 3: 4
Although the case of displaying a wide image having a ratio of has been described, the present invention is not limited to this. In short, the present invention is also suitable for displaying an image having a ratio different from the screen ratio of the liquid crystal display panel. It goes without saying that it can be applied.

[0072]

According to the first or fifth aspect of the present invention,
In a liquid crystal driving device or a driving method for transmitting a driving signal for displaying an image having an aspect ratio different from the display screen size of the liquid crystal display panel, for example, a wide image, to the liquid crystal display panel, individual driving signal generating means is provided. By applying a drive signal (scanning signal) to the scan lines of the first display area and the second display area of the liquid crystal display panel, the first display area and the second display area of the liquid crystal display panel are individually For example, when a wide image is displayed on a liquid crystal display panel, an operation of selecting and scanning a gate line of a black band image displayed above and below the wide image is performed by a gate line of the wide image. Can be overlapped in time with the operation of selecting and scanning.

Therefore, the number of scan lines in the black band region and the number of scan processes (the number of shifts during the flyback period) can be greatly reduced, and the frequency of the shift clock required for the shift operation can be set low. In order to reduce the impedance of the clock line, it is not necessary to increase the width (thickness) of the wiring of the clock line, and the size of the buffer circuit for outputting the shift clock is reduced. The size can be sufficiently reduced, and the power consumption can be reduced.

According to the second aspect of the present invention, based on different control signals (output enable signals), driving signals (scanning signals) are supplied to the scanning lines of the first display area and the second display area of the liquid crystal display panel. ), The liquid crystal display panel has a simple configuration in which, for example, an existing gate circuit is divided into two groups, and the operation of each group of gate circuits is controlled by an individual control signal. Can be divided into a first display area and a second display area, and the display can be individually controlled.

According to the third aspect of the present invention, a part of the scan line of the first display area and a part of the scan line of the second display area of the liquid crystal display panel are selected at the same timing. As a result, the operation of selecting and scanning a gate line of a wide image displayed in one of the first display area and the second display area is performed, and at the same time, a gate of a black band image displayed in the other area is displayed. The operation of selecting and scanning a line can be executed, and the number of operations of selecting only a black band image (shift operation during a blanking period) can be substantially reduced.

According to the fourth aspect of the invention, the liquid crystal display panel has an aspect ratio of 3: 4, and an image having an aspect ratio of 9:16 is controlled to be displayed on the liquid crystal display panel. The configuration of each claim can satisfactorily control the display of a wide image and a black band image on an existing liquid crystal display panel having an aspect ratio corresponding to the NTSC system.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an overall configuration of a liquid crystal display device to which a liquid crystal driving device according to the present invention is applied.

FIG. 2 is a main part configuration diagram showing a gate driver applied to the liquid crystal driving device according to the embodiment.

FIG. 3 is a schematic diagram showing a display area setting of a liquid crystal display panel set by a gate driver according to the embodiment.

FIG. 4 shows screen scanning steps S11 to S13 when a wide image having an aspect ratio of 9:16 is displayed on a liquid crystal display panel having an aspect ratio of 3: 5 in a display driving process of the liquid crystal display device according to the present embodiment. It is the schematic which showed the screen scanning state typically.

FIG. 5 shows screen scanning steps S14 to S17 when displaying a wide image having an aspect ratio of 9:16 on a liquid crystal display panel having an aspect ratio of 3: 5 in the display driving process of the liquid crystal display device according to the embodiment. It is the schematic which showed the screen scanning state typically.

FIG. 6 shows a wide image having an aspect ratio of 9:16,
FIG. 9 is a schematic diagram showing a display area setting when displaying on a liquid crystal display panel having an aspect ratio of 3: 4.

FIG. 7 is a schematic configuration diagram illustrating a main configuration of a liquid crystal driving device for driving a liquid crystal display panel for display.

FIG. 8 is a main part configuration diagram showing a gate driver applied to a conventional liquid crystal driving device.

FIG. 9 is a schematic diagram schematically showing screen scanning states in conventional screen scanning steps S101 to S103 when a wide image having an aspect ratio of 9:16 is displayed on a liquid crystal display panel having an aspect ratio of 3: 5. is there.

FIG. 10 is a schematic diagram schematically showing screen scanning states in conventional screen scanning steps S104 to S106 when displaying a wide image having an aspect ratio of 9:16 on a liquid crystal display panel having an aspect ratio of 3: 5. is there.

[Explanation of symbols]

 Reference Signs List 10 liquid crystal display panel 20 source driver 30 gate driver 31 shift register 32 buffer 33 shift direction control circuit 40 LCD controller 50 system control IC 60 D / A converter F / F1-F / F240 flip-flop circuit AND1-AND240 logic gate Gw wide Image Bu Upper black band Bd Lower black band Ru Upper display area Rd Lower display area

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA20 NA22 NC09 NC16 NC22 NC90 ND34 ND39 5C006 AA01 AA22 AF35 AF42 AF72 AF82 BB14 BB15 BC12 BF03 BF06 BF26 FA08 FA15 FA47 5C080 AA10 BB05 CC03 DD26 FF11 GG08 JJ03

Claims (5)

[Claims] 1. A liquid crystal driving device for transmitting a driving signal for displaying an image on a liquid crystal display panel having a plurality of liquid crystal pixels arranged in a matrix near an intersection of a plurality of scanning lines and signal lines, A liquid crystal driving device, a first driving signal generation unit that applies the driving signal to the scan line in a first display area obtained by dividing the liquid crystal display panel in a horizontal direction, and the liquid crystal display panel is divided in a horizontal direction. And a second drive signal generating means for applying the drive signal to the scan lines in a second display area, while displaying a part of the image in the first display area,
A liquid crystal drive device, wherein a predetermined band image is displayed in an area included in the second display area and not displaying the image. 2. A shift register for sequentially shifting a predetermined start signal to generate and output the drive signal applied to the scan line at a predetermined timing, the shift register including: A first gate circuit for applying the drive signal output from the register to the scan line in the first display area based on a first control signal; A drive signal generation unit configured to apply the drive signal output from the shift register to the scan line in the second display area based on a second control signal; 2. The liquid crystal driving device according to claim 1, comprising: 3. The liquid crystal driving device according to claim 1, wherein the scanning line in the first display area and at least a part of the scanning line in the second display area are simultaneously selected. The liquid crystal driving device as described in the above. 4. The liquid crystal display panel has an aspect ratio of 3: 4, and the image displayed on the liquid crystal display panel is 9:16.
2. An aspect ratio as defined in claim 1,
4. The liquid crystal driving device according to any one of items 1 to 3. 5. A driving method of a liquid crystal driving device for transmitting a driving signal for displaying an image on a liquid crystal display panel having a plurality of liquid crystal pixels arranged in a matrix near an intersection of a plurality of scanning lines and signal lines. In the method, simultaneously with the step of displaying a part of the image in a first display area obtained by dividing the liquid crystal display panel in a horizontal direction, the area included in the second display area and in which the image is not displayed may be A method for driving a liquid crystal driving device, comprising a step of displaying a set band image.