JPS5883478A - Reception channel display circuit - Google Patents

Abstract

PURPOSE:To perform a clear reception channel display, by synchronizing a channel display signal with a sampling clock, through the use of a synchronizing circuit logically operating the output of a plurality of stages of D-FFs, in a television receiver using liuid crystal. CONSTITUTION:A pulse width signal (d) in which the pulse width is changed corresponding to the reception channel and which is obtained by applying a saw tooth wave and a tuning voltage to a voltage comparison circuit, is inputted to the 1st D-FF17 and an output signal Q1 of the D-FF17 is applied to the 2nd D-FF18. An output signal Q2' of the D-FF18 is applied to an NOR gate 19 together with the signal Q1 to obtain a channel display signal (f). After the signal is amplified, it is sampled with a sampling clock from a control signal generating circuit 14 at an A/D conversion circuit 11 and converted into a digital signal, and after the signal (f) is serial-parallel-converted at a signal electrode driving circuit 13 and displayed on a liquid crystal panel.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a λ reception channel display circuit for displaying an index representing a reception channel on a liquid crystal panel in a liquid crystal television.

The conventional circuit that displays the reception channel on the
J side Kj! Next II! I will clarify.

gtm is a block diagram showing an example of a conventional O channel display circuit for television reception using a cathode ray tube.

In the figure, 1 is an antenna, 2 is a block with an R-capacitance diode on the same board, black is a video detection circuit, 4 is a video detection circuit, 5 is a cathode ray tube, 6 is the same voltage generation circuit, and 7 8 is a sawtooth wave generation circuit that generates a single tooth wave synchronized with the horizontal 111-period signal, 8 is a pressure comparison circuit, and 9 is a differential Lg.
It is Jl&.

Further, FIG. jg2 is a tie chart for explaining the circuit operation of FIG. 1. 1 in the same figure is a horizontal synchronizing signal, Todoroki to C in the same figure are output signals of the parts shown with the same symbols in FIG. Width signal, - is channel display signal.

In the circuit shown in FIG. 311, the sawtooth wave output from the sawtooth wave generation circuit 7 and the tuning voltage Q output from the tuning voltage generation circuit 6 are applied at a voltage ratio IIIZ1gIj1!8. Then, the #electromotive voltage comparator circuit 8 outputs the pulse width old number d shown in FIG. Note that it is generally well known that this pulse width signal d can also be obtained by a separate hand JiRK.

As is clear from FIG. JII2, the pulse width signal d has a pulse width corresponding to the level change of the III voltage. Furthermore, the m-th pulse width correction code d is passed through a differentiator 9 to i
gl#, the channel display signal shown in Figure 2 can be obtained. Since this channel display signal is obtained by differentiating the falling edge of the pulse width signal d, its position changes depending on the reception channel.

FIG. 5 shows how the channel display signal is input to the video amplification circuit 4, superimposed on the video signal, amplified, and displayed on the cathode ray tube.

Next, regarding the channel display circuit of an LCD TV, Figure r
Explain a using Ev. Jei4#7A is a block diagram illustrating a conventional reception channel display circuit of an LCD TV. In the same figure, 10 is a circuit boot which includes all the circuits except for the cathode ray tube 5 from the purchased tFiAo diagram, 11 is an A/N R* device, and 12 is a circuit board.
Kmgm171E[, 15 is a power supply circuit, 14 is a control number 11 generation circuit, and 15 is a 1% IA matrix panel.

LCD mat! The scanning panel 15 has one ** region pole and important signal electrodes, and each electrode is controlled (controlled) by a scanning electrode and signal electrodes 12 and 13, respectively.

, When performing TV maw display (including reception channel display; the same applies hereinafter) on the G-crystal matrix panel 15,
As is well known, first, a video signal (including the reception channel display No. 1 added to the video signal; the same applies hereinafter) is input to the A//D converter 11 by a tsukutsuku pulse from the control signal generation circuit 14. (Sampling clock) K
% k-bit digital (It
Change the number K K.

Thereafter, the digital signal, ie, the digitized image 111! In the signal domain polar drive circuit 15, the scanning electrode 1IKIIb circuit 12 manually performs direct tL column conversion in response to the O output α pulse from the control signal generation circuit 14. Is the H signal generation circuit 14 synchronized with the alpha pulse? This is done by performing IiI sequential execution.

As described above, gsllg shows a vertical m feature indicating the receiving channel superimposed on the video signal and displayed on the liquid crystal matrix panel 15, that is, a portion of the receiving channel display.

In the conventional reception channel/channel display circuit of an LCD TV, the upper
As is clear from the description, the channel display signal shown in FIG.
The signal is sampled using a sampling clock from the il signal generation circuit 14 and displayed on the liquid crystal matrix panel 15. For this reason, if the above-mentioned ring clock and channel display signal are not synchronized, the receiving channel display may be disturbed as shown in FIG.

The edges of the channels were blurred, and I was often unable to clearly display the reception channel.

One aspect of the present invention is to eliminate the above-mentioned drawbacks and provide a reception channel display circuit for displaying a clear finger on the LCD panel in an LCD television. .

In order to achieve the purpose t-4 of the present invention, the eiki polarization code t-? The channel display signal should be synchronized with the sampling frequency.

In place of the conventional differential circuit, a synchronization path consisting of a plurality of stages of D-flip frogs and a logic-salt gate that outputs the output of the D-flip frog is used.

Hereinafter, the present invention will be explained in detail using 1111 planes.

FIG. 6 is a block diagram showing the essential parts of the reception channel display circuit of the present invention, that is, the details around the riiJ period. In the same case, 16 is an input terminal, 17 and 1
8 is @1 and 7g2 D7 rig 7ayg, 19 is N
0It gate, 20 is an inverter. In addition, recommendation 1
The same parts and the same parts as those in FIG. 4 and FIG. A and d in the figure are the same horizontal synchronizing signal and pulse width signal as 6 and d in FIG.

In addition, CP・ is m or a ivy pulse CP・ is inverter 2.
Inverted from 0&C and D7 litgraph a of %1 and 2
Tags 17 and 11 [input]. The check signal, Ql, is the signal output from the D7 lip-frog 17 of @1, Q
, are signals output from the D-flip 7a of the rattan 2, and f is a channel display signal output from the NOR gate 19.

The means for controlling the pulse width signal d described at 8 in FIG. 1 outputs a pulse width signal d whose pulse width changes in accordance with the receiving channel/channel. When the pulse 1 d is inputted to the D flip-flop 1 of Jiil through the input terminal 16, its output becomes the signal Q1 shown in FIG. 7, as described above.

The i1r signal Q is supplied to the N0It gate 19 and also to the second D7V gate 18. Therefore, as described above, the output of the second D7 receiver 7a is a nine-fold signal shown at 47-.

It is clear that when the l1tI period signals Q1 and Q are supplied to the NOR gate 19, its output becomes the channel display note f shown in FIG. 7, as described above.

Said channel display signal j is multiplied by a video intensifier md path 4 and then R-subjected to a digital signal by a '/n conversion -11 in the same manner as in the fourth LjlI,
The signal is serial-parallel converted in the signal processing circuit 15 and displayed on the liquid crystal display 15.

As is clear from the above description, in the present invention, the channel display signal f is converted into the received channel display signal itt by the clock pulse CP0 output from the 1111# signal angle 8: times jll14, and the received channel display signal itt Ng9
It is synchronized with the y data.

As a result, it is clear that according to the present invention, it is possible to display a dark channel on the liquid crystal panel without bending or blurring.In addition, in this embodiment, the falling edge of the pulse width signal is digitally As mentioned above, in order to generate the channel display signal t-,
A two-stage follower 11fi D7 7a tsugu was used.

As a result, the width of the vertical channel display (number of channels displayed) becomes very large. However, it is clear that by increasing the D71) y Gua Qg's N Dan Yi, the width of the Yong JIK reception channel display can be widened.

[Brief explanation of the drawing]

Figure 1 shows the conventional TV receiver of the Gurakun tube system (1 channel display, 1 route, 1 channel, 7J)
Figure Ii1 is a timing chart for explaining the circuit operation, Figure Hs is a diagram showing an example of channel display by the reception channel display circuit of Figure $1, and Ji14111 is a diagram showing an example of the conventional reception channel display circuit of an LCD TV. c.
Fig. 45 is a diagram showing the inside of the channel display by the circuit of Fig. 44, Fig. 6 is a block diagram showing one embodiment of the main part of the reception channel display circuit of the present invention, and Fig. 7 is
3 is a timing chart for explaining the operation of the circuit shown in the figure. 4...Wkts amplifier circuit 6...Identical voltage generation circuit 7...Sawtooth wave Ryusei circuit 8...Wax pressure Hiei circuit 11
...A/n'R^ device 12...Run range drive circuit 15...Signal power line drive circuit 14...Control signal generation circuit 15...Liquid crystal matrix panel 17-$ 1 D frijig 70yg 1B-$2 D7sy guastyg banknote 2 figure. Ol..., foil 5 figure I 4 figure blue! ! l”i5 figureYiIi7 figure

Claims (1)

[Claims] (1) means for outputting a pulse width signal synchronized with a horizontal synchronization signal and having a pulse width corresponding to the receiving channel; and generating channel display No. 1g from the pulse width signal;
and a channel display signal generating means for outputting the channel display O! A video signal amplification path for amplifying the Iv, an AA) R converter for converting the amplified channel display signal into a digital signal of VK bits, and a signal ° (poles S and A liquid crystal panel having a scanning electrode, and the digital signal inputted thereto, and the signal voltage value is set to 1I.
IJTs! By driving the signal electrode I111 line and the scanning electrode in an oxygen-deficient manner, 7I! The scanning f:'lE polar antagonizing circuit that performs the control, and the controlling m signal generation circuit that supplies the a-scanning pulse to each of the front transducer No. 14, the No. 41 electrode driving circuit, and the scanning electrode part m circuit. In the low-channel display circuit, the second channel display signal generating means is connected to several stages of D79 blocks 7&2 to which the pulse width signal is input, and from a logic gate that calculates the output of the D flip-flop. Then, the above D flip-flop is
1-* A receiving channel display circuit configured to be supplied with a tsuk pulse.