JPH02309317A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain the driving circuit for a large screen and high image quality by storing the digital video signals consisting of a series of picture element data of a prescribed number of bits successively by each one line into a shift register circuit and outputting the signals as analog video signals to source electrodes of the corresponding picture elements. CONSTITUTION:The digital video signals Vd consisting of a series of the picture element data of the prescribed number of bits are successively stored by one line each into the shift register circuit 2 and the picture element data for one line are outputted to and held in a latch circuit 3. A pulse width modulating circuit 4 executes the pulse width modulation of the respective sets of the picture element data for one line inputted from the latch circuit 3 and outputs the same as the analog video signal to the source electrodes of the corresponding picture elements of a thin-film transistor (TFT) array 9. The video signals are not inaccurate even if the writing time permitted for the picture element data is shortened by an increase in the number of the picture elements in the TFT array for the high screen and high image quality. In addition, the need for a costly decoder and driving voltage circuit is eliminated.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a method for driving a liquid crystal by supplying a video signal to a source line of an active matrix display device consisting of a thin film transistor (hereinafter abbreviated as TPT) array. The present invention relates to a drive circuit for a liquid crystal display device.

<Prior Art> Conventionally, as a driving circuit for this type of liquid crystal display device, a circuit as shown in FIG. 5 or FIG. 7, for example, is known. The drive circuit shown in FIG. 5 drives the shift register circuit 22 with the sampling clock C1 and the start pulse P from the timing generation circuit 21, and sequentially activates the zumbling gate low path 23 while the zumbling gate circuit The analog video signal Va input to 23 is 1
This is stored in the capacitor 24 (see FIG. 6) every horizontal scanning period, and then held by the capacitor 26 (see FIG. 6) of the latch gate circuit 25 that receives the latch pulse P from the timing generation circuit 21. The analog signal for one line is T I” in the next horizontal scanning period.
Each source line of the T-array 27 is simultaneously outputted via the output circuit 26, and the video signal Va of the next horizontal scanning period is taken into the sampling gate circuit 23 in parallel. On the other hand, T F '1'' array 27
A scanning pulse is outputted to each gate line from a gate drive circuit 28 that receives a control signal from a timing generation circuit 21, and thereby each pixel of the TFT array 27 is sequentially driven according to the video signal, and an image is generated. Is displayed.

In other words, as shown in FIG. 6, this drive circuit stores the input analog video signal Va in the zumbling gate circuit 23 based on the zumbling pulses P from the shift register circuit 22 line by line. Then, after receiving the latch pulse P, it is held by the latch gate circuit 25 and then outputted through the output circuit 26.

On the other hand, the drive circuit shown in FIG. 7 drives the shift register 2 with the clock C8 and outputs n+1 bits of pixel data P1.
One line of digital video signal Vd consisting of m sets (i=1-m) of (Dn, -, Do) is sequentially stored, and then held by latch 3 that receives latch pulse P. , the held digital signals of 1912 minutes are each converted into an analog signal by the decoder 31 in the next one horizontal scanning period, and the externally supplied voltage value V is determined according to the conversion In. ,
...Select Vk and press 'r I? ' The video signal Vd for the next line is taken in in parallel to each source line of the T-array 27 at the same time.

<Problems to be Solved by the Invention> However, since the drive circuit shown in FIG.
As the number of pixels in one line increases as in the FT array 27, the sampling time allowed for one pixel data becomes shorter, and the capacitor 24 of the sampling gate circuit 23
There is a drawback that the charging time becomes insufficient and the video signal Va cannot be captured accurately, which deteriorates the display quality of the TF'L' array 27.

Further, the drive circuit shown in FIG. 7 converts each pixel data into an analog signal by the decoder 31, and outputs an externally supplied voltage value v0 according to the converted value. ..., Vn is selected and output to each source line, so it is possible to use a large screen and high quality T.
When the number of pixels and the number of bits of pixel data increase as in the F i' array 27, many decoders 31 and many voltage values are required, wiring etc. become complicated and the drive circuit becomes complicated and expensive. It has the disadvantage of becoming.

SUMMARY OF THE INVENTION An object of the present invention is to input a digital video signal that is not limited by sampling time to a drive circuit, and to provide a large screen with a simple and inexpensive configuration that does not require a decoder or drive voltage selection circuit.

It is an object of the present invention to provide a driving circuit for a liquid crystal display device that can sufficiently drive even a high-quality 'I' F T array.

Means for Solving the Problems> In order to achieve the above object, a driving circuit for a liquid crystal display device of the present invention drives a source line of an active matrix display device consisting of a thin film transistor array. A shift register circuit that sequentially stores digital video signals consisting of pixel data one line at a time, a latch circuit that holds the pixel data for each line that is input from this shift register circuit, and a latch circuit that holds the pixel data for each line, which is input manually from this latch circuit! It is characterized by being equipped with a pulse width modulation circuit that changes the pulse width of each line of pixel data and outputs it as an analog video signal to the source 71 pole of the corresponding pixel of the thin film transistor array at IAI L.

Function> A digital video signal consisting of a series of pixel data of a predetermined number of bits is sequentially stored line by line in a shift register circuit, and then one line of pixel data is output to a latch circuit and held. The pulse width modulation circuit performs pulse width modulation on one line of pixel data manually inputted from the latch circuit to determine the source of the corresponding pixel in the thin film transistor ('rl;'T) array. It is output as an analog video signal.

Therefore, in a large-screen, high-quality 'rFT array, the writing time allowed for one pixel data is shortened due to an increase in the number of pixels (
Even if this happens, the captured video signal will not become inaccurate unlike the conventional analog video signal input method, and the display quality of the TFT array will not deteriorate. Furthermore, since each pixel data from the latch circuit is pulse-width modulated and output as an analog video signal, there is no need for a complicated and expensive decoder or drive voltage circuit as in conventional digital video signal input systems.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of a drive circuit for a product display device according to the present invention, in which 1 is a timing generation circuit that receives a synchronization signal S and generates timing signals such as a clock C+ and a latch pulse Pr; receives the clock C1 and outputs n+I bits of pixel data Pi(Dn, .=, Do
3 is a shift register circuit which sequentially stores the digital video signal Vd for lines (3 is a shift register circuit 2 which receives the latch pulse Pr) (see FIG. 7). A latch circuit 4 holds one line of pixel data for one horizontal scanning period from this latch circuit 3. [The line of pixel data is generated by a timing generator 5 using a clock C+. This is a pulse width modulation circuit that performs pulse width variation R (PWM) based on the comparison signal C6.

Maruko, 6 is! a data inversion circuit that inverts the output signal of the pulse width modulation circuit 4 every field or one horizontal scanning period; 7 is a level shifter circuit that shifts the level of the output signal from the data inversion circuit 0; 8 is a level shifter circuit of the level shifter circuit 7; Convert the output signal to an analog operating voltage and convert it to Tl? An output circuit 12 supplies each source line 10.10 of the 'L' array 9, and receives a control signal C3 from a timing generation circuit 1 to scan each gate line [1, 11...] of the TFT array 9. This is a gate drive circuit that supplies pulses.

When the pixel data is, for example, 4 bits, the shift register circuit 2 receives m clocks C as shown in FIG.
1, one line of pixel data P 1 (Dn, -
, Do] (i=I-m), while the latch circuit 3 receives the latch pulse P' inputted when the storage is completed, and stores one line of stored pixel data from the shift register circuit 2. The pixel data is taken in and held for one horizontal scanning period, during which the shift register circuit 2 stores the next one line of pixel data.

As shown in FIG.
This is a 4-bit binary counter made up of delayed flip-flops 13 connected in series, which counts the clock CI input to the lowest flip-flop, and sends the counting result to a 4-bit comparison signal ct( Q*,...,Q,)
It is output to the pulse width varying WM circuit 4 as a pulse width variable WM circuit. Further, the pulse width modulation circuit 4 is formed by arranging m 4-bit comparators I4 in parallel, and each comparator 14 receives corresponding pixel data Pi(D, . . . ....

■], ) are compared with the comparison signals (C3,...,Q,), and when Pi is larger than C2, "same" is output, and when Pi is not larger than C1, "0" is output, respectively. It is output as the signal PO.In other words, the comparison signal C! is the clock CI
is incremented each time the image data is inputted by one, and when the image data becomes 21 or more, the output signal PO, which was previously "1", becomes 0", so the counting period of the timing generation circuit 5, which is a binary counter, increases. The above output signal PO for
The pulse duty of the output signal PO is uniquely determined by the ratio of the periods during which the is "Bi", and the pixel data is pulse width modulated.

Further, the data inverting circuit 6 includes the pulse width modulation circuit 4.
It consists of m exclusive OR gates 15 which receive each output J signal PO at one input terminal and receive a common polarity switching signal C4 from the timing generator 5 at the other input terminal.

Then, the polarity switching signal c4 hits 1 during the counting-circulation period (period for 24 clocks CI) of the timing generation circuit 5.
It is designed to alternately change from "1" to "0" every horizontal scanning period.Therefore, when the polarity switching signal C4 is "0", the pulse width modulated output signal PO is output as is. and when it is the same, it is inverted and output.

As shown in FIG. 4, the level shifter circuit 7 level-shifts each output signal whose pulse width has been changed 11 from the data inverting circuit 6 so as to match the dynamic range of the Tri'T array 9. The shifted signal is manually applied to the capacitor 17 via the resistor 16, and an analog voltage value corresponding to the pulse duty is applied to the capacitor 17.
Get to the terminal. In addition, the output circuit 8 includes each capacitor 17.
It consists of m voltage followers I8 that maintain and output a terminal voltage of .

The operation of the drive circuit of the liquid crystal display device having the above configuration will be described next.

m 4-bit pixel data Pi (D3..., D
1912 minutes of digital video signal V (l) consisting of = 1 to IM in a) is sequentially stored in the shift register circuit 2 in synchronization with the clock C1, and then the latch pulse Pr
The video signal Vd is taken into the receiving latch circuit 3 and held here for one horizontal scanning period, while the next one line of video signal Vd is stored in the shift register circuit 2 during this period. Each pixel data Pi held in the latch circuit 3 is converted into an output signal po having a pulse duty corresponding to the data by a pulse width modulation circuit 4 which receives a comparison signal C1 from a timing generator 5, and is converted into an output signal po having a pulse duty corresponding to the data. The received data is inverted every horizontal scanning period through a data inverting circuit 6, and is outputted to a level shifter circuit 7. Therefore, for example, the first pixel data P1 of the first line of pixel data is P, (
0, 0, 1, 1), the converted output signal 1) 0 corresponds to the I6 clock, and the last 3 clocks of the full width of the pulse J are "B" and the 13 clocks are "0". The duty of I6 is set to 6 pulses, which are directly outputted to the level shifter circuit 7, and the same pixel data P for the next line is generated.
, (0, 0, 1°l) output signal 1) O is "0" for 3 clocks of the above pulse and "0" for 13 clocks.
A pulse having a duty of 1 3 /I 6 is output to the level shifter circuit 7 . Next, the level shifter circuit 7 converts the above-mentioned output signal for one line from the data inverting circuit 6 into an analog operating voltage, and supplies it to each source line 10 of the T F'r array 9 via the output circuit 8.
,10. Supply to... On the other hand, Tl? 'V array 9
Each gate line I 1, 11 . ..., a scanning pulse is output from the gate drive circuit 12, and thereby T
Each pixel of the FT array 9 is sequentially driven in accordance with the above operating voltage, and image features are displayed.

In this way, in the above embodiment, the digital video signal V
d for one line is directly stored in the shift register circuit 2, held in the latch circuit 3 for I horizontal period, and each pixel data from the latch circuit 3 is converted into a pulse in the pulse width modulation circuit 4 with a simple configuration. Since analog video signals are obtained by width modulation, the time required to write each pixel data to the shift register circuit is shortened due to the large screen and high image quality of the Tr;'T array 9. Unlike the video signal input method, the written video signal will not be inaccurate.
TI? The display quality of the T-array 9 does not deteriorate, and the complicated and expensive decoder and drive voltage circuit required in the conventional digital video signal manual system are not required.

In addition, in the above embodiment, since the data inversion circuit 6 is provided to invert the pulse width modulated output signal every horizontal scanning period, the polarity is inverted as in the case of the conventional analog video one-image signal manual system. The TFT array 9 can be driven with alternating current without providing a separate circuit, and 'I' I? 'r's liquid crystal life can be extended. Furthermore, since the digital video signal is converted to analog in a staggered manner, there is no need to synchronize the input to the shift register circuit 2 with the horizontal scanning period, and it is possible to directly handle signals that have been digitally processed externally by non-interlace conversion, etc. Do it.

It goes without saying that the present invention is not limited to the illustrated embodiment.

<Effects of the Invention> As is clear from the above description, the drive circuit for a liquid crystal display device of the present invention stores a digital video signal consisting of a series of pixel data of a predetermined number of bits line by line in a shift register circuit, and stores this digital video signal line by line in a shift register circuit. After holding the pixel data for the I line in a latch circuit, it is pulse width modulated in a pulse width modulation circuit and output as an analog [J] video signal to the source electrode of the corresponding pixel of the thin film I/Runnostar array. Therefore, even if the writing time of human video signals becomes shorter due to the large screen size and high image quality of thin film transistor arrays, the written video signals will not become inaccurate as with the conventional analog video signal input method, and the LCD The display quality does not deteriorate, and the complicated and expensive decoder and drive voltage circuit required in conventional digital video input systems are no longer required, making it possible to reduce the cost of the drive circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the driving circuit of a liquid crystal display device of the present invention, FIG. 2 is a detailed diagram showing the shift register circuit etc. of FIG. 1, and FIG. 3 is a pulse width modulation diagram of FIG. 1. FIG. 4 is a detailed diagram showing the circuit etc., and FIG. 5 is a detailed diagram showing the level shifter circuit etc. of FIG. 1. FIG. 6 is a block diagram showing a drive circuit for a conventional analog video signal input method, and FIG. 7 is a block diagram showing a drive circuit for a conventional digital video signal input method. T...Timing generation circuit, 2...Shift register circuit, 3...Latch circuit, 4
...Pulse width modulation circuit, 9...TFT array, +
0.10. ... Source line, 11, II... Gate line, 12... Gate drive circuit, Vd... Digital video signal. Patent applicant: Sharp Corporation Agent
Patent attorney Aohaku Ao and 1 other figure 2 ζ 4 4J 雫-1゜Figure 7

Claims (1)

[Claims] (1) In a drive circuit that drives a source line of an active matrix display device consisting of a thin film transistor array, there is a shift register circuit that sequentially stores a digital video signal consisting of a series of pixel data of a predetermined number of bits line by line, and this shift register circuit. A latch circuit holds one line of pixel data input from the latch circuit, and pulse width modulates the one line of pixel data input from this latch circuit to send an analog video signal to the source electrode of the corresponding pixel of the thin film transistor array. 1. A drive circuit for a liquid crystal display device, comprising a pulse width modulation circuit that outputs a pulse width modulation circuit.