JP2747326B2 - Drive circuit for liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a liquid crystal display device which drives a liquid crystal by supplying a video signal to a source line of an active matrix display device comprising a thin film transistor (hereinafter abbreviated as TFT) array. Related to a driving circuit.

<Prior Art> Conventionally, as a driving circuit of this type of liquid crystal display device, for example, a driving circuit as shown in FIG. 5 or FIG. 7 is known. Driving circuit shown in Fig. 5, by driving the shift register circuit 22 by the sampling clock C ₁ and a start pulse P ₁ from the timing generator 21, a sampling gate circuit
While sequentially activating 23, this sampling gate circuit
23 analog video signal Va one horizontal scanning period every the capacitor 24 to be input to the accumulated in (FIG. 6 reference), then the capacitor of the latch gate circuit 25 which receives the latch pulse P ₂ of this from the timing generating circuit 21 26 (see FIG. 6), the analog signals of one line held are simultaneously output to the source lines of the TFT array 27 via the output circuit 26 in the next one horizontal scanning period, and the next one horizontal scanning is performed. The video signal Va of the period is taken in parallel to the sampling gate circuit 23. On the other hand, a scan pulse is output to each gate line of the TFT array 27 from a gate drive circuit 28 that receives a control signal of the timing generation circuit 21,
Thereby, each pixel of the TFT array 27 is sequentially driven according to the video signal, and an image is displayed. That is, the driving circuit, as shown in FIG. 6, a video signal Va of the analog input, and stores the sampling gate circuit 23 based on the sampling pulse P ₃ from the shift register circuit 22 by one line, the filtrate was held at latch gate circuit 25 which receives the latch pulse P _2, than it outputs through an output circuit 26.

On the other hand, the driving circuit shown in FIG. 7 drives the shift register 2 by the clock C ₁ n + 1-bit pixel data Pi (D
n,..., D ₀ ) are sequentially stored for one line of digital video signals Vd consisting of m sets (i = 1 to m), and are then held by a latch 3 receiving a latch pulse P _2. , And the converted digital signals for one line are converted into analog signals by the decoder 31 in the next one horizontal scanning period, and the external supply voltage values V ₀ ,... Simultaneous output to the source line and video signal Vd for the next one line are taken in in parallel.

<Problems to be Solved by the Invention> However, since the driving circuit shown in FIG. 5 is a system for inputting an analog video signal Va, a TF having a large screen and high image quality is required.
When the number of pixels in one line increases as in the T array 27, 1
The disadvantage is that the sampling time allowed for one pixel data becomes short, the charging time of the capacitor 24 of the sampling gate circuit 23 becomes insufficient, the video signal Va cannot be taken in accurately, and the display quality of the TFT array 27 deteriorates. is there.

The drive circuit shown in FIG. 7 converts each pixel data into an analog signal by the decoder 31 and selects an external supply voltage value V ₀ ,..., Vn according to the converted value and outputs it to each source line. Large-screen, high-quality TFT array 27
When the number of pixels and the number of bits of pixel data increase as described above, many decoders 31 and many voltage values are required, so that wiring and the like become complicated, and the driving circuit becomes complicated and expensive.

Accordingly, an object of the present invention is to input a digital video signal, which is not restricted by the sampling time, to a drive circuit, and to realize a large-screen, high-quality image with a simple and inexpensive configuration that does not require a decoder or a drive voltage selection circuit. An object of the present invention is to provide a driving circuit of a liquid crystal display device which can sufficiently drive a TFT array.

<Means for Solving the Problems> In order to achieve the above object, a drive circuit for a liquid crystal display device of the present invention includes a series of predetermined circuits in a drive circuit for driving a source line of an active matrix type liquid crystal display device including a thin film transistor array. A shift register circuit for sequentially storing a digital video signal composed of pixel data of the number of bits line by line, a latch circuit for holding one line of pixel data input from the shift register circuit, and an input from the latch circuit A pulse width modulation circuit for performing pulse width modulation on each line of pixel data; a pulse width modulation signal output from the pulse width modulation circuit being level-shifted so as to conform to the dynamic range of the thin film transistor array; Input the shifted signal to the capacitor via the resistor. An output circuit comprising: a level shifter circuit for obtaining an analog voltage value corresponding to the pulse duty of the pulse width modulation signal; and a voltage follower for maintaining the analog voltage value output from the level shifter circuit and outputting the analog voltage value to a source line of a corresponding pixel. And characterized in that:

<Operation> A digital video signal composed of a series of pixel data of a predetermined number of bits is sequentially stored line by line in a shift register circuit, and then pixel data of one line is output to a latch circuit and held. The pulse width modulation circuit performs pulse width modulation on each line of pixel data input from the latch circuit, and outputs the result as a pulse width modulation signal. The level shifter circuit in the next stage shifts the level of the pulse width modulation signal so as to conform to the dynamic range of the thin film transistor array, and inputs the level shifted signal to a capacitor via a resistor to generate a pulse duty of the pulse width modulation signal. The corresponding analog voltage value is output. The output circuit at the subsequent stage maintains the output analog voltage value by a voltage follower and outputs the analog voltage value to the source line of the corresponding pixel.

<Example> Hereinafter, the present invention will be described in detail with reference to an illustrated example.

FIG. 1 is a block diagram showing an embodiment of a driving circuit of a liquid crystal display device according to the present invention. In FIG. 1, reference numeral 1 denotes a timing generation circuit which receives a synchronization signal S and generates a timing signal such as a clock C ₁ and a latch pulse Pr; 2 receives the clock C ₁ n
Shift register circuit for sequentially storing one line of digital video signal Vd composed of m sets (i = 1 to m) (see FIG. 7) of + 1-bit pixel data Pi (Dn,..., D ₀ ) Reference numeral 3 denotes a latch circuit which receives the latch pulse Pr and holds one line of pixel data from the shift register circuit 2 for one horizontal scanning period. 4 denotes one line of pixel data input from the latch circuit 3. and a pulse width modulation circuit for pulse width modulation (PWM) on the basis of the comparison signal C ₂ which is generated by the timing generator 5 by the clock C _1.

Reference numeral 6 denotes a data inversion circuit for inverting the output signal of the pulse width modulation circuit 4 every field or one horizontal scanning period, reference numeral 7 denotes a level shifter circuit for shifting the level of the output signal from the data inversion circuit 6, and reference numeral 8 denotes The output signal of the level shifter circuit 7 is converted into an analog operating voltage.
Each source line 10, 10, the output circuit supplies ... to the TFT array 9, 12 gate lines 11, 11 of the TFT array 9 receives a control signal C ₃ from the timing generating circuit 1, supplies the scan pulse to ... Gate drive circuit.

The shift register circuit 2 stores pixel data of, for example, 4
If it is a bit, then m clocks as shown in FIG.
In synchronization with the C ₁ 1 line of pixel data _{Pi (Dn, ..., D 0} )
(I = 1 to m) are sequentially stored while the latch circuit 3
Receives the latch pulse Pr input when storage is completed,
One line of stored pixel data is fetched from the shift register circuit 2 and held for one horizontal scanning period, during which the shift register circuit 2 stores the next one line of pixel data.

The timing generation circuit 5 includes, as shown in FIG.
Comprising four delayed flip-flop 13 are connected in series 4 is a binary counter of bits, counting the clock C ₁ inputted to the bottom of the flip-flop, the counting result of 4 comparison signal bits C ₂ (Q ₃ ,..., Q ₀ ) are output to the pulse width modulation circuit 4. Further, the pulse width modulation circuit 4
m 4-bit comparators 14 are arranged in parallel,
Each comparator 14 compares the corresponding pixel data Pi (D ₃ ,..., D ₀ ) input from the latch circuit 3 to one input terminal with the comparison signal (Q ₃ ,..., Q ₀ ). Pi is "1" is greater than C _2, Pi outputs "0" when not greater than C ₂ respectively as an output signal PO. That is, the comparison signal C ₂
Increments each time a clock C ₁ is input one and which is equal to or higher than the image data Pi, because the output signal PO which was an "1" to "0", serving as the binary counter timing generator circuit 5 The pulse duty of the output signal PO is uniquely determined by the ratio of the period during which the output signal PO is "1" to the counting cycle period, and the pixel data is pulse width modulated. Furthermore, the data inverting circuit 6 receives the output signals PO of the pulse width modulation circuit 4 to one input terminal, the other input terminal of the common from the timing generator 5 polarity switching signal C ₄ to receive the m An exclusive OR gate 15 is provided. Then, the polarity switching signal C ₄ is, inter counting one循期timing generating circuit 5 every (2 periods of ^four of the clock C ₁₎ i.e. one horizontal scanning period "1" alternately changes to "0" It has become. Therefore, the pulse width modulated output signal
PO is, when the polarity switching signal C ₄ is "0", is output as it is, when it is "1" is inverted and outputted.

As shown in FIG. 4, the level shifter circuit 7 converts each pulse width modulated output signal from the data inverting circuit 6
The level is shifted so as to conform to the dynamic range of the TFT array 9, the level-shifted signal is input to the capacitor 17 via the resistor 16, and an analog voltage value corresponding to the pulse duty is obtained at the terminal of the capacitor 17. The output circuit 8 includes m voltage followers 18 that maintain and output the terminal voltage of each capacitor 17.

The operation of the driving circuit of the liquid crystal display device having the above configuration will be described below.

m pieces of 4-bit pixel data Pi (D ₃ ,..., D ₀ ) (i =
1-m) for one line of digital video signal Vd
Are sequentially stored in the shift register circuit 2 in synchronization with the clock C _1, then latch circuit 3 which receives the latch pulse Pr
The video signal Vd for the next one line is stored in the shift register circuit 2 during this period. Each pixel data Pi held in the latch circuit 3 is a comparison signal from the timing generator 5.
Is converted by a pulse width modulation circuit 4 for receiving a C ₂ to the output signal PO having a pulse duty corresponding to the data, the polarity switching signal subjected to C ₄ data inverter 6 is inverted through in every horizontal scanning period a level shifter circuit 7 Is output to
Therefore, for example, when the first pixel data P ₁ of the pixel data of the first one line is P ₁ (0, 0, _{1, 1} ), the converted output signal PO is the pulse width of the pulse corresponding to 16 clocks. A pulse having a duty of 3/16, in which three clocks are "1" and 13 clocks are "0", is output to the level shifter circuit 7 as it is, and the same pixel data P ₁ (0, 0, 1,
The output signal PO of 1) is output to the level shifter circuit 7 as a pulse having a duty of 13/16 in which three clocks obtained by inverting the above pulse are "0" and 13 clocks are "1". Next, the level shifter circuit 7 outputs the data inversion circuit 6
Are converted into analog operating voltages and supplied to the source lines 10, 10,... Of the TFT array 9 via the output circuit 8. On the other hand, a scan pulse is output from the gate drive circuit 12 to each of the gate lines 11, 11,... Of the TFT array 9, whereby each pixel of the TFT array 9 is sequentially driven according to the operation voltage, and an image is displayed. Is done.

Thus, in the above embodiment, the digital video signal
Vd is directly stored in the shift register circuit 2 line by line, and this is held by the latch circuit 3 for one horizontal period, and each pixel data from the latch circuit 3 is pulsed by the pulse width modulation circuit 4 having a simple configuration. Since an analog video signal is obtained by performing width modulation, the conventional analog video signal can be used even if the time required to write each pixel data to the shift register circuit becomes short due to the large screen and high image quality of the TFT array 9. The video signal written as in the input method does not become inaccurate,
The display quality of the T-array 9 is not degraded, and a complicated and expensive decoder and driving voltage circuit as in the conventional digital video signal input method are not required.

In the above embodiment, the data inverting circuit 6 is provided to invert the pulse-width-modulated output signal every one horizontal scanning period. Therefore, the polarity inverting circuit is used as in the case of the conventional analog video signal input method. Even if it is not separately provided, the TFT array 9 can be driven by AC, and the life of the liquid crystal of the TFT can be extended. Further, since the digital video signal is converted to analog, it is not necessary to synchronize the input to the shift register circuit 2 with the horizontal scanning period, and it is possible to directly handle the externally digitally processed signal by non-interlace conversion or the like. Can also.

It goes without saying that the present invention is not limited to the illustrated embodiment.

<Effect of the Invention> As is clear from the above description, the drive circuit of the liquid crystal display device of the present invention stores a digital video signal consisting of a series of pixel data of a predetermined number of bits line by line in a shift register circuit. After holding the pixel data for one line by the latch circuit, pulse width modulation by the pulse width modulation circuit, and level shifting the pulse width modulation signal by the next level shifter circuit so as to conform to the dynamic range of the thin film transistor array. Then, the voltage is converted to an analog voltage value corresponding to the pulse duty through a capacitor, and the analog voltage value is output as an analog video signal to a source line of each pixel while being maintained by a voltage filter of a subsequent output circuit. Therefore, since it is a digital signal input method, even if the writing time allowed for one pixel data is shortened due to an increase in the number of pixels in a large-screen, high-quality TFT array, it is captured as in the conventional analog video signal input method. The video signal does not become inaccurate and the display quality of the TFT array does not deteriorate. In addition, since each pixel data from the latch circuit is pulse width modulated and output as an analog video signal, a complicated and expensive decoder and drive voltage circuit as in the conventional digital video signal input method are not required, and the manufacturing cost is reduced. Can be reduced. Further, good image quality can be ensured without being affected by the capacitance of the liquid crystal pixel itself, the wiring resistance of the source line, and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a driving circuit for a liquid crystal display device according to the present invention, FIG. 2 is a detailed diagram showing a shift register circuit and the like in FIG. 1, and FIG. 3 is a pulse width modulation in FIG. FIG. 4 is a detailed diagram showing the level shifter circuit and the like in FIG. 1, FIG. 5 and FIG. 6 are block diagrams showing a conventional analog video signal input type driving circuit, and FIG. FIG. 10 is a block diagram showing a conventional digital video signal input type driving circuit. 1 timing generation circuit, 2 shift register circuit, 3 latch circuit, 4 pulse width modulation circuit, 9
… TFT array, 10, 10,… source line, 11, 11,… gate line, 12… gate drive circuit, Vd… digital video signal.

Claims (1)

(57) [Claims] 1. A drive circuit for driving a source line of an active matrix type liquid crystal display device comprising a thin film transistor array, comprising: a shift register circuit for sequentially storing a digital video signal composed of a series of pixel data of a predetermined number of bits line by line; A latch circuit for holding one line of pixel data input from the shift register circuit, a pulse width modulation circuit for pulse width modulation of one line of pixel data input from the latch circuit, and a pulse width modulation circuit The pulse width modulation signal output from the circuit is level-shifted so as to conform to the dynamic range of the thin film transistor array, and the level-shifted signal is input to a capacitor via a resistor, and the pulse duty of the pulse width modulation signal is Level to obtain analog voltage value according to A drive circuit for a liquid crystal display device, comprising: a shifter circuit; and an output circuit including a voltage follower for maintaining an analog voltage value output from the level shifter circuit and outputting the voltage to a source line of a corresponding pixel.