JPH01105667A - Average value data output circuit - Google Patents

Abstract

PURPOSE:To obtain the average value of a small error by equipping a first random number generating circuit to generate a random number, which is driven with a data clock, and a sampling signal generating circuit which generates a sampling control signal to thin out data based on an output from this first random number generating circuit. CONSTITUTION:An average value data output circuit has a first random number generating circuit 10, a second random number generating circuit 20 and a sampling signal generating circuit 40 as constitution to supply the sampling control signal to a sampling circuit 9. Then, the first random number generating circuit 10 generates the random number of a so-called (m)-system with being driven by a data clock CK from a clock input terminal 31 and the sampling signal generating circuit 40 generates the sampling control signal to thin out the data based on the output from this first random number generating circuit 10. The second random number generating circuit 20 is driven by a clock (horizontal synchronizing signal) HD of a horizontal period from a clock input terminal 32 and generates the random number of the (m)-system. Then, the initial value of the first random number generating circuit 10 is set by this random number.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to 1. an average value data output circuit that thins out video signal data and performs averaging for auto-iris control operation of a color video camera; It is.

B0 Summary of the Invention The present invention provides an average value data output circuit that thins out and averages data of a video signal, which thins out the data based on the output from a first random number generation circuit driven by a data clock, and , by setting the initial value of the first random number generation circuit by the output of the second random number generation circuit driven by a clock with an integral multiple of the horizontal period, random data thinning is performed with a simple configuration to eliminate errors. This is to obtain an average value with a small number of values.

C0 Conventional technology When processing digital video signals, it is often necessary to find the average level of one field, one frame (two fields), or several fields of video signals0 For example, the so-called auto iris of a video camera is When performing digitally, it is necessary to obtain field average data (or average data of several fields) of the video signal level as exposure amount data or incident light amount data.

Adding and averaging all pixel data to obtain such average value data involves problems such as the amount of calculation being too large and requiring a high-speed calculation circuit configuration, so it is necessary to reduce the amount of calculation in some way. It is desired to reduce the amount.

D0 Problems to be Solved by the Invention By the way, as a method to reduce the amount of calculation to obtain the above average value data, for example, before averaging, the image may be dulled using a digital low-pass filter, and then thinned out at equal intervals. There is a method of sampling the data, but it requires a digital filter, which increases the circuit scale and complicates the configuration.

It is also possible to thin out the video signal data regularly according to a predetermined pattern, but depending on the image content, the correlation between the thinned out data may become high, and there is a risk that an accurate value cannot be obtained as an average value. be.

The present invention has been made in view of these circumstances, and provides an average value that can obtain an average value with little error by thinning out random data independent of image content with a simple circuit configuration. The purpose is to provide data output circuits.

Means for Solving the E0 Problem In order to solve the above-mentioned problem, the average value data output circuit according to the present invention thins out and samples the data of n field periods (n is a natural number) of the video signal and outputs the average value. In the average value data output circuit that outputs data, there is a first random number generation circuit that is driven by a data clock to generate random numbers, and sampling control for thinning out the data based on the output from the first random number generation circuit. a sampling signal generation circuit that generates a signal; and a second random number generation circuit that is driven by a clock having an integral multiple of a horizontal period to generate a random number and sets an initial value of the first random number generation circuit using the random number. It is characterized by having

10 Effects Since the data is thinned out using the sampling control signal generated using the first and second random number generation circuits, 2
Dimension double image data can be thinned out randomly without depending on the image content, and the amount of calculation when calculating the average value can be reduced.

G. Embodiment FIG. 1 shows a schematic configuration of an auto-iris circuit constructed using an average value data output circuit according to an embodiment of the present invention.

In this FIG. 1, each input terminal IR, IC.

The IB is supplied with digital input signals of three primary colors, R (red), G (green), and B (blue) from, for example, a digital color video camera. These R,
G and B digital input signals are NAM (non-additive mixed)
The signal with the highest level is taken out by the circuit 2, and the vertical weighting is sent to the circuit 3. This vertical weighting circuit 3 takes into consideration that generally a bright sky is placed at the top of the screen, so that the video signal at the top of the screen is not subject to iris control.
Or it is to keep the weight low. The output signal from the vertical weighting circuit 3 is subjected to detection processing by a detection circuit 4, and then sent to a sampling circuit 9 for data thinning of the average value data output circuit according to the embodiment of the present invention. The data thinned out by this sampling circuit 9 is
The data is sent to the field averaging circuit 5 and averaged, thereby obtaining average value data for l fields, and sent to one input terminal (for example, a non-inverting input terminal) of the comparison circuit 6. The other input terminal (for example, inverting input terminal) 7 of this comparator 4 is supplied with reference voltage data v7 corresponding to a preset target value for iris control, and this setting data (control target value) ? Error data of the above-mentioned average data is sent to the iris drive control circuit 8 as iris correction data. The output from the iris drive control circuit 8 controls the iris mechanism (mechanical diaphragm mechanism using aperture blades, etc., or electro-optic conversion element whose light transmittance is electrically controlled) provided in the optical system of the video camera. The aperture mechanism used) is driven, and the field average data of the detected data becomes the set value (control target data vy).
It is controlled so that

Here, the average value data output circuit according to the embodiment of the present invention is as follows.
As a configuration for supplying a sampling control signal to the sampling circuit 9, a first random number generation circuit lO1, a second
random number generation circuit 20 and sampling signal generation circuit 40
The first random number generation circuit 10 is driven by the data clock CK from the clock input terminal 31 to generate so-called m-sequence random numbers, and based on the output from the first random number generation circuit 10, Sampling signal generation circuit 4
0 generates a sampling control signal for thinning out the data. The second random number generation circuit 20 receives a horizontal period clock (horizontal synchronization signal) HD from a clock input terminal 32.
is driven to generate m series of random numbers, and the initial value of the first random number generation circuit 10 is set by these random numbers.

Note that the data clock CK is a sampling clock for pixel data of a digital video signal.

Further, the second random number generation circuit 20 may generally be driven with a clock having an integral multiple of the horizontal period.

A more specific example of a configuration for supplying such a sampling control signal will be described with reference to FIG. 2.

In this FIG. 2, the first random number generation circuit 10 is
It has a 5-stage shift register formed by cascading five D-type flip-flops 11 to 15, and has Ex, OR(
Exclusive or 1. Exclusive OR) circuit 16 calculates the exclusive OR of the Q output of the third stage flip-flop 13 and the Q output of the fifth stage flip-flop 15, and calculates the By returning it to the input terminal, a 31-bit long m-sequence pulse is generated. A data clock CK from an input terminal 31 is used as a driving clock for each of the flip-flops 11 to 15 constituting this five-stage shift register. A circuit 40 that generates a sampling control signal based on the output from the first random number generation circuit 1° is composed of a NOR (NOR) circuit 41, an AND circuit 42, and a changeover switch 43. Each output from the circuit 42 is selected by a changeover switch 43 and sent to the sampling circuit 9 as a sampling control signal.

The second random number generation circuit 20 has a five-stage shift register formed by cascading five D-type flip-flops 21 to 25, and the fourth and fifth stages of the five-stage shift register.
Ex, OR circuit 26 that takes the exclusive OR of each output of each stage
The output from the output from the OR circuit 27, Ex which takes the exclusive OR of each output from the second stage and the third stage, and the output from the OR circuit 27 are
, an exclusive OR is performed by the OR circuit 28, and the result is returned to the input of the first stage of the shift register, thereby generating other m-series pulses having a length of 31 bits.

A horizontal periodic clock (horizontal synchronization signal) HD from an input terminal 32 is used as a driving clock for each of the flip-flops 21 to 25 of this shift register. Therefore, the output from the second random number generation circuit 20 is updated every horizontal period, and the output from each stage of the five-stage shift register is output from the flip-flop of each stage of the shift register of the first random number generation circuit 10. It is sent to each preset input terminal 11 to 15. Further, the horizontal period clock HD from the terminal 32 is sent via an inverter 33 to a 172 frequency divider consisting of a D-type flip-flop 34, and the Q output of this flip-flop 34 is divided into two horizontal periods and one horizontal period. This signal becomes a signal that alternately switches between "H" (high level) and "L" (low level) every period, and this signal causes the changeover switch 43 of the sampling signal generation circuit 40 to be activated.
is controlled to switch.

Here, 3 generated from the first random number generation circuit 10 is
The code sequence with a length of 1 bit is as follows. On the other hand, the NOR circuit 41 operates from the fifth stage to the second stage of the shift register of the first random number generation circuit 10.
The AND circuit 42 detects that the 4-bit output up to the fifth stage becomes "0000" and sets the output to "H".
For example, the 5-bit output from the first stage to the first stage is "110".
In this case, each detected bit pattern has the longest appearance interval (i.e., 31 bits) when the above 31-bit code sequence is repeatedly output. The 4-bit pattern has only the above 'oooo', and the other 4 bits are
In the bit pattern, the same pattern appears at intervals shorter than 31 bits. Also, in a 5-bit pattern, ooo
Any pattern other than "oo" can be selected; however, when the above 31-bit code sequence is repeated, the above "o"
The above-mentioned "11000" is selected as the 5-bit pattern that is farthest from the "ooo" pattern, that is, exists approximately in the middle of the 31-bit repetition interval.

Then, the changeover switch 43 switches between the output from the NOR circuit 41 and the output from the AND circuit 42 every horizontal period (every two horizontal periods) to produce the sampling control signal.

Next, a 31-bit long code sequence sequentially generated from the second random number generation circuit 20 according to the horizontal periodic clock HD is as follows, and this is repeatedly generated.

The consecutive 5 bits on this code sequence are sent as initial values to the 5 bits from the 5th stage to the 1st stage of the shift register of the first random number generation circuit 10, and are sent every horizontal period. Then, the consecutive five bits serving as the initial value are shifted one bit at a time along the code sequence.

Therefore, the horizontal direction (H direction) and vertical direction (■
The points (sample points) thinned out and sampled by the sampling circuit 9 with respect to the pixels arranged in the direction (direction) are, for example, like the circle mark (0) in FIG.

By the way, if you want to take the above average in units of one frame (two fields), supply an even/odd field switching signal to the logic circuit 36 through the terminal 35 in FIG.・Generates 5-bit initial value data that differs from each other depending on the odd field,
Different initial value data for each even/odd field is sent to each flip-flop 2 of the second random number generation circuit 20.
By sending data to preset terminals 1 to 25, the sample points on the screen may be made different between even and odd fields.

Note that the present invention is not limited to the above-mentioned embodiments. For example, each of the random number generation circuits 10 and 20 shown in FIG. An m-sequence pulse generation circuit or other random number generation circuit can be used, and the logic for generating the sampling control signal can also be set arbitrarily. Furthermore, it goes without saying that the average value data output circuit of the present invention can be applied not only to the auto iris circuit but also to an auto knee circuit and other video signal processing in which average value data is required. In addition,
Various modifications can be made without departing from the spirit of the invention.

H0 Effects of the Invention According to the average value data output circuit according to the present invention, since two-dimensional image data is thinned out by the sampling control signal generated using the first and second random number generation circuits, the image content is It is possible to perform random thinning of data without depending on the data using a simple circuit configuration, and the amount of calculation when calculating an average value is significantly reduced, and an average value with less error can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a schematic configuration of an auto iris circuit to which an average value data output circuit according to an embodiment of the present invention is applied, and FIG. Block circuit diagram showing a concrete example, 3rd
The figure is a schematic plan view showing a specific example of sample points on the screen. 1... Digital primary color signal input terminal 2..., NAM (non-additive mixing) circuit 3... Vertical weighting circuit 4... Detection circuit 5... Field averaging circuit 6... Comparator 8... Iris drive control circuit 9... Sampling circuit 10... First random number generation circuit 20... Second random number generation circuit 31... Data clock input terminal 32... Horizontal period clock input Terminal 40...Sampling signal generation circuit

Claims (1)

[Claims] In an average value data output circuit that thins and samples data of n field periods (n is a natural number) of a video signal and outputs average value data, a first circuit that is driven by a data clock and generates random numbers; a random number generation circuit; a sampling signal generation circuit that generates a sampling control signal for thinning out the data based on the output from the first random number generation circuit; and a sampling signal generation circuit that is driven by a clock having an integral multiple of the horizontal period to generate random numbers. and a second random number generation circuit that sets an initial value of the first random number generation circuit using the random number.