JPS6152508B2 - - Google Patents

Info

Publication number
JPS6152508B2
JPS6152508B2 JP55188223A JP18822380A JPS6152508B2 JP S6152508 B2 JPS6152508 B2 JP S6152508B2 JP 55188223 A JP55188223 A JP 55188223A JP 18822380 A JP18822380 A JP 18822380A JP S6152508 B2 JPS6152508 B2 JP S6152508B2
Authority
JP
Japan
Prior art keywords
ram
control circuit
signal
interrupt
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55188223A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57111624A (en
Inventor
Masaki Tsucha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP18822380A priority Critical patent/JPS57111624A/ja
Publication of JPS57111624A publication Critical patent/JPS57111624A/ja
Publication of JPS6152508B2 publication Critical patent/JPS6152508B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP18822380A 1980-12-27 1980-12-27 Priority controlling circuit Granted JPS57111624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18822380A JPS57111624A (en) 1980-12-27 1980-12-27 Priority controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18822380A JPS57111624A (en) 1980-12-27 1980-12-27 Priority controlling circuit

Publications (2)

Publication Number Publication Date
JPS57111624A JPS57111624A (en) 1982-07-12
JPS6152508B2 true JPS6152508B2 (enrdf_load_stackoverflow) 1986-11-13

Family

ID=16219921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18822380A Granted JPS57111624A (en) 1980-12-27 1980-12-27 Priority controlling circuit

Country Status (1)

Country Link
JP (1) JPS57111624A (enrdf_load_stackoverflow)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5556221A (en) * 1978-10-18 1980-04-24 Fujitsu Ltd Priority decision system

Also Published As

Publication number Publication date
JPS57111624A (en) 1982-07-12

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