JPS6152508B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a priority control circuit in an information processing device, and more specifically, to a priority control circuit that determines the priority of interrupt signals. Conventionally, in this type of priority control circuit, the priority was determined by hardware based on the mounting position and the like. For this reason, the priority order becomes fixed once the system is configured, and when the priority order is changed, the mounting position must be changed. Another drawback was that the length of the cable changes as the mounting position changes, requiring the creation of a new cable, which increases overhead costs. SUMMARY OF THE INVENTION An object of the present invention is to provide a priority control circuit that solves the above-mentioned drawbacks. In order to achieve the above object, the priority control circuit according to the present invention is a priority control circuit for an information processing device that determines the priority order of interrupt signals, and includes a latch circuit that holds a large number of interrupt signals, and a latch circuit that holds a large number of interrupt signals. It has a RAM that stores information for determining the priority of each interrupt signal, and a large number of interrupt signal output lines weighted according to the priority, and the RAM
a decoder circuit that decodes information from the RAM and outputs an interrupt signal to a corresponding output line; a control circuit that can write information for determining priorities to an arbitrary address of the RAM; It is equipped with a latch circuit output when reading information, and a selector that selects an address from the control circuit when writing information to RAM, and is configured so that priorities can be arbitrarily set for multiple interrupt signals. It has been done. According to the above configuration, the priority order can be easily changed and the object of the present invention can be completely achieved. Hereinafter, the present invention will be explained in more detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a priority control circuit according to the present invention. In FIG. 1, 1 is a group of interrupt signals, 2 is a latch circuit for holding the 1 interrupt signal group, and 3 is an output signal from the latch circuit 2. 4 is output signal 3
A signal selector 5 is an output signal from the selector 4 and is connected to the RAM 6, and becomes an address of the RAM 6. 7
is read data from RAM6 and decoder 8
It is connected to the. 9 is an output signal of the decoder 8, and the interrupt signal with the highest priority is output.
The output signal 9 is also connected to a control circuit. 10
is the aforementioned control circuit, which controls the latch circuit 2, selector 4 and RAM 66. 15 is a control signal for the latch circuit 2, and 13 is an address signal for storing data in the RAM 6. 11 is a switching signal for the selector 4, 14 is write data to the RAM 6, and 12 is a control signal for writing to the RAM 6. Writing of the priorities into the RAM 6 is performed by the control circuit 10. That is, the RAM 6 receives information for determining priorities by switching the selector 4 to the address signal 13 by the switching signal 11, inputting the control signal 12, and writing the write data signal to the address given via the selector 4. Set. After setting as described above, the control circuit 10 changes the selector 4 from the address signal 13 to the address signal 3.
At the same time, switch RAM6 to control line 12.
Switch to read mode using . When the interrupt signal 1 is generated, the interrupt signal 1 is held in the latch circuit 2. The output signal 3 of the latch circuit 2 becomes the address signal 5 of the RAM 6 via the selector 4, and information is read from the RAM 6. Output data 7 from RAM 6 is output by a decoder circuit 8 with the highest priority relative to interrupt signal 1. FIG. 2 is a diagram showing the configuration of the RAM 6. The method of setting information in the RAM 6 in response to the interrupt signal 1 will be explained in more detail with reference to FIG. The output 9 of the decoder 8 is connected to a control circuit 10, and when an interrupt is received, the control circuit 10 controls the control signal 15 based on the information of the output 9, and activates the latch circuit 2 for the interrupt signal with the highest priority. Reset. From then on, this operation will be repeated. Here, if the number of interrupt signal lines is N, the RAM address is Z ^N and the bit width is (log ₂ N) + 1 (round up the decimal point).
The capacity of RAM6 is 2 ^N × (log ₂ H + 1). For example, if the number of interrupt signal lines is 8, a RAM capacity of 256×4 bits is required. In Figure 2, the number of interrupt signal lines is 4, the RAM capacity is 16 x 3 bits, and the priorities are set to interrupt signals 101, 102, and 10.
In this example, the numbers decrease in the order of 3,104.
Information for determining priorities based on the above conditions is set in the RAM 6. Interrupt signal 10
1 to 104 are each latched by the latch circuit 2. The latch circuit 2 has weighting, which is determined as shown in FIG. The output of RAM6 becomes the address of RAM6. For example, if interrupt signals 101 and 102 are latched by latch circuit 2, the address of RAM 6 is 3 _(
H) and reads the contents of address 3 _(H) . RAM6
Since 001 is written in address 3 _(H) ,
001 is read from RAM6. The outputs 108 to 111 of the decoding circuit 8 and read data correspond as shown below.

[Table] Therefore, as a result of decoding by the decoding circuit 8, an interrupt signal 108 is generated at the output of the decoding circuit 8, and the priority order is determined. When changing the contents of the RAM, the priority order for interrupt signals can be arbitrarily changed by the control circuit without changing the mounting position or the like. It is also a configuration that can determine priorities for combinations. As explained above, the present invention allows the priority order of interrupt signals to be changed arbitrarily, so there is no need to change the mounting position or change the cable length, which is required in the past. Ta.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a priority control circuit according to the present invention, and FIG. 2 is a detailed diagram of the RAM shown in FIG. 1. 1... Interrupt signal group, 2... Latch circuit, 3... Output signal of latch circuit 2, 4... Selector, 5... Output signal of selector 4, 6... RAM, 7... Read data from RAM 6, 8... Decode circuit, 9... Output signal of decode circuit 8, 10... Control circuit, 11... Switching signal, 12... Control signal to RAM 6, 13... Address signal, 14... Write data to RAM 6, 15...
Control signal to latch circuit 2, 101-104... Interrupt signal, 108-111... Interrupt signal after priority determination.

Claims (1)

[Scope of Claims] 1. In a priority control circuit of an information processing device that determines the priority of interrupt signals, a latch circuit that holds a plurality of interrupt signals provided from a plurality of interrupt signal input lines; a RAM having a plurality of memory locations assigned with addresses of the plurality of interrupt signals, each of which stores a code indicating one of the plurality of interrupt signal input lines; a control circuit capable of writing the code; and when reading the code from the RAM, the output of the latch circuit is used as the read address.
A selector for supplying the output of the control circuit to the RAM as a write address when writing the code to the RAM, and a plurality of interrupt signal output lines weighted with priorities, and reading from the RAM. A priority control circuit comprising: a decoder circuit that decodes the issued code and outputs an interrupt signal to the corresponding output line.